CN1928771A - Frequency regulation method and device for clock/data restoring circuit - Google Patents
Frequency regulation method and device for clock/data restoring circuit Download PDFInfo
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- CN1928771A CN1928771A CN 200610159321 CN200610159321A CN1928771A CN 1928771 A CN1928771 A CN 1928771A CN 200610159321 CN200610159321 CN 200610159321 CN 200610159321 A CN200610159321 A CN 200610159321A CN 1928771 A CN1928771 A CN 1928771A
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Abstract
The frequency adjustment method for clock/data recovery circuit comprises: when starting, an external device sends external data signal to a receiver according to operation frequency; the phase-lock loop of receiver outputs the transmission clock; the recovery circuit receives the clock according to the external signal; checking the frequency difference between receiver clock and transmission clock, and reducing the frequency of external signal if the difference over threshold.
Description
Technical field
The present invention is relevant for a kind of method of adjustment and its device of frequency, particularly relevant for a kind of method of adjustment and its device of frequency of clock/data recovery circuit.
Background technology
It is the data processing of concurrency that traditional interface standard-parallel advanced techniques connects (PATA, Parallel AdvancedTechnology Attachment), so wiring is many, winding displacement is but too short, the signal transmission is comparatively unstable, takes up space again, causes sizable inconvenience in the use.Therefore, consideration based on demands such as convenience, stability and operating frequencies, serial advanced technology connects (SATA, SerialAdvanced Technology Attachment) promptly developed into interface standard between system of new generation and the hard disk, and set the technical development blueprint in 10 years to reach the operating frequency of 6Gbps.
The SATA Related product of Tui Chuing belongs to SATA 1.0 specifications more in the market, and its operating frequency reaches 1.5GBps; The specification of the SATA II of a new generation, its operating frequency then can reach 3GBps.The product in this two generation all comes across on the present consumption market, and when the product in this two generation interconnected with the transmission data, regular meeting was because operating frequency difference and generation problem.For example, when the device of a SATA 1.0 as receiver, and the device of a SATA II as transmitter when transmitting data to receiver, because the operating frequency difference of this two devices, frequency junior's (being receiver) clock internal/data recovery circuit can remove to follow the operating frequency of transmitter.After after a while, the frequency of clock data/restoring circuit has surpassed its exercisable scope, in addition locked to transmitter operating frequency and can't get back to self frequency.
When the specification of SATA is in generation alternately the time, the connection between the device in different generations certainly will have the different problem of operating frequency, how to avoid occurrence frequency to disperse causing the acceptor device can't normal operation, is the problem that product designer is needed solution badly.
Summary of the invention
In view of this, the present invention proposes a kind of method of adjustment of frequency of clock/data recovery circuit, is applicable to an acceptor device that is connected with an external device (ED).After external device (ED) started, external device (ED) transmitted external data signal to acceptor device.Acceptor device comprises a phase-locked loop and a clock data recovery circuit.A transmitter clock is exported according to the operating frequency of acceptor device in the phase-locked loop, and clock/data recovery circuit is according to external data signal or transmitter clock generating one receiver clock.When the clock data recovery circuit was set in phase pattern, receiver clock was followed the transmitted frequency of external data signal, and whether the difference of the frequency of the frequency of inspection receiver clock and transmitter clock is greater than a threshold value.When this difference during, make this external device (ED) operate in the operating frequency of this acceptor device greater than this threshold value.
The present invention proposes a kind of acceptor device in addition, comprises a phase-locked loop, a clock/data recovery circuit, a frequency detector and a controller.To export a transmitter clock, clock/data recovery circuit receives external data signal, and exports a receiver clock according to the operating frequency of acceptor device in the phase-locked loop.When clock/data recovery circuit is positioned at phase pattern following time, receiver clock is followed external data signal, and when clock/data recovery circuit is positioned at frequency mode following time, receiver clock is followed the transmitter clock.Whether greater than a threshold value, controller is according to the testing result of the frequency detector pattern with the adjustment clock/data recovery circuit in order to the difference of the frequency that detects receiver clock and the frequency of transmitter clock for frequency detector.
The present invention proposes a kind of frequency adjusting method of acceptor device again, be applicable to an acceptor device that operates in one first operating frequency, this acceptor device is connected with an external device (ED), and adjust a receiver clock to receive an external data signal, this external device (ED) initial operation is in one second operating frequency.At first make receiver clock follow second operating frequency; Then detect receiver clock and whether be in a normal operation range; If yes, then make external device (ED) operate in first operating frequency; If then receiver clock continues to follow second operating clock not.Wherein receiver clock is followed first operating frequency when acceptor device does not connect this external device (ED).
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail as follows:
Description of drawings
Fig. 1 represents the calcspar according to acceptor device of the present invention.
Fig. 2 represent according to first embodiment of the invention the process flow diagram of method of adjustment of frequency.
Fig. 3 represents the process flow diagram according to the method for adjustment of the frequency of second embodiment of the invention.
The main element symbol description
10: receiving end
110: the phase-locked loop
120: clock data recovery circuit
130: frequency detector
140: controller
150: reset controller
Embodiment
The present invention proposes a kind of method of adjustment of frequency of clock data recovery circuit, is applicable to that one has the acceptor device of first generation SATA interface.For example, in South Bridge chip, increase frequency that a frequency detector checks clock/data recovery circuit whether because of the transmission frequency of following external data signal so that disperse.In addition, the present invention proposes the method for adjustment of the frequency of another kind of clock data recovery circuit again, utilizes the controller of acceptor device to switch clock/data recovery circuit between frequency mode and phase pattern, disperses with the frequency of prevention clock data recovery circuit.
Please refer to Fig. 1, it is the calcspar of the acceptor device of a preferred embodiment of the present invention.One has the acceptor device 100 of first generation SATA interface, a South Bridge chip for example, and it operates in one first operating frequency (as 1.5Gbps) to receive an external data signal continuously.One external device (ED) 20 with second generation SATA interface can operate in first operating frequency and one second operating frequency (as 3Gbps), and wherein first operating frequency is lower than second operating frequency.After external device (ED) 20 started, external device (ED) 20 transmitted external data signal to acceptor device 100 with second operating frequency.
Acceptor device 100 comprises a receiving end 10, a phase-locked loop 110, a clock/data recovery circuit 120, a frequency detector 130 and a controller 140.Receiving end 10 makes acceptor device 100 to handle external data signal in order to receive external data signal continuously.Phase-locked loop 110 according to first operating frequency of acceptor device 100 to export a transmitter clock TxClk.Clock/data recovery circuit 120 receives external data signal, and exports a receiver clock RxClk.When clock/data recovery circuit 120 is positioned at phase pattern (Phase Mode) following time, receiver clock RxClk follows the phase place and the correspondence of external data signal and adjusts frequency; When clock/data recovery circuit 120 is positioned at frequency mode (Frequency Mode) following time, receiver clock RxClk follows the frequency of transmitter clock TxClk.Frequency detector 130 in order to the difference of the frequency of the frequency that detects receiver clock TxClk and transmitter clock RxClk whether greater than a threshold value.Controller 140 according to the testing result of receive frequency detecting device 130 to switch this clock/data recovery circuit 120 between phase pattern and frequency mode.
In addition, acceptor device 100 comprises that also a reset controller 150 disperses in order to the frequency of avoiding clock/data recovery circuit.When the difference of the frequency of the frequency of receiver clock RxClk and transmitter clock TxClk during greater than a threshold value, reset controller 150 outputs one reset signal Reset resets acceptor device 100.
How the acceptor device 100 that below will illustrate further the embodiment of the invention reaches the purpose of adjusting frequency.When acceptor device 100 is not connected to external device (ED) 20 as yet with the reception data-signal, clock/data recovery circuit 120 produces receiver clock RxClk, i.e. first operating frequency of acceptor device 100 according to the frequency (1.5Gbps) of the transmitter clock TxClk of phase-locked loop 110.This receiver clock RxClk is for giving each element of acceptor device 100 as operating frequency.
Because acceptor device 100 has clock generator so that operating frequency separately to be provided separately with external device (ED) 20, in acceptor device 100 ends is phase-locked loop 110, therefore when acceptor device 100 is connected with data signal with external device (ED) 20, must make both clock frequencies synchronous earlier, so external data signal can normally transmit.
When clock/data recovery circuit 120 under phase pattern, receiver clock RxClk can remove to follow the phase place of external data signal and frequency can correctly transmit data with locking operating frequency; When clock/data recovery circuit 120 under frequency mode, receiver clock RxClk can follow the operating frequency of acceptor device 100.Therefore, the present invention promptly utilizes the mode switch of clock/data recovery circuit to adjust frequency to disperse avoiding.
When acceptor device 100 was connected to external device (ED) 20, at first phase-locked loop 110 produced the transmitter clock TxClk of first operating frequency; At this moment, clock/data recovery circuit 120 is in frequency mode work down, and receiver clock RxClk follows transmitter clock TxClk, that is frequency is first operating frequency.Then controller 140 switches clock/data recovery circuits 120 to phase pattern, makes the phase place and the frequency of receiver clock RxClk locking external data signal, makes acceptor device 100 and the external device (ED) 20 can be synchronous.But because acceptor device 100 is the SATA interface arrangement in different generations with external device (ED) 20, therefore initial receiver clock RxClk can't be locked in the phase place and the frequency of external data signal, and clock/data recovery circuit 120 needs to improve relatively the frequency of receiver clock RxClk to catch up with external data signal.
When frequency detector 130 detects the difference during greater than a threshold value of learning adjusted receiver clock RxClk and transmitter clock TxClk, that is the operating frequency of acceptor device 100 is far below the operating frequency of external device (ED) 20, and then frequency detector 130 sends one and detects and disperse signal CDRDisperse to reset controller 150 and controller 140.Reset controller 150 receive detect disperse signal CDRDisperse after, promptly send a reset signal Reset to clock/data recovery circuit 120, clock/data recovery circuit 120 is restarted.Controller 140 is also dispersed signal CDRDisperse according to detecting, and switches to frequency mode after clock/data recovery circuit 120 restarts.
Clock/data recovery circuit 120 enters frequency mode to follow the frequency of transmitter clock TxClk again when restarting, then switch to phase pattern, and whether test can catch up with the frequency of external data signal again.Can't receive the response of acceptor device 100 in this process external device (ED) 20.If acceptor device 100 does not still have response after a period of time, that is clock/data recovery circuit 120 can't improve receiver clock RxClk to the second operating frequency, then external device (ED) 20 will reduce operating frequency to the first operating frequency, make receiver clock RxClk can tune to the frequency synchronous with external device (ED) 20, data-signal can normally transmit.
External device (ED) 20 is provided with the overtime time, and promptly said external device 20 is waited for the time that acceptor device 100 is responded.If surpass this overtime time, external device (ED) 20 learns that promptly acceptor device 100 can't catch up with second operating frequency, and then external device (ED) will reduce operating frequency to the first operating frequency automatically.Generally speaking, the overtime time of external device (ED) 20 is about 54 μ s.
Please refer to Fig. 2, it is the process flow diagram of method of adjustment of the frequency of first embodiment of the invention.At first, in step S210, clock/data recovery circuit 120 is under frequency mode, and transmitter clock TxClk are exported in phase-locked loop 110, and receiver clock RxClk follows first operating frequency of transmitter clock TxClk.In step S220, clock/data recovery circuit 120 is set in phase pattern.As discussed previously, clock/data recovery circuit 120 is under phase pattern, and receiver clock RxClk can remove to follow the transmitted frequency of external data signal, i.e. second operating frequency.
Then, in step S230, utilize frequency detector 130 whether to detect the difference of receiver clock RxClk and transmitter clock TxClk greater than a threshold value, for example 15Mbps.Because receiver clock RxClk need follow the external data clock, but make external device (ED) 20 data signal, so receiver clock RxClk must rise, make it can catch up with second operating frequency of external data clock to acceptor device 100.If the difference of the frequency of receiver clock RxClk and transmitter clock TxClk is greater than a threshold value, difference as clock/data recovery circuit 120 exercisable maximum frequencies and transmitter clock TxClk frequency, then clock/data recovery circuit 120 may be dispersed, and leads to errors.
As in step S230, the difference of receiver clock RxClk and transmitter clock TxClk is greater than this threshold value, expression clock/data recovery circuit 120 may be dispersed, then in step S240, frequency detector 130 outputs one detect disperses signal CDRDisperse to controller 140 and replacement detecting device 150.
Be connected in step S250, reset controller 150 is dispersed signal CDRDisperse according to detection and is sent a reset signal Reset to clock/data recovery circuit 120, and controller 140 is also dispersed signal CDRDisperse according to detection clock/data recovery circuit 120 is switched to frequency mode.At this moment, 20 of external device (ED)s restart because of clock/data recovery circuit 120 is in and can't obtain to respond.
In step S260, external device (ED) 20 is waited for a period 1, if clock/data recovery circuit 120 does not still have any response, then external device (ED) 20 is adjusted its operating frequency, make the external data frequency be reduced to first operating frequency, wherein this period 1 is the overtime time of external device (ED) 20.In this step, because clock/data recovery circuit 120 can't be worked under the second higher operating frequency, make receiver clock RxClk not chase after the external data frequency, therefore external device (ED) 20 corresponding its operating frequency to the first operating frequencies that reduce make receiver clock RxClk can follow the external data frequency.Then promptly enter step S270, the beginning data signal.
As in step S230, the difference of receiver clock RxClk and transmitter clock TxClk is not greater than this threshold value, expression clock/data recovery circuit 120 can be in the second higher operating frequency normal running, then enter step S270, make acceptor device 100 begin to read external data signal institute data carried by data.
The method of adjustment of the disclosed frequency of present embodiment increases by a frequency detector 130 and judges whether the frequency of clock/data recovery circuit 120 surpasses operating frequency one threshold value of acceptor device 100 in the acceptor device 100 with first generation SATA interface.The present invention only increases a spot of circuit area and number of gates in acceptor device 100 originally can reach the purpose that the frequency of preventing clock/data recovery circuit is dispersed.
In another embodiment of the present invention, whether frequency detector 130 can equal the frequency of transmitter clock TxClk in order to the frequency that detects receiver clock RxClk, disperses signal CDRDisperse to produce to detect.The detection of controller 140 receive frequency detecting devices 130 is dispersed signal CDRDisperse to switch clock/data recovery circuit 120 between phase pattern and frequency mode.Reset controller 150 is also dispersed signal CDRDisperse and exports a reset signal Reset and reset acceptor device 100 according to detecting.
How the acceptor device 100 that below will further specify present embodiment reaches the purpose of the adjustment of frequency.When two SATA generations, different devices interconnected with the transmission data, because the operating frequency difference of this two devices, the acceptor device of first generation SATA can't read the external data signal that external device (ED) transmitted of second generation SATA.Under this situation, the acceptor device 100 of present embodiment is higher than the operating frequency of himself if judge the operating frequency of external device (ED) 20, then order about external device (ED) 20 and reduce its operating frequency, acceptor device 100 and external device (ED) 20 can be operated under the identical operations frequency.
As above an embodiment is described, and clock data/restoring circuit 120 at first under frequency mode, makes receiver clock RxClk follow transmitter clock TxClk, and its frequency is first operating frequency; Then clock data/restoring circuit 120 switches to phase pattern, makes receiver clock RxClk follow external data signal.Because the operating frequency (second operating frequency) of external data signal is higher, so receiver clock RxClk will rise gradually.If detecting, frequency detector 130 learns that receiver clock RxClk and transmitter clock TxClk are different, that is the operating frequency of acceptor device 100 differs from the operating frequency of external device (ED) 20, and then frequency detector 130 sends one and detects and disperse signal CDRDisperse to controller 140 and reset controller 150.
Reset controller 150 receives after this detection disperses signal CDRDisperse, promptly sends a replacement Reset signal to clock data/restoring circuit 120, and clock data/restoring circuit 120 is restarted.In this process, external device (ED) 20 will lose the response of acceptor device 100, and wait for the overtime time, after if this overtime time finishes, acceptor device 100 does not have any response yet, and then external device (ED) 20 will reduce its operating frequency, makes acceptor device 100 can catch up with its operating frequency.
Controller 140 is also dispersed signal CDRDisperse according to detecting, and switches clock data/restoring circuit 120 to frequency mode in restarting the back, makes receiver clock RxClk follow transmitter clock TxClk again.Because external device (ED) 20 has reduced its operating frequency to the first operating frequency, after controller 140 switches to phase pattern with clock data/restoring circuit 120 again, receiver clock RxClk and external data signal are in first operating frequency equally, therefore clock data/restoring circuit 120 need not be adjusted the frequency of receiver clock RxClk, and external device (ED) 20 can normally transmit data with acceptor device 100.
Please refer to Fig. 3, it is the process flow diagram of method of adjustment of the frequency of second embodiment of the invention.At first, in step S310, clock/data recovery circuit 120 is under frequency mode, and transmitter clock RxClk are exported in phase-locked loop 110, and receiver clock RxClk follows first operating frequency of transmitter clock TxClk.After external device (ED) 20 starts, clock data/restoring circuit 120 is positioned under the phase pattern, receiver clock RxClk follows external data signal to adjust its frequency, shown in step S320.
Then, whether execution in step S330 utilizes the frequency of frequency detector 130 detection receiver clock RxClk identical with the frequency (1.5Gbps) of transmitter clock TxClk.If operating frequency second operating frequency of external device (ED) 20, receiver clock RxClk will adjust upward from the first original operating frequency, to follow external data signal.Under this situation, the frequency of receiver clock RxClk will differ from the frequency of transmitter clock TxClk.
In step S340, if receiver clock RxClk and transmitter clock TxClk are different, frequency detector 130 sends to detect disperses signal CDRDisperse to controller 140 and reset controller 150.
In step S350, reset controller 150 is dispersed signal CDRDisperse according to detection and is sent a reset signal Reset to clock/data recovery circuit 120, and controller 140 is also dispersed signal CDRDisperse according to detection clock/data recovery circuit 120 is switched to frequency mode.At this moment, 20 of external device (ED)s restart because of clock/data recovery circuit 120 is in and can't obtain to respond.
In step S360, external device (ED) 20 is waited for a period 1, if clock/data recovery circuit 120 does not still have any response, then external device (ED) 20 is adjusted its operating frequency, make the external data frequency be reduced to first operating frequency, wherein this period 1 is the overtime time of external device (ED) 20.In this step, because both operating frequencies of the device 100 of display receiver as a result that clock/data recovery circuit 120 is adjusted receiver clock RxClk and external device (ED) 20 are different, so external device (ED) 20 corresponding its operating frequency to the first operating frequencies of reduction.So acceptor device 100 can transmit data down in same operating frequency with external device (ED) 20, and to guarantee acceptor device 100 unlikely dispersing, data also can correctly transmit.Then promptly enter step S370, make acceptor device 100 begin to read external data signal institute data carried by data.
If among the step S330, external device (ED) 20 has reduced operating frequency to the first operating frequency, that is after receiver clock RxClk entered phase pattern, the external data signal frequency of being followed was identical with transmitter clock TxClk frequency, then directly enters step S370 and begins data signal.
Its difference of the embodiment of Fig. 2 and Fig. 3 is, in the embodiment of Fig. 2, if acceptor device can normal operation under the second higher operating frequency, then clock/data recovery circuit makes receiver clock RxClk continue to follow the frequency of external device (ED) with data signal.If acceptor device can't operate under higher second frequency, the operating frequency that then reduces external device (ED) is to cooperate acceptor device.Then relatively whether acceptor device is identical with the operating frequency of external device (ED) in the embodiment of Fig. 3, if both are different, then reduces the operating frequency of external device (ED); If both identical data that then normally transmit.
The operating frequency that goes to follow external device (ED) for fear of the frequency of the clock data recovery circuit of acceptor device causes dispersing, traditional practice is after the time of a fixed cycle acceptor device to be reset, and makes the frequency of clock/data recovery circuit get back to the operating frequency of acceptor device.Yet, repeatedly can cause the sensitivity of voltage oscillation controller (VCO) in the clock/data recovery circuit to descend to the acceptor device replacement.Acceptor device provided by the present invention suitably switches on clock/data recovery circuit between frequency mode and the phase pattern to be dispersed with the frequency that prevents clock/data recovery circuit.Compared to method in the past, method of the present invention is more simple, also can not reduce the sensitivity of voltage oscillation controller.Simultaneously, the method of adjustment of the frequency of data recovery circuit provided by the invention, be applicable to have different two devices, can effectively solve the problem that the frequency of clock/data recovery circuit that data transmission causes between this two devices is dispersed easily for the serial advanced technology connecting interface.
Though the present invention with preferred embodiment openly as above; right its is not that any those skilled in the art are under the situation that does not break away from the spirit and scope of the present invention in order to qualification the present invention; can change and modification, so protection scope of the present invention is as the criterion with the claim institute restricted portion that is proposed.
Claims (20)
1. the method for adjustment of the frequency of a clock/data recovery circuit, be applicable to an acceptor device that is connected with an external device (ED), this acceptor device comprises a phase-locked loop and a clock/data recovery circuit, a transmitter clock is exported according to the operating frequency of this acceptor device in this phase-locked loop, this clock/data recovery circuit produces a receiver clock according to an external data signal of this external device (ED), and the method for adjustment of this frequency comprises:
(a) set this clock/data recovery circuit in a phase pattern, make this receiver clock follow the frequency of this external data signal;
(b) check that whether the difference of frequency of the frequency of this receiver clock and this transmitter clock is greater than a threshold value; And
(c), make the operating frequency of this external device (ED) equal the operating frequency of this acceptor device when this difference during greater than this threshold value.
2. the method for adjustment of frequency as claimed in claim 1, wherein the operating frequency of this acceptor device is lower than the operating frequency of this external device (ED).
3. the method for adjustment of frequency as claimed in claim 1, wherein this method also comprises:
When this external device (ED) was connected in this acceptor device, this clock/data recovery circuit at first in frequency mode operation down, made this receiver clock follow the frequency of this transmitter clock.
4. the method for adjustment of frequency as claimed in claim 1 wherein, also comprises in step (c):
When this difference during greater than this threshold value, this acceptor device sends a reset signal to restart this clock/data recovery circuit;
Wherein this threshold value is the difference of exercisable maximum frequency of this acceptor device and nominal operation frequency, perhaps is a rational higher limit.
5. the method for adjustment of frequency as claimed in claim 4 wherein also comprises:
Set this clock/data recovery circuit in this frequency mode, make this receiver clock follow the frequency of transmitter clock; And
Switch this clock/data recovery circuit in this phase pattern, make this receiver clock follow the frequency of this external data signal again.
6. the method for adjustment of frequency as claimed in claim 1 wherein, also comprises in step (c):
When this difference during, make this acceptor device keep following the frequency of this external data signal less than this threshold value.
7. the method for adjustment of frequency as claimed in claim 1, wherein this method also comprises:
Transmit this external data signal to this acceptor device from this external device (ED).
8. an acceptor device is applicable to an external data signal that receives an external device (ED), and this acceptor device comprises:
A transmitter clock is exported according to the operating frequency of this acceptor device in one phase-locked loop;
One clock/data recovery circuit, receive this external data signal, and export a receiver clock, when this clock/data recovery circuit is positioned at a phase pattern, this receiver clock is followed this external data signal, when this clock data/restoring circuit is positioned at frequency mode following time, this receiver clock is followed this transmitter clock; And
One frequency detector is dispersed signal according to the frequency of this receiver clock and the frequency of this transmitter clock to export a detection;
Wherein, when this clock/data recovery circuit is positioned at this phase pattern, and this frequency detector exports this detection when dispersing signal, and then this clock data recovery circuit is switched to this frequency mode, otherwise this clock/data recovery circuit maintains this phase pattern.
9. acceptor device as claimed in claim 8, wherein this acceptor device also comprises a controller, operates in this phase pattern or this frequency mode in order to switch this clock/data recovery circuit.
10. acceptor device as claimed in claim 9, wherein this frequency detector is exported this detection when dispersing signal, and this controller switches this clock/data recovery circuit to this frequency mode.
11. acceptor device as claimed in claim 8, when wherein the difference of the frequency of the frequency of this receiver clock and this transmitter clock exceeded a threshold value, this frequency detector was exported this detection and is dispersed signal.
12. acceptor device as claimed in claim 11, wherein this threshold value is the difference of exercisable maximum frequency of this acceptor device and nominal operation frequency, perhaps is a rational higher limit.
13. acceptor device as claimed in claim 8, when wherein the frequency of this receiver clock differed from the frequency of this transmitter clock, this frequency detector was exported this detection and is dispersed signal.
14. acceptor device as claimed in claim 13, when this external device (ED) was connected in this acceptor device, this clock/data recovery circuit at first in the operation down of this frequency mode, switched to this phase pattern again.
15. acceptor device as claimed in claim 8, wherein this acceptor device also comprises a reset controller, be used to this frequency detector and export this detection when dispersing signal, send a reset signal to this clock/data recovery circuit to restart this clock/data recovery circuit.
16. acceptor device as claimed in claim 8, wherein this external device (ED) is not when an overtime receives the response of this acceptor device in the time, and this external device (ED) switches the operating frequency of its operating frequency to this acceptor device.
17. the frequency adjusting method of an acceptor device, be applicable to an acceptor device that operates in one first operating frequency, this acceptor device is connected with an external device (ED), and adjust a receiver clock to receive an external data signal, this external device (ED) operates in one second operating frequency, and this frequency adjusting method comprises:
(a) make this receiver clock follow this second operating frequency;
(b) detect this receiver clock and be not in a normal operation range;
(c) make this external device (ED) operate in this first operating frequency;
Wherein this receiver clock is followed this first operating frequency when this acceptor device does not connect this external device (ED).
18. frequency adjusting method as claimed in claim 17, wherein this external device (ED) can operate in this first frequency and this second frequency, and this first frequency is lower than this second frequency.
19. frequency adjusting method as claimed in claim 17, wherein this first operating frequency of this normal operation range adds a threshold value.
20. frequency adjusting method as claimed in claim 17, when wherein this receiver clock was in this normal operation range, this receiver clock continued to follow this second operating frequency; When this receiver clock is not in this normal operation range, restart this acceptor device.
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| CNB2006101593211A CN100461065C (en) | 2006-09-27 | 2006-09-27 | Frequency regulation method and device for clock/data restoring circuit |
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| CNB2006101593211A CN100461065C (en) | 2006-09-27 | 2006-09-27 | Frequency regulation method and device for clock/data restoring circuit |
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| CN102103847A (en) * | 2009-12-22 | 2011-06-22 | 瑞萨电子株式会社 | Clock data recovery circuit, data transfer device for display device, and data transfer method for display device |
| WO2011088610A1 (en) * | 2010-01-19 | 2011-07-28 | Integrated Device Technologies, Inc | Method and circuit for displayport video clock recovery |
| CN103152103A (en) * | 2013-02-19 | 2013-06-12 | 青岛海信宽带多媒体技术有限公司 | Optical module and adaptive regulation method for rate mode of clock and data recovery (CDR) chip of optical module |
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| JP2002007322A (en) * | 2000-06-27 | 2002-01-11 | Hitachi Ltd | Phase regulation and control method, and information processor |
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| CN100374984C (en) * | 2005-03-01 | 2008-03-12 | 联想(北京)有限公司 | Method and device for switching video card working frequency |
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| CN102103847A (en) * | 2009-12-22 | 2011-06-22 | 瑞萨电子株式会社 | Clock data recovery circuit, data transfer device for display device, and data transfer method for display device |
| CN102103847B (en) * | 2009-12-22 | 2014-10-22 | 瑞萨电子株式会社 | Clock data recovery circuit, data transfer device for display device, and data transfer method for display device |
| WO2011088610A1 (en) * | 2010-01-19 | 2011-07-28 | Integrated Device Technologies, Inc | Method and circuit for displayport video clock recovery |
| US8217689B2 (en) | 2010-01-19 | 2012-07-10 | Integrated Device Technology, Inc. | Method and circuit for DisplayPort video clock recovery |
| CN103152103A (en) * | 2013-02-19 | 2013-06-12 | 青岛海信宽带多媒体技术有限公司 | Optical module and adaptive regulation method for rate mode of clock and data recovery (CDR) chip of optical module |
| CN113890553A (en) * | 2020-07-01 | 2022-01-04 | 联咏科技股份有限公司 | Receiver and transmitter for high-speed data and low-speed command signal transmission |
| CN113890553B (en) * | 2020-07-01 | 2023-02-17 | 联咏科技股份有限公司 | Receiver for high speed data and low speed command signal transmission |
| US11824966B2 (en) | 2020-07-01 | 2023-11-21 | Novatek Microelectronics Corp. | Receiver and transmitter for high speed data and low speed command signal transmissions |
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| CN100461065C (en) | 2009-02-11 |
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