CN1298203C - Circuit apparatus - Google Patents
Circuit apparatus Download PDFInfo
- Publication number
- CN1298203C CN1298203C CNB2003101197080A CN200310119708A CN1298203C CN 1298203 C CN1298203 C CN 1298203C CN B2003101197080 A CNB2003101197080 A CN B2003101197080A CN 200310119708 A CN200310119708 A CN 200310119708A CN 1298203 C CN1298203 C CN 1298203C
- Authority
- CN
- China
- Prior art keywords
- conductive pattern
- circuit
- circuit arrangement
- circuit element
- connector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Provided is a circuit device 10 which has an arrangement of complex electric circuits inside but facilitates electrical connection. The circuit device 10 is arranged such that a first circuit element 13 is mounted on an uppermost conductive pattern layer 12A of conductive pattern layers 12 that constitute a multilayer interconnection, and a second circuit element 14 and connectors 15 are mounted on a fourth conductive pattern layer 12D which is a lowermost conductive pattern layer exposed to the rear of the device. This arrangement can provide the circuit device 10 having a more number of circuit elements. Also, the mounting of the connectors 15 on the rear of the device can facilitate external electrical connection.
Description
Technical field
The present invention relates to circuit arrangement, the inside that relates to the circuit arrangement of sealed resin is equipped with and the outside connector that is electrically connected and the circuit arrangement of circuit element.
Background technology
Be contained in circuit arrangement on the electronic equipment now in order to be used for mobile phone, portable computer etc., require miniaturization and lightweight.For example if describe with the example of semiconductor device as circuit arrangement, as general semiconductor device, recently, developing and be called as CSP (chip size packages), the CSP that the CSP of the wafer level that equates with chip size or size are bigger than chip size (with reference to patent documentation 1).
Fig. 5 represents as supporting substrates, is the also bigger CSP100 of ratio chip size that has adopted glass epoxy substrate 101.At this, describe as the structure that transistor chip T is installed on glass epoxy substrate 101.
Form the first electrode 102A on the surface of this glass epoxy substrate 101, the second electrode 102B and die pad 103 form the first the inside electrode 105A and the second the inside electrode 105B inside.By through hole TH, the described first electrode 102A and the first the inside electrode 105A, the second electrode 102B are electrically connected with the second the inside electrode 105B.In addition, fixing described naked transistor chip T on die pad 103, the first electrode 102A is connected by fine wire 104 with transistorized emission electrode, and the second electrode 102B is connected by fine wire 104 with transistorized base electrode.And then, resin bed 106 is set on glass epoxy substrate 101, make its covering transistor chip T.
Though described CSP100 adopts glass epoxy substrate 101, and is different with the CSP of wafer level, connect simple in structure that the inside electrode 105A, the 105B of usefulness prolong to the outside from chip T, having can the cheap advantage of making.
With reference to Fig. 6,, constitute a module because above-mentioned elements such as CSP100 are installed on the installation base plate PS.On installation base plate PS, except that CPS, the circuit arrangement 110 of built-in semiconductor element, chip-resistance CR, and chip capacity CC also be installed on surface and the inside.Each circuit element is electrically connected by the conductive path that forms on the surface of installation base plate PS and the inside.With this structure constitute be installed in carry and OA equipment etc. in module.
[patent documentation 1]
The spy opens 2001-339151 communique (first page of Fig. 1)
But when formation had a kind of module of function, it is big that overall dimensions becomes with the structure shown in the conventional example.Exist the electronic equipment that this module is housed to be difficult to miniaturization, light-weighted problem.Particularly, the problem of existence is that its size reaches more than ten centimetre square when realizing described module with the structure shown in the conventional example.
And, owing to, have the problem of substrate connection difficulties such as motherboard at the two sides of installation base plate PS permanent circuit element.
Summary of the invention
The present invention proposes in view of above problem.Main purpose is: by circuit element and connector are installed on the conductive pattern that exposes in the inside of circuit arrangement, provide a kind of have module function and small-sized circuit arrangement.
Circuit arrangement of the present invention comprises: one deck conductive pattern at least; First circuit element is fixed on the described conductive pattern; Sealing resin, it is whole that it covers described first circuit element and described conductive pattern and supporting, connects connector on the described conductive pattern that exposes inside, on described conductive pattern peristome is set.
Have, circuit arrangement of the present invention comprises one deck conductive pattern at least again; First circuit element, it is fixed on the described conductive pattern; Sealing resin, it covers described first circuit element and described conductive pattern and supporting is whole, also has the second circuit element, and set on its described conductive pattern that exposes in the inside of described circuit arrangement is provided with peristome on described conductive pattern.
And then circuit arrangement of the present invention comprises: have encapsulation, this encapsulation comprises: two-layer at least conductive pattern; First circuit element, it is connected electrically on first electrode that forms as the conductive pattern of the described the superiors; Sealing resin, its described first circuit element and described conductive pattern integral sealing; Second electrode, its from form undermost conductive pattern, be positioned at the inside described sealing resin show out, described second electrode is made up of mounted connector electrode of using and the electrode that installation second circuit element is used, difference mounted connector and second circuit element, realize the circuit or the circuit system that need on described conductive pattern, peristome being set by striding across from the superiors to the orlop through hole that is provided with and distribution.
Description of drawings
Fig. 1 is the figure of explanation circuit arrangement of the present invention, (A) is plane graph, (B) is profile;
Fig. 2 is the figure of explanation circuit arrangement of the present invention, (A) is plane graph, (B) is profile;
Fig. 3 is the figure of explanation circuit arrangement of the present invention, (A) is profile, (B) is plane graph;
Fig. 4 is the figure of explanation circuit arrangement of the present invention, (A) is profile, (B) is plane graph;
Fig. 5 is the profile of explanation available circuit device;
Fig. 6 is the profile of explanation available circuit device.
Embodiment
The structure of circuit arrangement 10 of the present invention is described with reference to Fig. 1.Fig. 1 (A) is the top figure of circuit arrangement 10, and Fig. 1 (B) is its profile.Circuit arrangement 10 of the present invention comprises one deck conductive pattern 12A～D at least, be fixed on first circuit element 13, covering first circuit element 13 and conductive pattern 12A and the whole sealing resin 16 of supporting on the conductive pattern 12A, the conductive pattern 12D that inside exposes goes up the connection connector.Below in detail this kind structure will be described in detail.
With reference to tack, weldability, the plating of Fig. 1 (B) conductive pattern 12 consideration scolders, select its material.As material, to adopt with Cu be the conductive foil of main material, be the conductive foil of main material or by the conductive foil of alloy compositions such as Fe-Ni with Al.At this, form four layers the multi-layer wiring structure of forming by the first conductive pattern 12A, the second conductive pattern 12B, the 3rd conductive pattern 12C and the 4th conductive pattern 12D.Each conductive pattern 12 usefulness jockey 20 (contact hole or through hole) is electrically connected.Afterwards, each conductive pattern 12 is repeatedly long-pending together between the centre with resin bed 21.
The concrete structure of above-mentioned multilayer conductive figure 12 is described.The second conductive pattern 12B and the 3rd conductive pattern 12C are that the resin bed 21 of 100 μ m degree is repeatedly long-pending between the centre with thickness.And utilizing the electroplating film that on the through hole that passes resin bed 21, forms to form jockey 20, this jockey 20 is electrically connected the second conductive pattern 12B and the 3rd conductive pattern 12C.
The second conductive pattern 12B and the 3rd conductive pattern 12C utilize resin bed 21 to cover.On the resin bed 21 that covers the second conductive pattern 12B, establish through hole,, form the first conductive pattern 12A by forming copper coating.In addition, on the resin bed 21 that covers the 3rd conductive pattern 12C, establish through hole,, form the 4th conductive pattern 12D by forming copper coating.And the 4th position of conductive pattern 12D except exposing as terminal 18 covered by resin coating 17.
With reference to Fig. 1 (A), terminal 18 is made up of the 4th conductive pattern 12D that exposes from the resin coating 17 that covers circuit arrangement 10 the insides.At this,, be electrically connected with the first connector 15A of the connecting portion of outside at the terminal 18A of a side proper alignment of circuit arrangement 10.At the terminal 18B of one side proper alignment relative with terminal 18A, the terminal 18B that is connected with the outside connects.In addition, terminal 18C is along other side setting, has various as the using method of this terminal.For example also can be used for toward built-in semiconductor element (particularly memory, microcomputer etc.) write, sense data.Terminal 18E is located at the position beyond the periphery.As the method that this terminal uses, for example also can be used for the inner circuit that forms or the inspection of system.
As first circuit element 13, be passive components such as semiconductor element, chip capacity, chip-resistance such as transistor, diode, IC chip.In addition, though the thickness thickening also can be installed the semiconductor element of upside-down mountings such as CSP, BGA.And then also can adopt inductance, thermistor etc.Afterwards, first circuit element 13 is fixed on the first conductive pattern 12A, is covered by sealing resin 16.At this, the positive first circuit element 13A that installs is electrically connected with other the first conductive pattern 12A by fine wire 19.And as chip parts such as first circuit element 13B employing chip-resistance and chip capacities.Chip part as the first circuit element 13B adopts in order to suppress the thickness of sealing resin 16, adopts small parts, for example adopts the parts also thinner than the top of fine wire 19.And then owing to adopt than the also thin element of sealing resin 16 as first circuit element 13, the integral thickness that can form circuit arrangement 10 is very thin.
The first connector 15A is installed near the side of circuit arrangement 10 the insides, has and the outside effect that is electrically connected.On terminal 18A, carry out the electrical connection of the first connector 15A and terminal 18A by the lead fixed that derives from the first connector 15A.In addition, at the two ends of the first connector 15A, the lead by deriving fixing usefulness and with this lead fixed on terminal 18D, the first connector 15A is fixed on the inside of circuit element 10.
The second connector 15B be fixed on the first connector 15A opposed side edges portion near, be electrically connected with a plurality of terminal 18B by lead.Other structure is identical with the above-mentioned first connector 15A.
The above-mentioned first connector 15A and the second connector 15B also can be fixed on the side position in addition of circuit arrangement 10.And, two connectors 15 of quantity in addition can be installed in the inside of circuit arrangement 10.When two connector 15A, 15B are installed, also can be on the limit outside the relative limit mounted connector 15.
At this, the use-case that specifically makes of the first connector 15A and the second connector 15B is described.By the first connector 15A is electrically connected with other control part, the control part of the second connector 15B and CD-RW etc. is connected, and can use circuit arrangement 10 as the control module of CD-RW.Thereby, can carry out the indication that writes and read of CD-RW by second connector 15 according to the signal of telecommunication by other control part input.And then be sent to the outside from the first connector 15A by the signal that medium such as CD-RW are read.
With reference to Fig. 2, the mounting structure of relevant connector 15A is described.Fig. 2 (A) is the plane graph of circuit arrangement 10, and Fig. 2 (B) is a side view of seeing circuit arrangement 10 from the direction of arrow shown in Fig. 2 (A).
With reference to Fig. 2 (B), the first connector 15A draws lead 22A in the bottom at its two ends, utilizes lead 22A to be fixed on the terminal 18D, and the first connector 15A is fixed on the inside of circuit arrangement.At this, terminal 18D is made up of above-mentioned the 4th conductive pattern 12D, is the pseudo-conductive pattern that the signal of telecommunication does not pass through.In addition, the lead 22B that has below it at a side and each terminal 18A that exposes, the first connector 15A of circuit arrangement 10 of proper alignment is electrically connected by the scolder of welding etc.And each lead 22B is drawn go back to the inside of first connector, with terminal 18F conducting.Terminal 18F is as the outside input and output terminal performance function of circuit arrangement 10.The structure of the second connector 15B is identical with above-mentioned first connector.
The structure of the first conductive pattern 12A is described with reference to Fig. 3.Fig. 3 (A) is the profile of circuit arrangement 10, and Fig. 3 (B) is the A-A` view of Fig. 3 (A), and expression has the first conductive pattern 12A of circuit arrangement 10.
With reference to Fig. 3 (B), the first conductive pattern 12A forms weld pad and the wiring part that first circuit element 13 is installed.This figure central authorities with dashed lines area surrounded represents it is the first circuit element 13A of semiconductor element, and it is fixing that its first conductive pattern that forms on the island faces up.In addition, be provided with the connection weld pad that forms by the first conductive pattern 12A round circuit element 13A.By the wiring part that forms by the first conductive pattern 12A, reach first circuit element 13 between first circuit element 13 and be connected with jockey 20.
In the place that does not form trickle wiring part, with the structure of first conductive pattern 12A formation wide cut, the distribution that big as a comparison electric current flows uses.Particularly, the first conductive pattern 12A of wide cut formation can be used as the structure use that connects earthing potential or power supply.And the first conductive pattern 12A upper shed portion 23 that forms in wide cut is arranged to rectangular.Resin bed 21 exposes from peristome 23.Generally, the bonding force between the resin liken to into the bonding force of the metal of the material of conductive pattern 12 and resin big.Therefore, can make resin bed 21 bonding by the resin bed 21 that exposes from peristome 23 with other resin material that covers it (as sealing resin 16 or conduction tunicle 17).Therefore, can improve the reliability of circuit arrangement 10.In addition, by on the first conductive pattern 12A of such wide cut, peristome 23 being set, the side of conductive pattern 12A is exposed, make the contacts side surfaces of sealing resin 16 resins such as grade and conductive pattern 12, thereby, can improve the adhesive strength of conductive pattern 12A and sealing resin 16.
In addition, the peristome 23 of wide cut structure and formation there also is arranged on the second conductive pattern 12B and the 3rd conductive pattern 12C.Therefore, by on second conductive pattern and the 3rd conductive pattern, the adhesive strength that peristome 23 can improve resin bed 21 and conductive pattern 12 being set.
Describe relate to other advantage that peristome 23 is set on each layer conductive pattern 12.By on each layer conductive pattern 12, peristome being set, can adjust the survival rate of conductive pattern 12 by proper proportion.Particularly, by the first conductive pattern 12A and the 4th conductive pattern 12D being adjusted into the survival rate of same degree, can make the consistency of thickness of the resin coating 17 that covers them.And, can make the consistency of thickness of the resin bed 21 that covers them by the survival rate of the second conductive pattern 12B and the 3rd conductive pattern 12C being adjusted to same degree.
The second conductive pattern 12B and the 3rd conductive pattern 12C are electrically connected by jockey 20, form main wiring portion.
Structure with reference to Fig. 4 explanation and the 4th conductive pattern 12D.Fig. 4 (A) is the profile of circuit arrangement 10, and Fig. 4 (B) is the A-A` view of Fig. 4 (A).
With reference to Fig. 4 (B), the terminal 18 and the wiring part of second circuit element 14 and connector 15 installed in the 4th conductive pattern 12D, formation.Each terminal 18 is connected by the circuit that the wiring part be made up of the 4th conductive pattern 12D or jockey and inside at circuit arrangement 10 constitute.Terminal 18A and terminal 18B inside expose from resin coating 17 along a side proper alignment of circuit arrangement 10.In addition, be under a plurality of situations at terminal 18A or terminal 18B, as shown in the drawing, also can proper alignment become more than two row.Terminal 18C proper alignment, is used for data are write inner semiconductor element at this at a side of circuit arrangement 10.And the position of terminal 18E beyond the side portion of circuit arrangement 10 the insides forms.This terminal 18E can be used for as the action of the circuit of confirming to form in inside and characteristic etc.In addition, above-mentioned terminal 18 both can be located at the position beyond the side portion, also can not be that proper alignment ground is provided with.
Narrate feature of the present invention below.
Because general semiconductor packages is installed on the installation base plate of tellite etc., forms on the profile of encapsulation any element is not installed.As only forming the outside electrode that connects usefulness,, circuit element and connector are not installed in the part of the electrode that forms the inside as the BGA of an example in the encapsulation the inside.This is owing to be installed on the substrate by mounting materials such as scolding tin.
This device is not to be fixed on the installation base plate, is the semiconductor packages that himself is used as installation base plate.This encapsulation is not owing to know which layer to adopt conductive pattern at, its thickness difference, but integral body is slim plate body greatly about below one centimetre.If scolders such as scolding tin are set on the external connecting electrode that is positioned at the inside same as before, this also can form slim BGA, and as Fig. 1 (B), both represented the inside, use as installed surface again,, second circuit element 14 is connected with connector 15 and forms module at this.
In a word, the present invention utilizes following key element can realize circuitry needed or system.
(1) the conductive pattern 12A of modular first circuit element 13, the superiors with the electrode that forms by it, bonding land, be connected weld pad etc.;
(2) external connecting electrode, the distribution that forms by undermost the 4th conductive pattern 12D, second circuit element 14 mounted thereto;
(3) be located at the distribution of one deck at least between orlop and the superiors' conductive pattern;
(4) through hole of 12 formation of each conductive pattern;
(5) be located at connector 15 on the undermost external connecting electrode.
Thin thickness, and do not have the part of lead frame, the area on its plane is also reduced, can realize subminiature encapsulation, can form and carry instrument, the miniaturization of OA machine, lightweight.In addition, connector becomes these Unit Installation devices.It generally is 0.5 millimeter slim encapsulation as 5 centimetres of 5 cm x, 4 centimetres of 10 cm x, thickness, even consider that usually its bending also is a problem, and is not the installations such as scolding tin that form inside, owing to, can install by its crooked former state with installations such as connector and thin plate holding devices.Thereby, also can prevent the crackle of scolding tin etc.
Then, the first conductive pattern 12A that forms island peristome 23 is described.Hereinafter referred to as network structure.The original aim of this network structure is the pesudo-structure that is provided with shown in Fig. 3 (A), and it is used for crossing over the first conductive pattern 12A～the 4th conductive pattern 12D comprehensively and they are made the sealing resin 16 of integral body, and formation essence is even.This pesudo-structure electrode self also can be an island, but because the voltage that adds separately is unearthed, produces electric capacity.For with its ground connection and fixing separately, contact holes must be arranged.If make such network structure, and be located on each layer or the overlapping the upper and lower together, just can make them become the identical contact hole of current potential at least at a place.And, by the resin-bonded of peristome 23 the upper and lower, as the adaptation raising of encapsulation.In addition, shown in Fig. 3 (B), figure also becomes the function that the large-current electric utmost point is flow through in wonderful works.And each layer network structure is fixing for example on earthing potential, does not also just produce parasitic capacitance.And then, also shield effectiveness can be arranged by the size of controlling this peristome 23.
The present invention can receive following effect.
By the inside at circuit arrangement 10 connector 15 that forms with the outside terminal that is connected is installed, the planar dimension of circuit arrangement 10 integral body can not become greatly, can be connected with external electric at an easy rate by connector 15.Described circuit arrangement 10 is equipped with first circuit element 13 that is positioned on the conductive pattern 12.
By second circuit element 14 is installed in the inside of circuit arrangement 10, can provides small-sized and have the circuit arrangement of complicated circuit structure.Described circuit arrangement 10 be equipped with built-in semiconductor element etc. first circuit element 13, form the conductive pattern 12 of multilayer.Particularly, the planar dimension of circuit arrangement 10 of the present invention can form about 3cm * 3cm.
Also have, owing to passing through that conductive pattern 12 is formed multilayers, at the more complicated circuit of the inner formation of device, so can constitute the circuit arrangement 10 that conduct has the module of a system.As constituting circuit arrangement 10 with hardware functions such as control CD-WR.
In addition,, do not need the such supporting substrates of installation base plate of conventional example, so that circuit arrangement 10 can be made is slim because circuit arrangement 10 can be whole by sealing resin supporting.
Claims (19)
1, a kind of circuit arrangement is characterized in that, comprising: one deck conductive pattern at least; First circuit element, it is fixed on the described conductive pattern; Sealing resin, it is whole that it covers described first circuit element and described conductive pattern and supporting,
Connect connector on the described conductive pattern that exposes inside,
On described conductive pattern, peristome is set.
2, circuit arrangement as claimed in claim 1 is characterized in that, described connector is located at the periphery of described circuit arrangement.
3, circuit arrangement as claimed in claim 1 is characterized in that, described connector is along the side setting of relative direction.
4, circuit arrangement as claimed in claim 1 is characterized in that, in the inside of described conductive pattern the second circuit element is installed.
5, circuit arrangement as claimed in claim 1 is characterized in that, described conductive pattern forms multilayer, and described first circuit element is installed on the described conductive pattern of the superiors, connects described connector on undermost described conductive pattern.
6, circuit arrangement as claimed in claim 1 is characterized in that, described first circuit element is transistor, diode, IC, chip capacity, chip-resistance, sealing resin shell, inductance or thermistor.
7, circuit arrangement as claimed in claim 4 is characterized in that, described second circuit element is transistor, diode, IC, electric capacity chip, chip-resistance, sealing resin shell, inductance or thermistor.
8, circuit arrangement as claimed in claim 1 is characterized in that, by constituting the weld pad and the wiring part of fixing described first circuit element by described conductive pattern, thus forming circuit or system.
9, a kind of circuit arrangement is characterized in that, comprises one deck conductive pattern at least; First circuit element, it is fixed on the described conductive pattern; Sealing resin, it is whole that it covers described first circuit element and described conductive pattern and supporting,
Also have the second circuit element, it is fixed on the described conductive pattern that exposes in described circuit arrangement the inside,
On described conductive pattern, peristome is set.
10, circuit arrangement as claimed in claim 9 is characterized in that, described first circuit element is semiconductor element and the chip part that is electrically connected with described conductive pattern with fine wire, and the thickness of described chip part is also thinner than described sealing resin.
11, circuit arrangement as claimed in claim 9 is characterized in that, described first circuit element and described second circuit element are transistor, diode, IC, chip capacity, chip-resistance, sealing resin shell, inductance or thermistor.
12, circuit arrangement as claimed in claim 9 is characterized in that, at the periphery of described circuit arrangement the connector that is connected with described conductive pattern is installed, and disposes the second circuit element in the zone that is clipped in by described connector therebetween.
13, circuit arrangement as claimed in claim 9 is characterized in that, described conductive pattern forms multilayer, and described first circuit element is installed on the described conductive pattern of the superiors, and described second circuit element is installed on undermost described conductive pattern.
14, circuit arrangement as claimed in claim 9 is characterized in that, by constituting the weld pad and the wiring part of fixing described first circuit element and described second circuit element by described conductive pattern, thus forming circuit or system.
15, a kind of circuit arrangement is characterized in that, has encapsulation, and this encapsulation comprises: two-layer at least conductive pattern; First circuit element, it is connected electrically on first electrode that forms as the conductive pattern of the described the superiors; Sealing resin, its described first circuit element and described conductive pattern integral sealing; Second electrode, it forms undermost conductive pattern, shows out from the described sealing resin that is positioned at the inside,
The electrode that described second electrode is used by mounted connector and the electrode that the second circuit element uses is installed is formed, mounted connector and second circuit element respectively, by stride across through hole that the superiors are provided with to orlop and distribution realize need circuit or circuit system,
On described conductive pattern, peristome is set.
16, circuit arrangement as claimed in claim 15 is characterized in that, described second circuit element is packed semiconductor element, chip capacity, chip-resistance or electrochemical capacitor.
17, as claim 1,9 or 15 described circuit arrangements, it is characterized in that, by the described peristome that on described conductive pattern, is provided with, make the resin bed of described conductive pattern one side of exposing from this peristome and cover other resin materials of described conductive pattern bonding.
18, circuit arrangement as claimed in claim 17 is characterized in that, described peristome forms island, the conductive pattern that is formed with described peristome on the upper strata or lower floor overlap and form, both fix with identical current potential on electric.
19, circuit arrangement as claimed in claim 17, it is characterized in that described peristome forms island, the conductive pattern that is formed with described peristome strides across multilayer, form dummy section, form with the resin bed of fixing this conductive pattern and stride across whole uniform thickness in fact.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP350774/02 | 2002-12-03 | ||
| JP350774/2002 | 2002-12-03 | ||
| JP2002350774A JP2004186362A (en) | 2002-12-03 | 2002-12-03 | Circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1505459A CN1505459A (en) | 2004-06-16 |
| CN1298203C true CN1298203C (en) | 2007-01-31 |
Family
ID=32752873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101197080A Expired - Fee Related CN1298203C (en) | 2002-12-03 | 2003-12-03 | Circuit apparatus |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP2004186362A (en) |
| KR (1) | KR100715409B1 (en) |
| CN (1) | CN1298203C (en) |
| TW (1) | TW595274B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006173489A (en) * | 2004-12-17 | 2006-06-29 | Tokai Rika Co Ltd | Electronic component mounting structure |
| JP2008053319A (en) * | 2006-08-22 | 2008-03-06 | Nec Electronics Corp | Semiconductor device |
| JP4958526B2 (en) * | 2006-11-30 | 2012-06-20 | 三洋電機株式会社 | Circuit device and circuit module |
| JP4948160B2 (en) * | 2006-12-29 | 2012-06-06 | 三洋電機株式会社 | Circuit module |
| JP4975655B2 (en) * | 2007-02-01 | 2012-07-11 | 日本特殊陶業株式会社 | Wiring board, semiconductor package |
| JP5360221B2 (en) * | 2009-09-16 | 2013-12-04 | 株式会社村田製作所 | Electronic component built-in module |
| TWI795644B (en) * | 2020-06-02 | 2023-03-11 | 大陸商上海兆芯集成電路有限公司 | Electronic assembly |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0870024A (en) * | 1994-08-29 | 1996-03-12 | Fujitsu Ltd | Semiconductor device and its manufacture |
| JP2001077232A (en) * | 1999-09-06 | 2001-03-23 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| CN1315823A (en) * | 2000-03-08 | 2001-10-03 | 三洋电机株式会社 | Method for manufacturing circuit device and circuit device |
| CN1348205A (en) * | 2000-10-02 | 2002-05-08 | 三洋电机株式会社 | Method for producing electric circuit device |
| US6445592B1 (en) * | 1993-08-30 | 2002-09-03 | Temic Telefunken Microelectronic Gmbh | Electronic assembly |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970001891B1 (en) * | 1991-02-08 | 1997-02-18 | 가부시키가이샤 도시바 | Semiconductor device and method for manufacturing the same |
| CN1265451C (en) * | 2000-09-06 | 2006-07-19 | 三洋电机株式会社 | Semiconductor device and manufactoring method thereof |
| JP3945968B2 (en) * | 2000-09-06 | 2007-07-18 | 三洋電機株式会社 | Semiconductor device and manufacturing method thereof |
-
2002
- 2002-12-03 JP JP2002350774A patent/JP2004186362A/en active Pending
-
2003
- 2003-08-15 TW TW092122459A patent/TW595274B/en not_active IP Right Cessation
- 2003-11-26 KR KR1020030084298A patent/KR100715409B1/en not_active IP Right Cessation
- 2003-12-03 CN CNB2003101197080A patent/CN1298203C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6445592B1 (en) * | 1993-08-30 | 2002-09-03 | Temic Telefunken Microelectronic Gmbh | Electronic assembly |
| JPH0870024A (en) * | 1994-08-29 | 1996-03-12 | Fujitsu Ltd | Semiconductor device and its manufacture |
| JP2001077232A (en) * | 1999-09-06 | 2001-03-23 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| CN1315823A (en) * | 2000-03-08 | 2001-10-03 | 三洋电机株式会社 | Method for manufacturing circuit device and circuit device |
| CN1348205A (en) * | 2000-10-02 | 2002-05-08 | 三洋电机株式会社 | Method for producing electric circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2004186362A (en) | 2004-07-02 |
| KR20040048818A (en) | 2004-06-10 |
| TW595274B (en) | 2004-06-21 |
| KR100715409B1 (en) | 2007-05-07 |
| CN1505459A (en) | 2004-06-16 |
| TW200410604A (en) | 2004-06-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10468380B2 (en) | Stackable microelectronic package structures | |
| US5475264A (en) | Arrangement having multilevel wiring structure used for electronic component module | |
| RU2504863C2 (en) | Housings with multilayer arrangement of chips in housing-on-housing type of device, methods for assembly thereof and systems comprising same | |
| CN103370785B (en) | There is the enhancing stacking micromodule of central contact | |
| JP5757448B2 (en) | Wearable integrated circuit package in package system | |
| CN104205268B (en) | Three-dimensional passive more device architectures | |
| CN1685509A (en) | Electronic package with back side cavity mounted capacitors and method of fabrication therefor | |
| CN103384913A (en) | Enhanced stacked microelectronic assemblies with central contacts and improved ground or power distribution | |
| CN211879388U (en) | Photosensitive module | |
| CN102498562A (en) | Flexible circuit module | |
| KR20190135322A (en) | Film package and Package module including the same | |
| CN107689366B (en) | Semiconductor chip and semiconductor package having the same | |
| CN103620775A (en) | Stacked chip-on-board module with edge connector | |
| CN101455129A (en) | Shielded via | |
| CN1298203C (en) | Circuit apparatus | |
| JP2005521228A (en) | Electronic assembly having laterally connected capacitors and method of manufacturing the same | |
| CN111354716B (en) | Decimated NAND logic in a stack | |
| US6803666B2 (en) | Semiconductor chip mounting substrate and semiconductor device using the same | |
| CN110277377B (en) | Film substrate structure, chip-on-film package and package module | |
| KR20120063202A (en) | Semiconductor package and display panel assembly having the same | |
| KR100513422B1 (en) | Mounting structure in integrated circuit module | |
| JP2630294B2 (en) | Hybrid integrated circuit device and method of manufacturing the same | |
| CN117393534A (en) | Chip packaging structure and electronic equipment | |
| CN114695326A (en) | Packaging structure and electronic equipment | |
| CN116963412A (en) | Packaging structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070131 Termination date: 20121203 |