CN1297173A - Synchronizer for converting asynchronous pulse signals to synchronous ones - Google Patents
Synchronizer for converting asynchronous pulse signals to synchronous ones Download PDFInfo
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- CN1297173A CN1297173A CN 99124816 CN99124816A CN1297173A CN 1297173 A CN1297173 A CN 1297173A CN 99124816 CN99124816 CN 99124816 CN 99124816 A CN99124816 A CN 99124816A CN 1297173 A CN1297173 A CN 1297173A
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Abstract
A synchronizer for converting the non-synchronous pulse signals to synchronous ones referring to one clock signal is composed of 4 triggers, 2 AND gates, 1 NAND gate and 1 inverter. The first trigger can capture the leading edge of input signal. The triggers No.2 and No.3 can generate pulse signal synchronous with the reference clock signals. The fourth trigger is used to reset other three.
Description
The present invention relates to a kind of signal conversion element, particularly relate to a kind of synchronous element (synchronizationelement) that is used for asynchronous pulse is converted to the synchronization pulse of reference one clock signal.
Along with the progress of semiconductor technology, make that the complicacy of digital circuit is more and more higher, for example present PC of generally using, in order to improve execution speed and usefulness, each subsystem in system can use different clock frequency work.Foreign frequency as CPU (CPU (central processing unit)) work is 66MHz or 100MHz, and the frequency of operation of pci interface is 33MHz or 66MHz, or is frequency work with 10MHz or 100MHz via the network interface that PCI (PCI (peripheral component interconnect)) interface connects.For a long time in the system of clock frequency, formation (queue) commonly used transmits data, to raise the efficiency at this kind.In the work of formation, promptly need asynchronous control signal is converted to the control signal synchronous with the reference clock signal of its work, in addition, also need the function of this kind conversion of signals between the subsystem of different operating frequency, could normally work.
Please refer to Fig. 1, a kind of block scheme that uses the system of two kinds of frequency work simultaneously shown in it.
As shown in Figure 1, host apparatus 120 transmits data with peripherals 110 by array device 130 and 140.Wherein use clock signal C K1 during host apparatus 120 work, and use clock signal C K2 during peripherals 110 work.The formation 135 that peripherals 110 is put into array device 130 through signal DIN and control signal PUSH with data, 120 of host apparatus are read the data of formation 135 via signal DOUT and control signal POP.On the other hand, host apparatus 120 reaches the formation 145 that control signal PUSH ' (pushing away) puts into array device 140 with data through signal DIN ', and 110 of peripherals reach control signal POP ' via signal DOUT ' data of formation 145 are read.
Because host apparatus 120 uses different reference clock (CK1 and CK2) respectively when working with peripherals 110, therefore in array device 130 and 140, the asynchronous pulse that host apparatus 120 or peripherals 110 must be sent converts the synchronization pulse with reference to the clock of its internal work to, could correctly work.
Pulse signal with reference to different clocks to be converted to pulse signal with reference to identical clock, traditional practice can utilize the state machine (state machine) of Gray code (Gray code) to finish, and it utilizes the principle once only allow a position to change to come control signal to change to a direction.But this kind finished the conventional practice of signal Synchronization with the state machine of Gray code, can only solve the problem that will convert to reference to the pulse signal of the clock of lower frequency with reference to the pulse signal of the clock of upper frequency, the pulse width of just original input signal must be greater than the cycle of new reference clock.If will convert pulse signal to, then can't finish with conventional practice with reference to the pulse signal of the clock of upper frequency with reference to the clock of lower frequency.
The object of the present invention is to provide a kind of synchronous element that asynchronous pulse is converted to synchronization pulse, it can convert the pulse signal with reference to the time clock of upper frequency to the pulse signal with reference to the time clock of lower frequency to the pulse signal width of input without limits.
Therefore the invention provides a kind of synchronous element that is used for asynchronous pulse is converted to synchronization pulse, it receives an input signal and a clock signal and exports an output signal, and receives a reset signal, in order to this output signal is resetted.This synchronous element comprises one first trigger, one second trigger, one the 3rd trigger, one the 4th trigger, a phase inverter, a NAND door (Sheffer stroke gate), one the one AND door (with door), reaches one the 2nd AND door.Wherein first trigger, second trigger, and the 3rd trigger all have a data input pin, a clock input end, a RESET input, an and state output end, and the 4th trigger has a data input pin, a clock input end, a RESET input, an and complementary state output terminal.
Wherein, the input end of clock of first trigger is coupled to this input signal, and the data input pin of first trigger is coupled to a noble potential.The data input pin of second trigger is coupled to the state output end of first trigger, and its input end of clock is coupled to clock signal.Second trigger, the 3rd trigger, and the RESET input of the 4th trigger all be coupled to reset signal.
Two input ends of the one AND door are coupled to the state output end of second trigger and the complementary state output terminal of the 4th trigger respectively, and the output terminal of an AND door is coupled to the data input pin of the 3rd trigger.
The input end of clock of the 3rd trigger is coupled to this clock signal, and its state output end is exported this output signal.
The data input pin of the 4th trigger is coupled to the state output end of the 3rd trigger, and this clock signal is coupled to the input end of clock of the 4th trigger through this phase inverter.
Two input ends of NAND door are coupled to the state output end of the 3rd trigger and the complementary state output terminal of the 4th trigger respectively, two input ends of the 2nd AND door are coupled to the output terminal of this reset signal and NAND door respectively, and the output terminal of the 2nd AND door then is coupled to the RESET input of first trigger.
According to a preferred embodiment of the present invention, wherein this input signal is a pulse signal.In addition, first trigger, second trigger, the 3rd trigger, and the 4th trigger can be respectively a D flip-flop.
According to another practice of the present invention, a kind of synchronous element that is used for asynchronous pulse is converted to synchronization pulse is provided, it receives an input signal and a clock signal and exports an output signal, wherein this input signal is a pulse signal, and this synchronous element comprises one first trigger, one second trigger, one the 3rd trigger, reaches one the 4th trigger.
Wherein, first trigger receives this input signal, the signal of its state output end is changed into another state (noble potential) in the forward position of this input signal, for example, the forward position of this input signal is input signal is become noble potential by electronegative potential a rising edge, and the virgin state of the signal of the state output end of first trigger is an electronegative potential, and another state after the change then is a noble potential.
Second trigger receives the signal of the state output end of this first trigger, after the signal of the state output end of this first trigger becomes another state, pulse front edge subsequently in this clock signal, for example the pulse front edge of this clock signal is clock signal is become noble potential by electronegative potential a rising edge, with the signal change of the state output end of this second trigger is another state, for example, the virgin state of the signal of the state output end of second trigger is an electronegative potential, and another state after the change then is a noble potential.
The 3rd trigger receives the signal of the state output end of this second trigger, the signal of the state output end of the 3rd trigger is this output signal, after the signal of the state output end of this second trigger becomes another state, pulse front edge subsequently in this clock signal, with the signal change of the state output end of the 3rd trigger is another state, for example, the virgin state of the signal of the state output end of the 3rd trigger is an electronegative potential, and another state after the change then is a noble potential.
The 4th trigger receives the signal of the state output end of the 3rd trigger, behind the signal change state of the state output end of the 3rd trigger, pulse back edge subsequently in this clock signal, for example the pulse back edge of this clock signal is clock signal is become electronegative potential by noble potential a negative edge, with the signal change of the state output end of the 4th trigger is another state, for example, the virgin state of the signal of the state output end of the 4th trigger is a noble potential, and another state after the change then is an electronegative potential.
The signal of the state output end of the 4th trigger is delivered to this first trigger and the 3rd trigger, and after the signal of the state output end of the 3rd trigger became another state, the signal of the state output end of this first trigger reverted to original state.And at the pulse front edge subsequently of this clock signal, the signal of the state output end of the 3rd trigger reverts to original state.
After the signal of the state output end of this first trigger reverts to original state,, the signal of the state output end of this second trigger is reverted to original state at the pulse front edge subsequently of this clock signal.After the signal of the state output end of the 3rd trigger reverts to original state,, the signal of the state output end of the 4th trigger is reverted to original state at the pulse back edge subsequently of this clock signal.
According to above proposed by the invention in order to asynchronous pulse is converted to the synchronous element of synchronization pulse, can limit the width of the pulse signal of input, as long as input signal is a pulse signal, therefore can be converted into synchronous pulse signal, can reach pulse signal with the clock of reference upper frequency and convert function to reference to the pulse signal of the clock of lower frequency.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, hereinafter, be described in detail below in conjunction with the accompanying drawings to the preferred embodiment of the present invention.
Fig. 1 is the block scheme that uses the system of two kinds of frequency work simultaneously.
Fig. 2 is the circuit diagram of synchronous element of the present invention.
Fig. 3 is the sequential chart of synchronous element work of the present invention.
Label declaration:
110 peripherals, 120 host apparatus
135 formations of 130 array devices
145 formations of 140 array devices
200 synchronous elements
, and 214 triggers 211,212,213
221 and 222 and (AND) door 223 with non-(NAND) door
224 phase inverters
Please refer to Fig. 2, shown in it according to a kind of circuit diagram of one embodiment of the present invention in order to the synchronous element (synchronization element) that asynchronous pulse is converted to synchronization pulse.
As shown in Figure 2, synchronous element 200 is used for converting input signal P1 to the output signal P2 synchronous with clock signal clk, and wherein input signal P1 is pulse (pulse) signal, and its width is not restricted to longer or short than the cycle of clock signal clk.Reset signal RST (reset) the output signal P2 that then can be used to reset for example, when reset signal RST is electronegative potential, can be reset to electronegative potential with output signal P2.
As shown in Figure 2, synchronous element 200 by four triggers 211,212,213, with 214, AND door 221 and 222, NAND door 223, reach phase inverter 224 and constituted, and in this embodiment, four triggers 211,212,213, with 214 all use D flip-flop, certainly, those skilled in the art also can use different triggers to reach identical functions.Circuit diagram according to present embodiment, suppose that all triggers live the signal latch (latch) of data input pin D when the signal rising edge of input end of clock CK, and when its RESET input R is electronegative potential, its state output end Q becomes electronegative potential, and its complementary state output terminal QN becomes noble potential, in addition, because do not use trigger 211,212, and the signal of 213 complementary state output terminal QN, so omitted not shown.
Wherein, the data input pin D of trigger 211 is coupled to power vd D, and its input end of clock CK then is coupled to input signal P1, therefore when input signal P1 becomes the rising edge of noble potential by electronegative potential, be the forward position of input signal P1, will make the state output end Q of trigger 211 become noble potential.
The data input pin D of trigger 212 is coupled to the state output end Q of trigger 211, after the state output end Q of trigger 211 becomes noble potential, rising edge subsequently at clock signal clk, be the forward position of the next cycle of clock signal clk, the state output end Q of trigger 212 also becomes noble potential.The complementary state output terminal QN of the state output end Q of trigger 212 and trigger 214 is coupled to two input ends of AND door 221 respectively, and the output terminal of AND door 221 then is coupled to the data input pin D of trigger 213.The virgin state of supposing the complementary state output terminal QN of trigger 214 is a noble potential, therefore after the state output end Q of trigger 212 becomes noble potential, the output terminal of AND door 221 also is a noble potential, rising edge subsequently at clock signal clk, the state output end Q of trigger 213 will become noble potential, and just output signal P2 becomes noble potential.
The complementary state output terminal QN of the state output end Q of trigger 213 and trigger 214 is coupled to two input ends of NAND door 223 respectively, therefore when the complementary state output terminal QN of the state output end Q of trigger 213 and trigger 214 is noble potential simultaneously, the current potential of the output terminal of NAND door 223 will become electronegative potential.And two input ends of AND door 222 are coupled to the output terminal of reset signal RST and NAND door 223 respectively, and the output terminal of AND door 222 then is coupled to the RESET input R of trigger 211.Therefore after the current potential of the output terminal of NAND door 223 became electronegative potential, the current potential of the output terminal of AND door 222 also and then became electronegative potential, so trigger 211 will be resetted, and the state output end Q of trigger 211 promptly reverts to the electronegative potential of virgin state.
The data input pin D of trigger 214 is coupled to the state output end Q of trigger 213, and clock signal clk then is coupled to the input end of clock CK of trigger 214 through phase inverter 224.Therefore after the state output end Q of trigger 213 becomes noble potential, negative edge subsequently (being the pulse back edge of clock signal clk) at clock signal clk, just when the current potential of the input end of clock CK of trigger 214 becomes the rising edge of noble potential by electronegative potential, the complementary state output terminal QN of trigger 214 will become electronegative potential, also make the output terminal of AND door 221 become electronegative potential jointly.
After the state output end Q of trigger 211 becomes electronegative potential, when subsequently the rising edge of clock signal clk, the state output end Q of trigger 212 reverts to the electronegative potential of virgin state, simultaneously, because the output terminal of AND door 221 is an electronegative potential, therefore the state output end Q of trigger 213 also reverts to the electronegative potential of virgin state, and promptly output signal P2 turns back to the electronegative potential of virgin state.
At last, after output signal P2 turned back to electronegative potential, again through half period, at the negative edge of clock signal clk, the current potential of the complementary state output terminal QN of trigger 214 reverted to the noble potential of virgin state.
In sum, trigger 211 mainly is to be used for the pulse front edge of capturing input signal P1, promptly the rising edge at input signal P1 latchs it, trigger 212 and 213 can produce and the synchronous pulse signal P2 of reference clock signal according to the state that trigger 211 latchs, trigger 214 is used for making other trigger to revert to original state, making output signal P2 only keep one-period promptly turns off, revert to original state, AND door 221 with 222 and 223 at NAND door be used for producing suitable control signal and control corresponding signal.
In addition, more than with correct logic the work of circuit is described, use if desired when the system of negative logic, as long as add suitable logic element,, promptly can be applicable to the system of negative logic as phase inverter.
In order to be illustrated more clearly in its course of work, please refer to Fig. 3, the sequential chart of the each point signal of the course of work of synchronous element shown in it 200.
As shown in Figure 3, read easily in order to make sequential chart, signal with the symbology each point, wherein signal EVT is the signal of the state output end Q of trigger 211, signal MTA is the signal of the state output end Q of trigger 212, signal P2I is the signal of the output terminal of AND door 221, and signal P2D is the signal of the complementary state output terminal QN of trigger 214, and signal R2Z is the signal of the output terminal of AND door 222.In addition, with the cycle reference of timing variations as an illustration of clock signal clk.
As shown in Figure 3, input signal P1 the pulse shorter than the one-period of clock signal clk of a width occur after period T 0.Become the rising edge of noble potential at input signal P1 by electronegative potential, i.e. its forward position, trigger 211 captures this to be changed, and makes the signal EVT of its state output end Q become noble potential.
Then, when the rising edge of subsequently period T 1, the signal MTA of the state output end Q of trigger 212 becomes noble potential, simultaneously, because the signal P2D of the complementary state output terminal QN of trigger 214 is a noble potential, so the signal P2I of AND door 221 output terminals also and then becomes noble potential.
Then, when the rising edge of period T 2, become noble potential by the output signal P2 of the state output end Q of trigger 213 output.Because the complementary state output terminal QN (being signal P2D) of state output end Q of trigger 213 (being output signal P2) and trigger 214 is a noble potential, therefore the signal R2Z that exports through the combinational logic of NAND door 223 and AND door 222 becomes electronegative potential, and trigger 211 is resetted, make the signal EVT of its state output end Q turn back to electronegative potential.
Because the output signal P2 of trigger 213 outputs is a noble potential, and clock signal clk delivers to the effect of the input end of clock of trigger 214 through phase inverter 224, becomes electronegative potential when making negative edge in the middle of period T 2 of the signal P2D of complementary state output terminal QN of trigger 214.Simultaneously, also make the signal P2I of AND door 221 outputs become electronegative potential.
At last, when the rising edge of period T 3, the output signal P2 of the signal MTA of trigger 212 outputs and trigger 213 outputs is returned as electronegative potential.Then, again through half period, the negative edge in the middle of period T 3, the current potential of the complementary state output terminal QN of trigger 214 reverts to noble potential.So far, the conversion of a signal is promptly accused and is finished.
Below, the conversion of second signal in the sequential chart is discussed.
As shown in Figure 3, input signal P1 became noble potential before the rising edge of period T 4, and recovered electronegative potential after keeping a blink.When input signal P1 became the rising edge of noble potential by electronegative potential, trigger 211 was mended and is grasped this variation, makes the signal EVT of its state output end Q become noble potential.
Then, when the rising edge of period T 4, the signal MTA of the state output end Q of trigger 212 becomes noble potential, simultaneously, because the signal P2D of the complementary state output terminal QN of trigger 214 is a noble potential, make the signal P2I of AND door 221 output terminals also and then become noble potential.
Then, when the rising edge of period T 5, become noble potential by the output signal P2 of the state output end Q of trigger 213 output.Because the complementary state output terminal QN (signal P2D) of the state output end Q (output signal P2) of trigger 213 and trigger 214 is a noble potential, therefore the signal R2Z of output becomes electronegative potential after NAND door 223 and AND door 222, and trigger 211 is resetted, make the signal EVT answer of its state output end Q be electronegative potential.
Because the output signal P2 of trigger 213 output is a noble potential, and through the effect of phase inverter 224, become electronegative potential when making negative edge in the middle of period T 5 of the signal P2D of complementary state output terminal QN of trigger 214.Simultaneously, also make the signal P2I of AND door 221 outputs become electronegative potential.
At last, when the rising edge of period T 6, the output signal P2 of the signal MTA of trigger 212 outputs and trigger 213 outputs is returned as electronegative potential.Then, again through half period, the negative edge in the middle of period T 6, the current potential of the complementary state output terminal QN of trigger 214 reverts to noble potential.So far, the conversion of a pulse signal is promptly accused and is finished.
According to above-mentioned process, no matter the width in the cycle of the pulse signal P1 of input or not synchronous with reference clock signal CLK, synchronous element 200 all can be caught input signal P1, produce then with clock signal clk synchronously and periodic width be the output signal P2 of a clock period.
From above discussion, as seen the synchronous element that is used for asynchronous pulse is converted to synchronization pulse of the present invention has following advantage, needn't limit the width of the pulse signal of input, as long as input is pulse signal, so can solve the problem that will convert to reference to the pulse signal of the clock of upper frequency with reference to the pulse signal of the clock of lower frequency.
Though above the preferred embodiments of the present invention are described; so it is not to be used for limiting the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; can make some modifications and modification, so protection scope of the present invention should be defined by the accompanying Claim book.
Claims (8)
1. synchronous element that is used for asynchronous pulse is converted to synchronization pulse, described synchronous element receives an input signal and a clock signal and exports an output signal, and receive a reset signal, be used for described output signal is resetted, described synchronous element comprises:
One first trigger, have a data input pin, a clock input end, a RESET input, reach a state output end, the input end of clock of described first trigger is coupled to described input signal, and the data input pin of described first trigger is coupled to a noble potential;
One second trigger, have a data input pin, a clock input end, a RESET input, reach a state output end, the data input pin of described second trigger is coupled to the state output end of described first trigger, the described input end of clock of described second trigger is coupled to described clock signal, and the RESET input of described second trigger is coupled to described reset signal;
One first with door, have a first input end, one second input end, an and output terminal, described first is coupled to the state output end of described second trigger with the first input end of door;
One the 3rd trigger, have a data input pin, a clock input end, a RESET input, reach a state output end, the data input pin of described the 3rd trigger be coupled to described first with the door output terminal, the input end of clock of described the 3rd trigger is coupled to described clock signal, the RESET input of described the 3rd trigger is coupled to described reset signal, and the state output end of described the 3rd trigger is exported described output signal;
One phase inverter has an input end and an output terminal, and the input end of described phase inverter is coupled to described clock signal;
One the 4th trigger, have a data input pin, a clock input end, a RESET input, reach a complementary state output terminal, the data input pin of described the 4th trigger is coupled to the state output end of described the 3rd trigger, the input end of clock of described the 4th trigger is coupled to the output terminal of described phase inverter, described the RESET input of described the 4th trigger is coupled to described reset signal, the complementary state output terminal of described the 4th trigger be coupled to described first with the door second input end;
One Sheffer stroke gate has two input ends and an output terminal, and described two input ends are coupled to the state output end of described the 3rd trigger and the complementary state output terminal of described the 4th trigger respectively; And
One second with the door, have two input ends and an output terminal, described two input ends are coupled to the output terminal of described reset signal and described Sheffer stroke gate respectively, described output terminal is coupled to the RESET input of described first trigger.
2. the synchronous element that is used for asynchronous pulse is converted to synchronization pulse as claimed in claim 1, wherein said input signal are a pulse signal.
3. the synchronous element that is used for asynchronous pulse is converted to synchronization pulse as claimed in claim 1, wherein said first trigger is a D flip-flop.
4. the synchronous element that is used for asynchronous pulse is converted to synchronization pulse as claimed in claim 1, wherein said second trigger is a D flip-flop.
5. the synchronous element that is used for asynchronous pulse is converted to synchronization pulse as claimed in claim 1, wherein said the 3rd trigger is a D flip-flop.
6. the synchronous element that is used for asynchronous pulse is converted to synchronization pulse as claimed in claim 1, wherein said the 4th trigger is a D flip-flop.
7. synchronous element that is used for asynchronous pulse is converted to synchronization pulse, described synchronous element receives an input signal and a clock signal and exports an output signal, wherein said input signal is a pulse signal, and described synchronous element comprises:
One first trigger receives described input signal, and the signal of its state output end is changed into another state in the forward position of described input signal;
One second trigger, receive the signal of the state output end of described first trigger, after the signal of the state output end of described first trigger becomes another state, at the pulse front edge subsequently of described clock signal, be another state with the signal change of the state output end of described second trigger;
One the 3rd trigger, receive the signal of the state output end of described second trigger, the signal of the state output end of described the 3rd trigger is described output signal, after the signal of the state output end of described second trigger becomes another state, at the pulse front edge subsequently of described clock signal, be another state with the signal change of the state output end of described the 3rd trigger; And
One the 4th trigger, receive the signal of the state output end of described the 3rd trigger, behind the signal change state of the state output end of described the 3rd trigger, at the pulse back edge subsequently of described clock signal, with the signal change of the state output end of described the 4th trigger is another state
The signal of the state output end of described the 4th trigger is delivered to described first trigger and described the 3rd trigger, after the signal of the state output end of described the 3rd trigger becomes another state, the signal of the state output end of described first trigger is reverted to original state, and pulse front edge subsequently in described clock signal, the signal of the state output end of described the 3rd trigger is reverted to original state
After the signal with the state output end of described first trigger reverts to original state,, the signal of the state output end of described second trigger is reverted to original state at the pulse front edge subsequently of described clock signal; After the signal with the state output end of described the 3rd trigger reverts to original state,, the signal of the state output end of described the 4th trigger is reverted to original state at the pulse back edge subsequently of described clock signal.
8. the synchronous element that is used for asynchronous pulse is converted to synchronization pulse as claimed in claim 7, also receive a reset signal, when adding the above reset signal, described first trigger, described second trigger, described the 3rd trigger, and the signal of the state output end of described the 4th trigger revert to original state.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB991248163A CN1167989C (en) | 1999-11-18 | 1999-11-18 | Synchronizer for converting asynchronous pulse signals to synchronous ones |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB991248163A CN1167989C (en) | 1999-11-18 | 1999-11-18 | Synchronizer for converting asynchronous pulse signals to synchronous ones |
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| CN1297173A true CN1297173A (en) | 2001-05-30 |
| CN1167989C CN1167989C (en) | 2004-09-22 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100359669C (en) * | 2004-04-30 | 2008-01-02 | 印芬龙科技股份有限公司 | Method and circuit arrangement for resetting an integrated circuit |
| CN102012717A (en) * | 2010-11-16 | 2011-04-13 | 青岛海信信芯科技有限公司 | Clock switching method and device |
| CN103814339A (en) * | 2011-09-21 | 2014-05-21 | 高通股份有限公司 | Systems and methods for asynchronous handshake-based interconnects |
| CN104143354A (en) * | 2013-05-08 | 2014-11-12 | 罗伯特·博世有限公司 | Memory device |
-
1999
- 1999-11-18 CN CNB991248163A patent/CN1167989C/en not_active Expired - Lifetime
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100359669C (en) * | 2004-04-30 | 2008-01-02 | 印芬龙科技股份有限公司 | Method and circuit arrangement for resetting an integrated circuit |
| CN102012717A (en) * | 2010-11-16 | 2011-04-13 | 青岛海信信芯科技有限公司 | Clock switching method and device |
| CN102012717B (en) * | 2010-11-16 | 2012-10-03 | 青岛海信信芯科技有限公司 | Clock switching method and device |
| CN103814339A (en) * | 2011-09-21 | 2014-05-21 | 高通股份有限公司 | Systems and methods for asynchronous handshake-based interconnects |
| CN103814339B (en) * | 2011-09-21 | 2016-05-11 | 高通股份有限公司 | For the system and method for the asynchronous interlinkage based on shaking hands |
| CN104143354A (en) * | 2013-05-08 | 2014-11-12 | 罗伯特·博世有限公司 | Memory device |
| CN104143354B (en) * | 2013-05-08 | 2018-09-21 | 罗伯特·博世有限公司 | Memory devices |
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| Publication number | Publication date |
|---|---|
| CN1167989C (en) | 2004-09-22 |
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