CN1292563C - Apparatus for realizing Ethernet managing interface - Google Patents
Apparatus for realizing Ethernet managing interface Download PDFInfo
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- CN1292563C CN1292563C CN 03131819 CN03131819A CN1292563C CN 1292563 C CN1292563 C CN 1292563C CN 03131819 CN03131819 CN 03131819 CN 03131819 A CN03131819 A CN 03131819A CN 1292563 C CN1292563 C CN 1292563C
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Abstract
The present invention relates to a device for realizing Ethernet management interfaces, particularly to a device for realizing management interfaces specified in the IEEE802.3 standard Clause45. The device of the present invention for realizing management interfaces is logically divided into four modules comprising an asynchronous data read-write module, a displacement enabled module, a displacement input module and a displacement output module, wherein the asynchronous data read-write module adopts asynchronous logic, and the other modules adopt synchronous logic and adopt the same clock; the sensitive variable of each module comprises a reset signal, and when the reset signal is effective, the initialized configuration of some registers in the corresponding module is completed. By adopting the present invention, PHY chips can be conveniently managed, and especially when no MAC chips exist on a line card or external management interfaces are not supported by MAC chips, PHY chips can be controlled and managed under the condition of little occupation of CPU (microprocessor) resources.
Description
Technical field
The present invention relates to a kind of device of realizing ethernet management interface, particularly a kind of device of realizing defined management interface among the IEEE802.3 standard C lause45.
Background technology
In ethernet switching device, general Ethernet ply-yarn drill all can provide a plurality of ethernet ports, in ply-yarn drill, generally can use a plurality of PHY (physical layer interface chip) chip like this,, will use ethernet management interface in order to realize management and control to a plurality of PHY chips.Its topology as shown in Figure 1.
In Fig. 1, STA refers to the management station in the management interface, generally is embedded in the MAC layer chip, and MMD refers to the manageable PHY device of management interface.The system configuration of Fig. 2 for realizing that management interface is used.
In the IEEE802.3 ethernet standard, Clause22 and Clause45 are described ethernet management interface, and wherein Clause22 stipulates 10M, 100M, 1000M ethernet management interface function.Clause45 expands management interface function among the Clause22, is primarily aimed at 10G Ethernet PHY chip, has expanded register address space, can visit more register.Management interface adopts a kind of two-wire serial port protocol standard, and one is clock line MDC, and one is two-way data wire MDIO, and the mode of employing indirect addressing realizes the addressing to the PHY register.
Summary of the invention
According to the regulation among the IEEE802.3 standard C lause45, the technical problem to be solved in the present invention provides a kind of device of ethernet management interface, to realize management and the control to the PHY chip.
The present invention is achieved in that
A kind of device of realizing ethernet management interface is characterized in that: described device comprises:
The asynchronous data module for reading and writing is used to finish sheet choosing and the reading and writing data that carries out the asynchronous logic operation note that define;
The shift enable module is used to finish the framing that triggers displacement output, disable shift output and data format;
The displacement input module is used to finish to whether the judgement of importing data being arranged, and realize the data shift input, and the data of being read are write read data register, and set DSR register;
The displacement output module, the input displacement detection when being used to finish data shift output and triggering read operation;
Described asynchronous data module for reading and writing adopts asynchronous logic, and described shift enable module, displacement input and output module adopt synchronous logic, and adopt same clock;
The responsive variable of described each module also comprises reset signal, finishes the initial configuration of register in the corresponding module when reset signal is effective.
The register of described asynchronous data module for reading and writing definition carrying out asynchronous logic action need comprises write data register, read data register, type of device register, device ID register, DSR register, shift enable register, operation register;
Utilize read-write operation signal, address and the data wire of microprocessor to finish read-write to these data registers.
Described shift enable module comprises: init state and displaced condition,
Described init state is forbidden the needed clock of output displacement, thus the work of disable shift module; Detecting the shift enable buffer status, judge whether to enable displacement, is the displaced condition work that then goes to, otherwise keeps init state,
Described displaced condition provides shift counter that the figure place of displacement is counted, and disable shift clock then when reaching desired count value forwards init state simultaneously to, waits for displacement next time; Otherwise open always shift clock is carried out data shift,
Described shift enable module is finished the framing of IEEE802.3 regulation MDIO interface data form, 64 altogether, 32 leading characters, two bit manipulation sign indicating numbers, five ID number, five device type positions, two TA positions, 16 bit data position or address bits.
Described displacement input module detects input displacement sampling trigger, detecting triggering signal then begins the data on the MDIO data wire are sampled, to preceding 36 bit comparisons in 36 bit data that sample and the read data operation frame, judged whether that data arrive, had data then to begin to import data shift, simultaneously data bit counting moving into, when meeting the requirements of count value, stop the displacement input, the data of being read are write read data register, and set DSR register.
Described displacement output module is shifted to the address function data or the read-write operation data of the output that will be shifted, employing is shifted out data by the trailing edge of shift clock, the physical layer interface chip is in rising edge clock sampling input, and the MDC clock of shift clock and output adopts same clock.
The read data of described each register of asynchronous data module for reading and writing adopts the trailing edge of read signal to trigger latch data, write data adopts the rising edge of write signal to trigger latch data, the width of data/address bus is 8, utilizes read-write operation signal, address and the data wire of microprocessor to finish read-write operation to the MMD chip.
Required 64 bit register SHFTOUT, 9 bit shift counter OUTCOUNT, state variable MY_STATE, the shift clock enable signal of definition framing in described this module of shift enable module,
Described shift enable module adopts the rising edge of shift clock as responsive variable,
At first forbid the needed clock of output displacement in the init state, thus the work of disable shift module; Detecting the shift enable buffer status, judge whether to enable displacement, is then to forward displaced condition work at next cycle, finishes the framing of displacement dateout form, the clock of open at last displacement output in this cycle according to concrete opcode value simultaneously; Otherwise still keep init state,
Provide shift counter to come the figure place of displacement is counted in the displaced condition, disable shift clock then when reaching desired count value, simultaneously forward init state to, wait for displacement next time, otherwise open always shift clock is carried out data shift at next cycle.
Described displacement input module definition displacement input 64 bit data register SHIFIN, input signal detection signal RDIN, input shift counter INCOUNT, input Data Detection register DETECTPRE, MDIO serial data input buffer register MDIOBUF.
Described displacement output module, definition displacement output counter COUNT in this module, output enable signal OUTEN, MDIO serial output signal MDIOOUT,
At first open output enable in the described displacement output module; Address function data or read-write operation data to the output that will be shifted are shifted then,
Described shift module is counted the figure place of output displacement, for data writing operation and address function, when reaching certain count value, forbids the output enable signal; To read data operation, because the TA sign indicating number is made up of a high-impedance state and a logical zero, so when the count value of counter is specific value, will realize forbidding or enabling the output enable signal; Finish displacement output for write operation; Then also to finish the operation of reading to trigger input displacement sampling for read operation.
Employing the method for the invention can realize the management to the PHY chip very easily, when especially on ply-yarn drill, not having MAC chip or MAC chip not to support the external management interface, control and the management that realizes under CPU (microprocessor) the resource situation seldom the PHY chip can taken.
Description of drawings
Fig. 1 is that management station is connected topological diagram with the PHY chip;
Fig. 2 is a functional block diagram of realizing the MDIO logic with programming device;
Fig. 3 is the read operation flow chart;
Fig. 4 is the write operation flow chart;
Fig. 5 is a module composition frame chart of the present invention;
Fig. 6 is the asynchronous read and write module frame chart;
Fig. 7 is a shift enable module flow chart;
Fig. 8 is a displacement input module flow chart;
Fig. 9 is a displacement output module flow chart.
Embodiment
Below in conjunction with accompanying drawing, the enforcement of technical scheme is described in further detail.
Realization management interface logic of the present invention is divided into four modules, is respectively asynchronous data module for reading and writing, shift enable module, displacement input module, displacement output module, as shown in Figure 5.Wherein the asynchronous data module for reading and writing adopts asynchronous logic, other three modules adopt synchronous logic, and adopting same clock, the responsive variable of each module also comprises reset signal, finishes the initial configuration of some registers in this module when reset signal is effective.
The flow process of read-write operation is seen Fig. 3 and Fig. 4, wherein WRRDY is that write operation is ready to register, DEVID is a device ID register, DEVTYPE is the type of device register, and ADDRL is low eight bit address register, and ADDRH is the high eight-bit address register, SHIFTEN is the shift enable register, RDRDY is that read data is ready to register, and WRDATAL is low eight write data registers, and WRDATAH is the high eight-bit write data register.
As module among Fig. 51 is the asynchronous data module for reading and writing, in this module, define the register that carries out the asynchronous logic action need and comprise write data register, read data register, type of device register, device ID register, DSR register, shift enable register, operation register; Utilize read-write operation signal, address and the data wire of CPU to finish read-write to these data registers.
As module among Fig. 52 is the shift enable module, two states of this module definition: init state and displaced condition, wherein forbid the needed clock of output displacement in the init state, thereby disable shift module work, also detect the shift enable buffer status simultaneously, judge whether to enable displacement, enable displacement and then forward displaced condition work to, otherwise still keep init state; Displaced condition provides shift counter to come the figure place of displacement is counted, and disable shift clock then when reaching desired count value forwards init state simultaneously to, wait for displacement next time, otherwise open always shift clock is carried out data shift.The shift enable module is also finished the framing of the MDIO interface data form of IEEE802.3 regulation, 64 altogether, 32 leading characters, two bit manipulation sign indicating numbers, five ID number, five device type positions, two TA positions, 16 bit data position or address bits.
Be the displacement input module as module among Fig. 53, detect input displacement sampling trigger in this module, detecting triggering signal then begins the data on the MDIO data wire are sampled, judged whether that data arrive, if having data to arrive then begin to import data shift, the data bit counting to moving into simultaneously, when meeting the requirements of count value, stop the displacement input, the data of being read are write read data register, and set DSR register.
Be the displacement output module as module among Fig. 54, this module is shifted to the address function data or the read-write operation data of the output that will be shifted, the foundation of PHY chip input data and the constraint of retention time have been stipulated among the IEEE802.3, in order to satisfy this constraint, adopt trailing edge to shift out data among the present invention by shift clock, the PHY chip is in rising edge clock sampling input, the MDC clock of shift clock and output adopts the method for same clock, rather than the method that adopts delay to export, the method that postpones output realizes cumbersome with programmable logic device, and the general technological level that also can be subject to device, adopt trailing edge displacement output then very convenient, can not be subject to the technological level of device, can also well satisfy the foundation of stipulating among the IEEE802.3 and the constraint of retention time.
Described each module further describes as follows:
As Fig. 6 is the asynchronous data module for reading and writing, in this module, define the register that carries out the asynchronous logic action need and comprise low eight write data register WRDATAL, high eight-bit write data register WRDATAH, low eight place readings are according to register RDDATAL, high eight-bit read data register RDDATAH, and type of device register DEVTYPE, device ID register DEVID, write operation are ready to register WRRDY, shift enable register SHIFTEN, read data is ready to register RDRDY; This module mainly is to finish the sheet choosing and the data write of defined each register, and the sheet choosing of each register utilizes the sheet choosing and the address wire logical operation of CPU output to realize that the width of data/address bus can be 8.Read data adopts the trailing edge of read signal to trigger latch data, and write data adopts the rising edge of write signal to trigger latch data.Utilize read-write operation signal, address and the data wire of CPU and read-write operation flow process to finish read-write operation to the MMD chip.
As Fig. 7 is shift enable module flow chart, required 64 bit register SHFTOUT, 9 bit shift counter OUTCOUNT, state variable MY_STATE, the shift clock enable signal of definition framing in this module.The rising edge that adopts shift clock in this module is as responsive variable, two states of this module definition: init state and displaced condition.At first forbid the needed clock of output displacement in the init state, thus the work of disable shift module; Detect the shift enable buffer status simultaneously, judge whether to enable displacement.If shift enable then forward displaced condition work at next cycle; Simultaneously finish the framing of displacement dateout form, the MDIO interface data form of IEEE802.3 regulation, 64 altogether according to concrete opcode value in this cycle, 32 leading characters, two bit manipulation sign indicating numbers, five ID number, five device type positions, two TA positions, 16 bit data position or address bits; The clock of open at last displacement output.Otherwise still keep init state.Provide shift counter to come the figure place of displacement is counted in the displaced condition, disable shift clock then when reaching desired count value, simultaneously forward init state to, wait for displacement next time, otherwise open always shift clock is carried out data shift at next cycle.
As Fig. 8 is displacement input module flow chart, definition displacement input 64 bit data register SHIFIN, input signal detection signal RDIN, input shift counter INCOUNT, input Data Detection register DETECTPRE, MDIO serial data input buffer register MDIOBUF in this module.This module detects input displacement sampling trigger, detecting triggering signal then begins the data on the MDIO data wire are sampled, to preceding 36 bit comparisons in 36 bit data that sample and the read data operation frame, judged whether that data arrive, if have data to arrive then begin to import data shift, data bit counting to moving into when meeting the requirements of count value, stops the displacement input simultaneously; The data of being read are write read data register, and set DSR register, the expression DSR can read.
Be displacement output module flow chart as Fig. 9, definition displacement output counter COUNT in this module, output enable signal OUTEN, MDIO serial output signal MDIOOUT.Because the IEEE802.3 standard code, the output of management interface data wire should be high resistant at one's leisure, so the output enable signal that will have the ternary register of control output to enable in this module.At first open output enable in this module; Address function data or read-write operation data to the output that will be shifted are shifted then.The foundation of PHY chip input data and the constraint of retention time have been stipulated among the IEEE802.3, in order to satisfy this constraint, adopt trailing edge to shift out data among the present invention by shift clock, the PHY chip is in rising edge clock sampling input, the MDC clock of shift clock and output adopts the method for same clock, rather than the method that adopts delay to export, the method that postpones output realizes cumbersome with programmable logic device, and the general technological level that also can be subject to device, adopt trailing edge displacement output then very convenient, can not be subject to the technological level of device, can also well satisfy the foundation of stipulating among the IEEE802.3 and the constraint of retention time.Also the figure place of output displacement is counted in this module, for data writing operation and address function, when reaching certain count value, forbid the output enable signal, read data is operated, because the TA sign indicating number is made up of a high-impedance state and a logical zero, so the function that when the count value of counter is specific value, will realize forbidding or enabling the output enable signal.As long as it is just passable to finish the displacement output function for write operation in this module, and also to finish the operation of reading to trigger input displacement sampling for read operation.
Claims (9)
1. device of realizing ethernet management interface, it is characterized in that: described device comprises:
The asynchronous data module for reading and writing is used to finish sheet choosing and the reading and writing data that carries out the asynchronous logic operation note that define;
The shift enable module is used to finish the framing that triggers displacement output, disable shift output and data format;
The displacement input module is used to finish to whether the judgement of importing data being arranged, and realize the data shift input, and the data of being read are write read data register, and set DSR register;
The displacement output module, the input displacement detection when being used to finish data shift output and triggering read operation;
Described asynchronous data module for reading and writing adopts asynchronous logic, described shift enable module, displacement input and output module adopt synchronous logic, and adopt same clock, communication is connected wherein said asynchronous data module for reading and writing with the displacement input module with described shift enable module respectively, described shift enable module is connected with the communication of displacement input module and the shift clock enable signal is passed to the displacement output module, and described displacement output module is connected with the communication of displacement input module and the inspection beginning that will be shifted can be passed to the displacement input module by signal;
The responsive variable of described each module also comprises reset signal, finishes the initial configuration of register in the corresponding module when reset signal is effective.
2. realize the device of ethernet management interface according to claim 1, it is characterized in that:
The register of described asynchronous data module for reading and writing definition carrying out asynchronous logic action need comprises write data register, read data register, type of device register, device ID register, DSR register, shift enable register, operation register;
Utilize read-write operation signal, address and the data wire of microprocessor to finish read-write to these data registers.
3. realize the device of ethernet management interface according to claim 1, it is characterized in that:
Described shift enable module comprises: init state and displaced condition,
Described init state is forbidden the needed clock of output displacement, thus the work of disable shift module; Detecting the shift enable buffer status, judge whether to enable displacement, is the displaced condition work that then goes to, otherwise keeps init state,
Described displaced condition provides shift counter that the figure place of displacement is counted, and disable shift clock then when reaching desired count value forwards init state simultaneously to, waits for displacement next time; Otherwise open always shift clock is carried out data shift,
Described shift enable module is finished the framing of IEEE802.3 regulation MDIO interface data form, 64 altogether, 32 leading characters, two bit manipulation sign indicating numbers, five ID number, five device type positions, two TA positions, 16 bit data position or address bits.
4. realize the device of ethernet management interface according to claim 1, it is characterized in that:
Described displacement input module detects input displacement sampling trigger, detecting triggering signal then begins the data on the MDIO data wire are sampled, to preceding 36 bit comparisons in 36 bit data that sample and the read data operation frame, judged whether that data arrive, had data then to begin to import data shift, simultaneously data bit counting moving into, when meeting the requirements of count value, stop the displacement input, the data of being read are write read data register, and set DSR register.
5. realize the device of ethernet management interface according to claim 1, it is characterized in that:
Described displacement output module is shifted to the address function data or the read-write operation data of the output that will be shifted, employing is shifted out data by the trailing edge of shift clock, the physical layer interface chip is in rising edge clock sampling input, and the MDC clock of shift clock and output adopts same clock.
6. realize the device of ethernet management interface as claimed in claim 1 or 2, it is characterized in that:
The read data of described each register of asynchronous data module for reading and writing adopts the trailing edge of read signal to trigger latch data, write data adopts the rising edge of write signal to trigger latch data, the width of data/address bus is 8, utilizes read-write operation signal, address and the data wire of microprocessor to finish read-write operation to the MMD chip.
7. as the device of realization ethernet management interface as described in claim 1 or 3, it is characterized in that:
Required 64 bit register SHFTOUT, 9 bit shift counter OUTCOUNT, state variable MY_STATE, the shift clock enable signal of definition framing in described this module of shift enable module.
Described shift enable module adopts the rising edge of shift clock as responsive variable,
At first forbid the needed clock of output displacement in the init state, thus the work of disable shift module; Detecting the shift enable buffer status, judge whether to enable displacement, is then to forward displaced condition work at next cycle, finishes the framing of displacement dateout form, the clock of open at last displacement output in this cycle according to concrete opcode value simultaneously; Otherwise still keep init state,
Provide shift counter to come the figure place of displacement is counted in the displaced condition, disable shift clock then when reaching desired count value, simultaneously forward init state to, wait for displacement next time, otherwise open always shift clock is carried out data shift at next cycle.
8. as the device of realization ethernet management interface as described in claim 1 or 4, it is characterized in that:
Described displacement input module definition displacement input 64 bit data register SHIFIN, input signal detection signal RDIN, input shift counter INCOUNT, input Data Detection register DETECTPRE, MDIO serial data input buffer register MDIOBUF.
9. realize the device of ethernet management interface as claim 1 or 5, it is characterized in that:
Described displacement output module, definition displacement output counter COUNT in this module, output enable signal OUTEN, MDIO serial output signal MDIOOUT,
At first open output enable in the described displacement output module; Address function data or read-write operation data to the output that will be shifted are shifted then,
Described shift module is counted the figure place of output displacement, for data writing operation and address function, when reaching certain count value, forbids the output enable signal; To read data operation, because the TA sign indicating number is made up of a high-impedance state and a logical zero, so when the count value of counter is specific value, will realize forbidding or enabling the output enable signal; Finish displacement output for write operation; Then also to finish the operation of reading to trigger input displacement sampling for read operation.
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| CN107703815A (en) * | 2017-10-29 | 2018-02-16 | 北京联合大学 | Circulate the line SPI communication systems of address formula three |
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| CN101141676B (en) * | 2007-06-19 | 2010-08-18 | 中兴通讯股份有限公司 | Method for preventing network broadcasting windstorm |
| CN101404645B (en) * | 2008-04-29 | 2011-11-16 | 华为技术有限公司 | Multiport Ethernet interface, its implementing method and physical layer interface |
| CN101304342B (en) * | 2008-06-27 | 2010-11-24 | 电子科技大学 | Enhancement type Ethernet interface apparatus |
| KR20100083395A (en) * | 2009-01-13 | 2010-07-22 | 삼성전자주식회사 | Method of parallel interfacing and devices using the same |
| CN105681479A (en) * | 2016-01-30 | 2016-06-15 | 安徽欧迈特数字技术有限责任公司 | Transmission method of multi-port Ethernet interface |
| CN108259388B (en) * | 2017-05-17 | 2021-04-27 | 新华三技术有限公司 | Control method and device for managing Ethernet interface |
| CN109165176B (en) * | 2018-07-27 | 2020-10-27 | 北京无线电测量研究所 | Amplitude-phase control chip and bus type data transmission assembly |
| CN110175145B (en) * | 2019-05-23 | 2021-07-06 | 深圳市易飞扬通信技术有限公司 | MDIO interface communication method and circuit |
| CN113360191B (en) * | 2020-03-03 | 2022-05-27 | 杭州海康威视数字技术股份有限公司 | Driving device of network switching chip |
| CN111949574B (en) * | 2020-06-30 | 2023-10-20 | 厦门汉印电子技术有限公司 | Bus bit number judging method, device, equipment and readable storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107703815A (en) * | 2017-10-29 | 2018-02-16 | 北京联合大学 | Circulate the line SPI communication systems of address formula three |
| CN107703815B (en) * | 2017-10-29 | 2020-04-24 | 北京联合大学 | Circulating address type three-wire SPI communication system |
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