CN111949574B - Bus bit number judging method, device, equipment and readable storage medium - Google Patents
Bus bit number judging method, device, equipment and readable storage medium Download PDFInfo
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- CN111949574B CN111949574B CN202010616181.6A CN202010616181A CN111949574B CN 111949574 B CN111949574 B CN 111949574B CN 202010616181 A CN202010616181 A CN 202010616181A CN 111949574 B CN111949574 B CN 111949574B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
- B41J29/00—Details of, or accessories for, typewriters or selective printing mechanisms not otherwise provided for
- B41J29/38—Drives, motors, controls or automatic cut-off devices for the entire printing mechanism
- B41J29/393—Devices for controlling or analysing the entire machine ; Controlling or analysing mechanical parameters involving printing of test patterns
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
Abstract
The application provides a method, a device, equipment and a readable storage medium for judging bus bit number, wherein the method comprises the following steps: resetting a plurality of shift registers in the head piece; inputting preset first data into each shift register, inputting preset number of 0 data, sampling output signals of each shift register, and storing the output signals of each shift register; comparing the output signal of each shift register with the first data to obtain a shift register effectively existing in the plurality of shift registers; and acquiring the bus bit number in the head chip according to the effectively existing shift register. Based on the application, the data bus bit number of the thermal print head can be simply and efficiently identified.
Description
Technical Field
The present application relates to the field of buses, and in particular, to a method, an apparatus, a device, and a readable storage medium for determining a number of bus bits.
Background
The control signals of the thermal print head comprise a clock clk, input data DIN, output data DOUT, latch and heat Strobe signals, the number of bits of the data bus is different for different print heads, for example, a plurality of bus numbers such as 1,2,4 and the like exist, and for a product which needs to be compatible with a plurality of print heads, how to simply and efficiently identify the number of bits of the data bus of the head chip is very important.
In the prior art, the type of the head piece can be identified by adding an electric signal generated by a circuit on the board, and the head piece matched with the board is firstly adapted in advance during production or use, so that the process is complicated.
In addition, the device can be controlled by matching different programs with different headpieces, but the device can lead to a plurality of versions for maintenance, and the maintenance is very difficult.
In view of this, the present application has been proposed.
Disclosure of Invention
The application discloses a bus bit number judging method, a device, equipment and a readable storage medium, which aim to simply and efficiently identify the data bus bit number of a thermal print head.
The first embodiment of the application provides a method for judging the number of bus bits, which comprises the following steps:
resetting a plurality of shift registers in the head piece;
inputting preset first data into each shift register, inputting preset number of 0 data, sampling output signals of each shift register, and storing the output signals of each shift register;
comparing the output signal of each shift register with the first data to obtain a shift register effectively existing in the plurality of shift registers;
and acquiring the bus bit number in the head chip according to the effectively existing shift register.
Preferably, the clearing of the shift registers in the header is specifically:
and shifting each shift register into 0 data exceeding the number of points in the head chip through a clock signal and a plurality of input signals, and resetting the plurality of shift registers.
Preferably, a predetermined first data is input to each shift register, and a predetermined number of 0 data is input, and at the same time, an output signal of each shift register is sampled, and the output signal of each shift register is saved, specifically:
firstly, inputting preset first data into the shift register according to a clock signal and a current input signal,
then, inputting 0 data exceeding the number of the internal points of the head chip into the current shift register, sampling the output signal of the current shift register through a clock signal, and storing the output signal of the current shift register;
repeating the steps until the output signal of each shift register is saved.
Preferably, the comparing the output signal of each shift register with the first data to obtain a shift register effectively existing in the plurality of shift registers, specifically:
judging whether the output signal of the shift register contains the first data or not;
if yes, judging that the shift register is valid currently;
if not, judging that the shift register is invalid currently;
repeating the steps until the validity of each shift register is judged.
A second embodiment of the present application provides a bus bit number judging device, including:
the zero clearing unit is used for zero clearing the plurality of shift registers in the head piece;
an output signal sampling unit, configured to input predetermined first data into each shift register, input a predetermined number of 0 data into the shift register, sample an output signal of each shift register, and store an output signal of each shift register;
a comparing unit, configured to compare an output signal of each shift register with the first data, so as to obtain a shift register that is effectively present in the plurality of shift registers;
and the bus bit number acquisition unit is used for acquiring the bus bit number in the header according to the effectively existing shift register.
Preferably, the clearing unit is specifically configured to: and shifting each shift register into 0 data exceeding the number of points in the head chip through a clock signal and a plurality of input signals, and resetting the plurality of shift registers.
Preferably, the output signal sampling unit is specifically configured to:
firstly, inputting preset first data into the shift register according to a clock signal and a current input signal,
then inputting 0 data exceeding the number of the internal points of the header, sampling the output signal of the shift register through a clock signal, and storing the output signal of the shift register;
repeating the steps until the output signal of each shift register is saved.
Preferably, the comparing unit is specifically configured to:
judging whether the output signal of the shift register contains the first data or not;
if yes, judging that the shift register is valid currently;
if not, judging that the shift register is invalid currently;
repeating the steps until the validity of each shift register is judged.
A third embodiment of the present application provides a bus number judgment device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, the processor executing the computer program to implement a bus number judgment method as set forth in any one of the above.
A fourth embodiment of the present application provides a readable storage medium storing a computer program executable by a processor of a device in which the storage medium is located to implement a method for determining a number of bus bits as set forth in any one of the above.
According to the method, the device, the equipment and the readable storage medium for judging the bus bit number, the plurality of shift registers in the head piece are cleared, each shift register is shifted into preset first data, the current shift register is shifted into 0 data exceeding the number of the head piece, the output signal of the current shift register is sampled through a clock signal, when the data in the output signal is judged to contain the first data, the shift register is judged to be valid, if the data in the output signal is judged not to contain the first data, the shift register is judged to be invalid, the execution is repeated until the existence condition of the shift registers on all the head pieces is obtained, and the data bus bit number of the thermal print head piece is simply and efficiently identified according to the shift registers which exist on the head piece effectively.
Drawings
FIG. 1 is a block diagram of a method for determining the number of bus bits according to a first embodiment of the present application;
FIG. 2 is a schematic diagram of the signal structure of a head piece;
FIG. 3 is a block diagram showing a bus number judgment device according to a third embodiment of the present application;
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
For a better understanding of the technical solution of the present application, the following detailed description of the embodiments of the present application refers to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
Depending on the context, the word "if" as used herein may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to detection". Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.
References to "first\second" in the embodiments are merely to distinguish similar objects and do not represent a particular ordering for the objects, it being understood that "first\second" may interchange a particular order or precedence where allowed. It is to be understood that the "first\second" distinguishing objects may be interchanged where appropriate to enable the embodiments described herein to be implemented in sequences other than those illustrated or described herein.
Specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.
The application discloses a bus bit number judging method, a device, equipment and a readable storage medium, which aim to simply and efficiently identify the data bus bit number of a thermal print head.
Referring to fig. 1, a first embodiment of the present application provides a method for determining a number of bus bits, including:
s101, resetting a plurality of shift registers in a head piece;
it should be noted that, the control signal of the head chip generally includes an input signal, an output signal, a clock signal, a latch signal and a strobe signal, the signal block diagram of the head chip is shown in fig. 2, but the bus bits of different printheads are different, and the controller of the printer needs to determine the bus bits of the head chip before sending the control signal.
In this embodiment, each input signal corresponds to an input end of a shift register, and 0 data exceeding the number of points in the head chip is shifted into the shift register by using a rising edge of a clock signal, so as to clear a plurality of shift registers.
S102, inputting preset first data into each shift register, inputting preset number of 0 data, sampling output signals of each shift register, and storing the output signals of each shift register;
in this embodiment, a set of regular first data may be shifted into the shift register at the rising edge of the clock signal, where the first data may be a set of equal ratio columns, an equal difference column, or the like, which is not limited herein.
Then, 0 data exceeding the number of the internal points of the head piece is moved into the current shift register, the output signal of the current shift register is sampled through the rising edge of the clock signal, and the output signal of the current shift register is stored;
repeating the steps until the output signal of each shift register is saved.
S103, comparing the output signal of each shift register with the first data to obtain a shift register effectively existing in the plurality of shift registers;
it should be noted that, after the register moves into the first data, the first data is moved into 0 data exceeding the number of points in the header, if the current shift register is a valid register, the first data is moved out of the current shift register, that is, the first data is stored in the output signal.
Judging whether the output signal of the shift register contains the first data or not;
when the output signal is judged to contain the first data, judging that the shift register is valid currently;
when the output signal is judged to not contain the first data, judging that the shift register is invalid currently;
repeating the steps until the validity of each shift register is judged.
S104, obtaining the bus bit number in the head chip according to the effectively existing shift register.
When the effective number of shift registers in the head chip is determined, the number of data lines connected to the head chip shift registers by the controller of the printer can be determined.
In summary, a plurality of shift registers in the head chip are cleared, each shift register is shifted into preset first data, the current shift register is shifted into 0 data exceeding the number of the head chip, an output signal of the current shift register is sampled through a clock signal, when the data in the output signal is judged to contain the first data, the shift register is judged to be valid, if the data in the output signal is judged not to contain the first data, the shift register is judged to be invalid, and the execution is repeated until the existence condition of the shift registers on all the head chips is acquired, and the data bus bit number of the thermal print head chip is simply and efficiently identified according to the shift registers which exist effectively on the head chip.
Referring to fig. 3, a second embodiment of the present application provides a bus bit number determining apparatus, including:
a clearing unit 201, configured to clear a plurality of shift registers in the header;
an output signal sampling unit 202, configured to input predetermined first data into each shift register, input a predetermined number of 0 data, sample an output signal of each shift register, and store an output signal of each shift register;
a comparing unit 203, configured to compare the output signal of each shift register with the first data, so as to obtain a shift register that is effectively present in the plurality of shift registers;
and the bus bit number acquisition unit 204 is configured to acquire the bus bit number in the header according to the shift register that is effectively present.
Preferably, the clearing unit 201 is specifically configured to: and shifting each shift register into 0 data exceeding the number of points in the head chip through a clock signal and a plurality of input signals, and resetting the plurality of shift registers.
Preferably, the output signal sampling unit 202 is specifically configured to:
firstly, inputting preset first data into the shift register according to a clock signal and a current input signal,
then, inputting 0 data exceeding the number of the internal points of the head chip into the current shift register, sampling the output signal of the current shift register through a clock signal, and storing the output signal of the current shift register;
repeating the steps until the output signal of each shift register is saved.
Preferably, the comparing unit 203 is specifically configured to:
judging whether the output signal of the shift register contains the first data or not;
if yes, judging that the shift register is valid currently;
if not, judging that the shift register is invalid currently;
repeating the steps until the validity of each shift register is judged.
A third embodiment of the present application provides a bus number judgment device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, the processor executing the computer program to implement a bus number judgment method as set forth in any one of the above.
A fourth embodiment of the present application provides a readable storage medium storing a computer program executable by a processor of a device in which the storage medium is located to implement a method for determining a number of bus bits as set forth in any one of the above.
According to the method, the device, the equipment and the readable storage medium for judging the bus bit number, the plurality of shift registers in the head piece are cleared, each shift register is shifted into preset first data, the current shift register is shifted into 0 data exceeding the number of the head piece, the output signal of the current shift register is sampled through a clock signal, when the data in the output signal is judged to contain the first data, the shift register is judged to be valid, if the data in the output signal is judged not to contain the first data, the shift register is judged to be invalid, the execution is repeated until the existence condition of the shift registers on all the head pieces is obtained, and the data bus bit number of the thermal print head piece is simply and efficiently identified according to the shift registers which exist on the head piece effectively.
Illustratively, the computer programs described in the third and fourth embodiments of the present application may be divided into one or more modules, which are stored in the memory and executed by the processor to complete the present application. The one or more modules may be a series of computer program instruction segments capable of performing a specified function, for describing the execution of the computer program in the device for determining the number of bits of a bus. For example, the device described in the second embodiment of the present application.
The processor may be a central processing unit (Central Processing Unit, CPU), other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor, etc., which is a control center of the method for determining the number of bus bits, and various interfaces and lines are used to connect the various parts of the entire method for determining the number of bus bits.
The memory may be used to store the computer program and/or the module, and the processor may implement various functions of the method for determining the number of bus bits by running or executing the computer program and/or the module stored in the memory and calling the data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program (such as a sound playing function, a text conversion function, etc.) required for at least one function, and the like; the storage data area may store data (such as audio data, text message data, etc.) created according to the use of the cellular phone, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as a hard disk, memory, plug-in hard disk, smart Media Card (SMC), secure Digital (SD) Card, flash Card (Flash Card), at least one disk storage device, flash memory device, or other volatile solid-state storage device.
Wherein the modules may be stored in a computer readable storage medium if implemented in the form of software functional units and sold or used as a stand alone product. Based on this understanding, the present application may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and the computer program may implement the steps of each method embodiment described above when executed by a processor. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the computer readable medium contains content that can be appropriately scaled according to the requirements of jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is subject to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.
It should be noted that the above-described apparatus embodiments are merely illustrative, and the units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, in the drawings of the embodiment of the device provided by the application, the connection relation between the modules represents that the modules have communication connection, and can be specifically implemented as one or more communication buses or signal lines. Those of ordinary skill in the art will understand and implement the present application without undue burden.
The present application is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present application are intended to be included in the scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims (6)
1. A method for determining the number of bus bits, comprising:
resetting a plurality of shift registers in the head piece;
inputting preset first data into each shift register, inputting preset number of 0 data, sampling output signals of each shift register, and storing the output signals of each shift register, wherein the preset first data is input into the current shift register according to clock signals and current input signals; then, inputting 0 data exceeding the number of the internal points of the head chip into the current shift register, sampling the output signal of the current shift register through a clock signal, and storing the output signal of the current shift register; repeating the steps until the output signal of each shift register is saved;
comparing the output signal of each shift register with the first data to obtain a shift register effectively existing in the plurality of shift registers, specifically: judging whether the output signal of the shift register contains the first data or not; if yes, judging that the shift register is valid currently; if not, judging that the shift register is invalid currently; repeating the steps until the validity of each shift register is judged;
and acquiring the bus bit number in the head chip according to the effectively existing shift register.
2. The method for determining the number of bus bits according to claim 1, wherein the clearing of the plurality of shift registers in the header is specifically:
and shifting each shift register into 0 data exceeding the number of points in the head chip through a clock signal and a plurality of input signals, and resetting the plurality of shift registers.
3. A bus number judgment device, comprising:
the zero clearing unit is used for zero clearing the plurality of shift registers in the head piece;
the output signal sampling unit is used for inputting preset first data into each shift register, inputting preset number of 0 data, simultaneously sampling the output signal of each shift register, and storing the output signal of each shift register, and is particularly used for: firstly, inputting preset first data into the shift register according to a clock signal and a current input signal; then, inputting 0 data exceeding the number of the internal points of the head chip into the current shift register, sampling the output signal of the current shift register through a clock signal, and storing the output signal of the current shift register; repeating the steps until the output signal of each shift register is saved;
the comparing unit is configured to compare the output signal of each shift register with the first data, so as to obtain a shift register that is effectively present in the plurality of shift registers, and is specifically configured to: judging whether the output signal of the shift register contains the first data or not; if yes, judging that the shift register is valid currently; if not, judging that the shift register is invalid currently; repeating the steps until the validity of each shift register is judged;
and the bus bit number acquisition unit is used for acquiring the bus bit number in the header according to the effectively existing shift register.
4. A bus bit number judgment device according to claim 3, wherein the clearing unit is specifically configured to: and shifting each shift register into 0 data exceeding the number of points in the head chip through a clock signal and a plurality of input signals, and resetting the plurality of shift registers.
5. A bus number judgment device comprising a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, the processor executing the computer program to implement a bus number judgment method according to any one of claims 1 to 2.
6. A readable storage medium storing a computer program executable by a processor of a device in which the storage medium is located to implement a method of determining the number of bus bits as claimed in any one of claims 1 to 2.
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| CN110554852A (en) * | 2018-05-31 | 2019-12-10 | 赛灵思公司 | Data splicing structure and method and on-chip implementation thereof |
| CN208922244U (en) * | 2018-08-30 | 2019-05-31 | 珠海欧比特宇航科技股份有限公司 | A kind of high-speed serial bus suitable for high-performance SOC chip unstrings IP kernel |
| CN111031233A (en) * | 2019-11-13 | 2020-04-17 | 安凯(广州)微电子技术有限公司 | Digital image processing frame rate control method and device |
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