CN105740087A - Method for carrying out SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) refreshing effect verification by lookup table shift register - Google Patents
Method for carrying out SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) refreshing effect verification by lookup table shift register Download PDFInfo
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Abstract
The invention relates to a method for carrying out SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) refreshing effect verification by a lookup table shift register. The method comprises the following steps: (1) constructing a shift register group formed by lookup tables in the FPGA, and setting an initial value for the shift register group; (2) finishing the power-on configuration of the FPGA, inputting serial data into the shift register group to drive the shift register group to carry out shifting; (3) when a save value in the current shift register is different from the initial value of the shift register, stopping inputting the serial data into the shift register group; (4) refreshing the SRAM type FPGA until all storage values of the shift register group are refreshed; (5) inputting the serial data into the shift register group again to drive the shift register group to shift, and moving all save values in the shift register group; and (6) judging whether refreshing is successful or not. The method does not need to carry out an irradiation test, does not need backward read and has the characteristics of being low in cost, simple in operation and accurate in judgment.
Description
Technical field
The present invention relates to a kind of method utilizing look-up table shift register to carry out SRAM type FPGA refreshing compliance test result, the characteristic in particular with look-up table shift register judges that whether refreshing is successful, belongs to technical field of integrated circuits.
Background technology
The basic structure of SRAM type FPGA such as Fig. 1, wherein main functional module includes: four Mondays circle input/output module (IOB), edge two row block storage (BlockRAM), internal FPGA block array (CLB), in addition, also has the interconnection resources spreading all over whole circuit connection modules.Above-mentioned logical resource and interconnection resources are all controlled by lower floor's SRAM configuration bit.The substantial amounts of SRAM configuration bit spreading all over FPGA circuitry determines the concrete function of FPGA circuitry, and namely the code stream set of these configuration bits is referred to as code stream (bitstream).
When SRAM type FPGA applies in spatial environments, Energetic particle can penetrate FPGA device inside and produce ionization on path, thus causing transient current interference on circuit node and causing circuit error.Typical 6 pipe sram cells are made up of two cross-coupled phase inverters and two gate pipes for Read-write Catrol, are illustrated in figure 2 the principle of the configuration memorizer single-particle inversion of SRAM type FPGA.When high energy particle beats the sensitive area at sram cell (drain region for reverse-biased n pipe), the electric charge collection in interface creates a transient current pulse, causes that the information that this unit stores is become " 0 " by " 1 ", and state occurs in that upset.This effect is exactly space Single event upset effecf, and the upset of configuration bit state may result in serious functional fault, causes built-in function entanglement, line short circuit, open circuit etc..The fault that the upset of this configuration bit causes is permanent fault, eliminates only by reloading code stream.
Refresh technique utilizes the function that SRAM type FPGA retaking of a year or grade and part are heavily joined, and repairs the configuration sram cell that single-particle inversion occurs.The single-particle inversion occurred in configuration SRAM can being corrected, thus thoroughly eliminating single-particle inversion accumulation, user logic will not being interrupted compared with all reloading code stream, thus increasing refresh rate.Refresh technique space FPGA apply in as the widely available application of supplementary measures.Refresh the whether effective problem being to compare in application process concern, be that FPGA inside configuration bit is written and read owing to refreshing, be similar to consistency operation, refresh whether successfully lack signal designation intuitively, it is difficult to judge.In order to judge that whether refreshing is successful, it usually needs carry out retaking of a year or grade after making SRAM position overturn by irradiation test again, just be capable of determining whether Flushing success after the code stream after retaking of a year or grade is contrasted with initial code stream.Due to needs irradiation test, this method of discrimination has higher Sharp criteria, and the operation of retaking of a year or grade and code stream analysis is also sufficiently complex.
Summary of the invention
It is an object of the invention to overcome the drawbacks described above of prior art, thering is provided a kind of utilizes look-up table shift register to carry out the SRAM type FPGA method refreshing compliance test result, the method utilizes the feature of FPGA internal searching table shift register, form one and can conveniently judge refreshing whether successfully method, the method is made without irradiation test, also without retaking of a year or grade, have that cost is low, simple to operate, the feature of accuracy of judgement.
The above-mentioned purpose of the present invention is achieved mainly by following technical scheme:
Look-up table shift register is utilized to carry out the SRAM type FPGA method refreshing compliance test result, it is characterised in that:
(1), in SRAM type FPGA, build the shift register group being made up of look-up table, and initial value is set for shift register group；
(2), complete the configuration that powers on of SRAM type FPGA, drive shift register group to shift to shift register group input serial data；
(3), when, after shift register group newly immigration value, when the save value in present shift register is different from the initial value of shift register, stopping to shift register group input serial data；
(4), SRAM type FPGA is refreshed, until all storage values of shift register group are all refreshed；
(5), again to shift register group input serial data drive shift register group to shift, the save value in shift register group is all removed；
(6) whether the initial value arranged in the removal value, in contrast step (5) and step (1) is identical, if identical, judges Flushing success, if difference, judges to refresh unsuccessful.
Look-up table shift register is utilized to carry out the SRAM type FPGA method refreshing compliance test result, refresh checking system by FPGA to realize, described FPGA refreshes checking system and includes SRAM type FPGA to be refreshed, refresh module, PROM and peripheral signal module, wherein PROM is used for storing SRAM type FPGA code stream, and concrete methods of realizing is as follows:
(1), in SRAM type FPGA, build the shift register group being made up of look-up table, and initial value is set for shift register group；
(2), completing powering on of SRAM type FPGA, be that SRAM type FPGA carries out code stream configuration by PROM, peripheral signal module drives shift register group to shift to shift register group input serial data；
(3), when, after shift register group newly immigration value, when the save value in present shift register is different from the initial value of shift register, peripheral signal module can stop to shift register group input serial data；
(4), refresh module SRAM type FPGA is refreshed, until when all storage values of shift register group are all refreshed；
(5), peripheral signal module again to shift register group input serial data drive shift register group shift, the save value in shift register group is all removed；
(6) whether the initial value arranged in the removal value, in contrast step (5) and step (1) is identical, if identical, judges Flushing success, if difference, judges to refresh unsuccessful.
Look-up table shift register is utilized to carry out in the SRAM type FPGA method refreshing compliance test result above-mentioned, the shift register group being made up of look-up table includes multiple shift register cell, each shift register cell includes memory element, 2 enters 1 the first Port Multiplier and 1 gone out and enter 2 the second Port Multipliers gone out, two Port Multipliers control gating path by controlling end, select by configuration path read-write memory cell, or select by user path read-write memory cell.
Utilizing look-up table shift register to carry out in the SRAM type FPGA method refreshing compliance test result above-mentioned, in step (4), refresh step selects to be realized by configuration path read-write memory cell (202)；Shift step in described step (2), (5) selects by user path read-write memory cell (202).
Look-up table shift register is utilized to carry out in the SRAM type FPGA method refreshing compliance test result above-mentioned, in step (3), when save value in present shift register is different from the initial value of shift register, and changing value account for initial save value more than 50% time, stop to shift register group input serial data.
Look-up table shift register is utilized to carry out, in the SRAM type FPGA method refreshing compliance test result, step (4) being refreshed by the code stream of storage in PROM above-mentioned.
Look-up table shift register is utilized to carry out in the SRAM type FPGA method refreshing compliance test result above-mentioned, whether identical by the middle initial value arranged of the removal value in oscillograph, logic analyser or digital signal acquiring device contrast step (5) and step (1) in step (6).
The present invention compared with prior art has the advantages that
(1), prior art requires over irradiation test, if not possessing irradiation test condition, then cannot be carried out, the invention enables whether refreshing successfully judges to carry out under normal test chamber environment, only needing witness plate one piece common, cost significantly reduces.
(2), prior art require over retaking of a year or grade, by current code stream read and contrast with source code flow.FPGA read back operation is sufficiently complex, including synchronizing, desynchronize, arrange frame length, arranging the series of orders words such as initial address, also needs to consider the interference of independent bit when retaking of a year or grade code stream and source code flow contrast, and the technical operation of existing retaking of a year or grade contrast is sufficiently complex；The present invention has only to design a chain of registers by user logic, and controls to refresh and register shift by a small amount of signal in operation, and operational approach hinge structure is greatly simplified.
(3), the inventive method only need to carry out in test chamber environment, it is not necessary to by irradiation test, threshold is low compared to existing technology, and the inventive method has the basis for estimation of clear and definite, it is judged that method is accurate.
(4), the method for the present invention method that is applicable to any FPGA model and any refreshing, applied widely, highly versatile, there is stronger practicality.
Accompanying drawing explanation
Fig. 1 is the system assumption diagram of SRAM type FPGA；
Fig. 2 is the schematic diagram of the configuration memorizer single-particle inversion of SRAM type FPGA；
Fig. 3 is that FPGA of the present invention refreshes checking system structure schematic diagram；
Fig. 4 is the cut-away view of each shift register cell of the present invention；
Fig. 5 is the flow chart that the present invention refreshes verification method；
Fig. 6 is the waveform diagram that the present invention refreshes verification method；
Fig. 7 is shift register structure figure in the embodiment of the present invention；
Fig. 8 is checking internal system annexation figure in the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail:
It is illustrated in figure 3 FPGA of the present invention and refreshes checking system structure schematic diagram, FPGA refreshing checking system includes refresh module 101 as seen from the figure, it is refreshed SRAM type FPGA102, PROM104, peripheral signal module 103, its concrete annexation is as follows: refresh module 101 is connected respectively to configuration data port and the configurable clock generator port of FPGA, refresh module 101 connects clock end and the data terminal of PROM104 respectively, peripheral signal module 103 connects the user data input of FPGA respectively, user controls end and user clock end, in addition, FPGA directly exports internal signal to be tested by user's pin.
Wherein, refresh module 101 reads configuration bit stream from PROM104 and SRAM type FPGA102 is refreshed, peripheral signal module 103 provides clock signal to the shift register group of SRAM type FPGA102, enables signal and input signal, wherein clock signal drives shift register group displacement, input signal updates first of shift register group every time, enables signal and controls the displacement stopping of shift register.SRAM type FPGA102 can pass through the logic function that software programming realizes setting, and the function of PROM104 is the configuration bit stream of storage FPGA.Refresh module 101 in checking system to possess suspends the ability refreshed.Peripheral signal module 103 in checking system needs output clock and the user IO being signally attached to SRAM type FPGA102.SRAM type FPGA102 in checking system is refreshed device, is internally configured as look-up table shift register group, and shift register has clock end, data input pin, data output end etc., and the initial value of shift register has significant feature.
It is illustrated in figure 4 the cut-away view of each shift register cell of the present invention, the shift register group being made up of look-up table includes multiple shift register cell, as shown in Figure 4, each shift register cell includes memory element 202,2 and enters 1 the first Port Multiplier 201 and 1 gone out and enter 2 the second Port Multipliers 203 gone out, two Port Multipliers 201,203 control gating path by controlling end, select by configuration path read-write memory cell 202, or select by user path read-write memory cell 202.By such structure, look-up table shift register can at configuration read-write and any switching laws under user writable both of which.
Being illustrated in figure 5 the present invention and refresh the flow chart of verification method, the present invention utilizes the method that look-up table shift register carries out SRAM type FPGA refreshing compliance test result to comprise the steps:
(1), design fpga logic, SRAM type FPGA builds the shift register group being made up of look-up table, and initial value is set for shift register group；
(2) powering on of SRAM type FPGA, is completed, it is that SRAM type FPGA carries out code stream configuration by PROM, peripheral signal module drives shift register group to shift to shift register group input serial data, and the serial data of input is different from the initial value arranged described in step (1).
(3), when, after shift register group newly immigration value, when the save value in present shift register is different from the initial value of shift register, it is desirable to there is significant difference, peripheral signal module can stop to shift register group input serial data.In the present invention, the save value in preferred present shift register is different from the initial value of shift register, and changing value number account for initial save value number more than 50% time, stop to shift register group input serial data.
(4), refresh module by PROM storage code stream SRAM type FPGA is refreshed, after all storage values of shift register group are all refreshed, stop refresh；
(5), peripheral signal module again to shift register group input serial data drive shift register group shift, the save value in shift register group is all removed；
(6) whether the initial value arranged in the removal value, in contrast step (5) and step (1) is identical, if identical, judges Flushing success, if difference, judges to refresh unsuccessful.The present invention contrasts the removal value in step (5) by oscillograph, logic analyser or other digital signal acquiring devices whether identical with the initial value of the middle setting of step (1).
In above-mentioned steps (4), refresh step selects to be realized by configuration path read-write memory cell 202；Shift step in step (2), (5) selects by user path read-write memory cell 202.
If Fig. 6 is the waveform diagram that the present invention refreshes checking, refresh control signal is not when refreshing, if the displacement of shift register group enables control bit effectively (in figure 401), then the signal of shift register output end is the user input signal (in figure 404) after postponing some cycles, delay period number is the degree of depth of shift register, when refreshing effectively, the displacement of shift register enables control bit invalid (in figure 402), if Flushing success, then when suspending refreshing and displacement enable recovers effective (in figure 403), first the signal of shift register output end exports initial value (in figure 405), then the user input signal (in figure 406) after output delay some cycles, if refreshing unsuccessful, then output signal is not initial value.The displacement enabling control and user's shift register refreshed enables can not effectively simultaneously, and otherwise output end signal is nondeterministic statement.
Embodiment
As Fig. 7 by FPGA develop the bit wide that is made up of look-up table of software design one be 1, data depth be the shift register of 16, this shift register includes 1 bit clock input clk, 1 signal input part in, 1 high effective enable control end enable, 1 signal output part out, all input and output are all connected to user's pin of FPGA, and wherein shift_out is directly output to the exploration hole of witness plate.It is 16 ' b1010101010011001 that the shift register of this 16 bit depth arranges initial value.The connection of refresh module and FPGA configuration port is as described in Figure 8, refresh module outfan TDI_F connects the TDI of FPGA, refresh module outfan TCK_F connects the TDO of TMS, the refresh module input TDO_F connection FPGA of TCK, the refresh module outfan TMS_F connection FPGA of FPGA.Connection such as Fig. 8 of refresh module and PROM, refresh module input Data_P connects the Data end of PROM, refresh module outfan Clk_P connects the Clk end of PROM, and refresh module outfan CE_P connects the CE end of PROM, and refresh module outfan OE_P connects the OE end of PROM.The input Pause of refresh module can select be pulled upward to high level or pull down to low level.Connection such as Fig. 8 of peripheral signal module and FPGA, the outfan shift_clk of peripheral signal module is connected to the input end of clock clk of the shift register of FPGA, the outfan shift_in of peripheral signal module is connected to the data input pin in, the outfan shift_enable of peripheral signal module of the shift register of FPGA and is connected to the high effectively Enable Pin enable of the shift register of FPGA.
The first step, enters in PROM by the look-up table shift register ASCII stream file ASCII programming of generation, re-powers, and loads code stream.Second step, the shift_clk (clock signal of shift register group) of peripheral signal module output exports 1MHz square wave clock, the shift_in (the input signal of shift register group) of peripheral signal module output exports high level, and the shift_enable (the enable signal of shift register group) of peripheral signal module output exports high level.The Pause signal ground of refresh module, stops refreshing.Out end at shift register detects that waveform first exports 16 ' b1010101010011001, and then output signal is 1 entirely.3rd step, shift_enable (the enable signal of the shift register group) output low level of peripheral signal module output, shift register group suspends displacement.The input Pause of refresh module is pulled upward to high level, starts and refreshes.4th step, the input Pause of refresh module pulls down to low level, after the save value of depositor to be shifted is all refreshed, suspends and refreshes.5th step, the shift_clk (clock signal of shift register group) of peripheral signal module output exports 1MHz square wave clock, the shift_in (the input signal of shift register group) of peripheral signal module output exports high level, the shift_enable (the enable signal of shift register group) of peripheral signal module output exports high level, recovers displacement.6th step, the out end of detection shift register, if detecting, waveform first exports 16 ' b1010101010011001, and then output signal is 1 entirely, then illustrate that refresh module function is correct, if detecting, waveform is 1 all the time entirely, then illustrate that refresh module function is incorrect.
The above; being only the detailed description of the invention that the present invention is best, but protection scope of the present invention is not limited thereto, any those familiar with the art is in the technical scope that the invention discloses; the change that can readily occur in or replacement, all should be encompassed within protection scope of the present invention.
The content not being described in detail in description of the present invention belongs to the known technology of professional and technical personnel in the field.
Claims (7)
1. utilize look-up table shift register to carry out the SRAM type FPGA method refreshing compliance test result, it is characterised in that:
(1), in SRAM type FPGA, build the shift register group being made up of look-up table, and initial value is set for shift register group；
(2), complete the configuration that powers on of SRAM type FPGA, drive shift register group to shift to shift register group input serial data；
(3), when, after shift register group newly immigration value, when the save value in present shift register is different from the initial value of shift register, stopping to shift register group input serial data；
(4), SRAM type FPGA is refreshed, until all storage values of shift register group are all refreshed；
(5), again to shift register group input serial data drive shift register group to shift, the save value in shift register group is all removed；
(6) whether the initial value arranged in the removal value, in contrast step (5) and step (1) is identical, if identical, judges Flushing success, if difference, judges to refresh unsuccessful.
2. utilize look-up table shift register to carry out the SRAM type FPGA method refreshing compliance test result, refresh checking system by FPGA to realize, described FPGA refreshes checking system and includes SRAM type FPGA to be refreshed, refresh module, PROM and peripheral signal module, wherein PROM is used for storing SRAM type FPGA code stream, and concrete methods of realizing is as follows:
(1), in SRAM type FPGA, build the shift register group being made up of look-up table, and initial value is set for shift register group；
(2), completing powering on of SRAM type FPGA, be that SRAM type FPGA carries out code stream configuration by PROM, peripheral signal module drives shift register group to shift to shift register group input serial data；
(3), when, after shift register group newly immigration value, when the save value in present shift register is different from the initial value of shift register, peripheral signal module can stop to shift register group input serial data；
(4), refresh module SRAM type FPGA is refreshed, until when all storage values of shift register group are all refreshed；
(5), peripheral signal module again to shift register group input serial data drive shift register group shift, the save value in shift register group is all removed；
(6) whether the initial value arranged in the removal value, in contrast step (5) and step (1) is identical, if identical, judges Flushing success, if difference, judges to refresh unsuccessful.
3. the method utilizing look-up table shift register to carry out SRAM type FPGA refreshing compliance test result according to claim 1 and 2, it is characterized in that: the described shift register group being made up of look-up table includes multiple shift register cell, each shift register cell includes memory element (202), 2 enter 1 the first Port Multiplier (201) and 1 gone out enters 2 the second Port Multipliers (203) gone out, two Port Multipliers (201, 203) by controlling end control gating path, select by configuration path read-write memory cell (202), or select by user path read-write memory cell (202).
4. the method utilizing look-up table shift register to carry out SRAM type FPGA refreshing compliance test result according to claim 3, it is characterised in that: in described step (4), refresh step selects to be realized by configuration path read-write memory cell (202)；Shift step in described step (2), (5) selects by user path read-write memory cell (202).
5. the method utilizing look-up table shift register to carry out SRAM type FPGA refreshing compliance test result according to claim 1 and 2, it is characterized in that: in described step (3), when save value in present shift register is different from the initial value of shift register, and changing value account for initial save value more than 50% time, stop to shift register group input serial data.
6. the method utilizing look-up table shift register to carry out SRAM type FPGA refreshing compliance test result according to claim 1 and 2, it is characterised in that: described step (4) is refreshed by the code stream of storage in PROM.
7. the method utilizing look-up table shift register to carry out SRAM type FPGA refreshing compliance test result according to claim 1 and 2, it is characterised in that: whether identical with the initial value of setting in step (1) by the removal value in oscillograph, logic analyser or digital signal acquiring device contrast step (5) in described step (6).
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| CN111949574A (en) * | 2020-06-30 | 2020-11-17 | 厦门汉印电子技术有限公司 | Bus bit number judging method, device, equipment and readable storage medium |
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