CN105740087A - Method for carrying out SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array) refreshing effect verification by lookup table shift register - Google Patents

Abstract

The present invention relates to the method that utilizes look-up table shift register to carry out SRAM type FPGA refreshing effect verification, comprises step (1), builds the shift register group that is made of look-up table in FPGA, and sets initial value for shift register group; 2), complete the power-on configuration of the FPGA, input serial data to the shift register group to drive the shift register group to shift; (3), when the saved value in the current shift register is different from the initial value of the shift register, Can stop inputting the serial data to the shift register group; (4), refresh the SRAM type FPGA until all stored values of the shift register group are refreshed; (5), input the serial data to the shift register group again to drive the shift The bit register group is shifted, and the saved values in the shift register group are all moved out; (6), judging whether the refresh is successful, the method of the present invention does not need to carry out an irradiation test, does not need to read back, and has low cost and simple operation , The characteristics of accurate judgment.

Description

Method for verifying refresh effect of SRAM FPGA by using lookup table shift register

technical field

The invention relates to a method for verifying the refresh effect of an SRAM FPGA by using a lookup table shift register, in particular using the characteristics of a lookup table shift register to judge whether the refresh is successful, and belongs to the technical field of integrated circuits.

Background technique

The basic structure of SRAM-type FPGA is shown in Figure 1. The main functional modules include: input and output modules (IOB) around the circle, two-column block memory (BlockRAM) on the edge, and internal programmable logic block array (CLB). In addition, there are interconnect resources that connect the various modules throughout the circuit. The above logic resources and interconnect resources are all controlled by the underlying SRAM configuration bits. A large number of SRAM configuration bits distributed throughout the FPGA circuit determine the specific functions of the FPGA circuit, and the bitstream set of these configuration bits is called a bitstream.

When the SRAM FPGA is applied in the space environment, space high-energy particles will penetrate the interior of the FPGA device and generate ionization on the path, which will cause instantaneous current interference on the circuit nodes and cause circuit errors. A typical 6-tube SRAM unit consists of two cross-connected inverters and two gating tubes for read and write control. Figure 2 shows the principle of single event flipping of the configuration memory of the SRAM FPGA. When high-energy particles hit the sensitive area of the SRAM unit (take the drain area of the reverse biased n-tube as an example), the collection of charges in the junction area generates a transient current pulse, causing the information stored in the unit to change from "1" to "0", the state has been reversed. This effect is the spatial single event flipping effect. The flipping of the configuration bit state may lead to serious functional failures, resulting in internal functional disorder, short circuit, open circuit, etc. Faults caused by this configuration bit flip are permanent and can only be removed by reloading the bitstream.

Refresh technology utilizes the readback and partial reconfiguration functions of SRAM-type FPGAs to repair configuration SRAM cells where single-event flipping occurs. Single event upsets occurring in configured SRAM can be corrected, thereby completely eliminating single event upset accumulation, without interrupting user logic compared to full reloading of the bitstream, thereby increasing the refresh rate. Refresh technology has been widely used as a supporting measure in space FPGA applications. Whether the refresh is effective is a more concerned issue in the application process. Since the refresh is to read and write the internal configuration bits of the FPGA, similar to background operations, it is difficult to judge whether the refresh is successful without an intuitive signal indication. In order to judge whether the refresh is successful, it is usually necessary to flip the SRAM bit through an irradiation test and then read it back. After comparing the read-back code stream with the initial code stream, it is possible to determine whether the refresh is successful. Due to the need for irradiation tests, this discrimination method has relatively high threshold conditions, and the operations of readback and code stream analysis are also very complicated.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned defect of prior art, provide a kind of method utilizing look-up table shift register to carry out SRAM type FPGA refreshing effect verification, this method utilizes the characteristic of FPGA internal look-up table shift register, forms a kind of can conveniently The method for judging whether the refreshing is successful or not does not require irradiation test or readback, and has the characteristics of low cost, simple operation and accurate judgment.

Above-mentioned purpose of the present invention is mainly achieved through the following technical solutions:

Utilize the look-up table shift register to carry out the method for SRAM type FPGA refreshing effect verification, it is characterized in that:

(1), construct the shift register group that is made of look-up table in SRAM type FPGA, and set initial value for shift register group;

(2), complete the power-on configuration of the SRAM type FPGA, and input the serial data to the shift register group to drive the shift register group to shift;

(3), when the shift register group is newly shifted into the value, when the saved value in the current shift register is different from the initial value of the shift register, the input serial data to the shift register group can be stopped;

(4), refresh the SRAM type FPGA, until all storage values of the shift register group are refreshed;

(5), input serial data to the shift register group again to drive the shift register group to shift, and all the stored values in the shift register group are shifted out;

(6), compare whether the removed value in step (5) is the same as the initial value set in step (1), if they are the same, it is judged that the refresh is successful, and if they are different, it is judged that the refresh is not successful.

Utilize the look-up table shift register to carry out the method for SRAM type FPGA refresh effect verification, realize by FPGA refresh verification system, described FPGA refresh verification system comprises SRAM type FPGA to be refreshed, refresh module, PROM and peripheral signal module, wherein PROM is used for Store the SRAM type FPGA code stream, the specific implementation method is as follows:

(1), construct the shift register group that is made of look-up table in SRAM type FPGA, and set initial value for shift register group;

(2), complete the power-on of the SRAM FPGA, configure the code stream for the SRAM FPGA through the PROM, and the peripheral signal module inputs serial data to the shift register group to drive the shift register group to shift;

(3), when the shift register group is newly shifted into the value, when the saved value in the current shift register is different from the initial value of the shift register, the peripheral signal module can stop inputting serial data to the shift register group;

(4), the refresh module refreshes the SRAM type FPGA until all stored values of the shift register group are refreshed;

(5), the peripheral signal module inputs the serial data to the shift register group again to drive the shift register group to shift, and all the stored values in the shift register group are moved out;

(6), compare whether the removed value in step (5) is the same as the initial value set in step (1), if they are the same, it is judged that the refresh is successful, and if they are different, it is judged that the refresh is not successful.

In the above-mentioned method for verifying the refresh effect of SRAM type FPGA by using a lookup table shift register, the shift register group composed of a lookup table includes a plurality of shift register units, and each shift register unit includes a storage unit, 2 into 1 out The first multiplexer and the second multiplexer with 1 input and 2 outputs, the two multiplexers control the gating path through the control terminal, choose to read and write the storage unit through the configuration path, or choose to read and write the storage unit through the user path.

In the above-mentioned method utilizing the look-up table shift register to carry out SRAM type FPGA refresh effect verification, the refresh step selection in the step (4) is realized by configuring the path read-write storage unit (202); in the steps (2), (5) The shift step of selects the read/write memory cell through the user path (202).

In the above-mentioned method for verifying the refresh effect of SRAM type FPGA by using a lookup table shift register, in step (3), when the saved value in the current shift register is different from the initial value of the shift register, and the changed value accounts for the initial saved value When more than 50% of the value, stop inputting serial data to the shift register group.

In the method for verifying the refresh effect of the SRAM FPGA by using the look-up table shift register above, in step (4), refresh is performed through the code stream stored in the PROM.

In the above-mentioned method for utilizing the look-up table shift register to carry out SRAM type FPGA refresh effect verification, in step (6), by oscilloscope, logic analyzer or digital signal acquisition device comparison step (5) in the value shifted out and in step (1) Whether the initial value of the setting is the same.

Compared with the prior art, the present invention has the following beneficial effects:

(1), the prior art needs to pass the irradiation test, if it does not have the irradiation test conditions, it cannot be carried out. The present invention enables the judgment of whether the refresh is successful or not to be carried out in a normal laboratory environment, and only needs an ordinary verification board , the cost is significantly reduced.

(2) The prior art needs to read back the current code stream and compare it with the original code stream. The FPGA readback operation is very complicated, including a series of command words such as synchronization, desynchronization, frame length setting, and starting address setting. When comparing the readback code stream with the original code stream, it is necessary to consider the interference of irrelevant bits. The existing readback comparison The technical operation is very complicated; the present invention only needs to design a register link through user logic, and control refresh and register shift through a small number of signals during operation, and the operation method is greatly simplified compared with the prior art.

(3), the method of the present invention only needs to be carried out in a laboratory environment, and does not need to pass an irradiation test, which is lower than the threshold of the prior art, and the method of the present invention has a clear and definite judgment basis, and the judgment method is accurate.

(4), the method of the present invention is applicable to any FPGA model and any refreshing method, has wide application range, strong versatility, and has stronger practicability.

Description of drawings

Fig. 1 is the architecture diagram of SRAM type FPGA;

Fig. 2 is the schematic diagram of single event flipping of configuration memory of SRAM type FPGA;

Fig. 3 is the structural representation of FPGA refresh verification system of the present invention;

Fig. 4 is the internal structural diagram of each shift register unit of the present invention;

Fig. 5 is a flow chart of the refresh verification method of the present invention;

FIG. 6 is a schematic diagram of waveforms of the refresh verification method of the present invention;

FIG. 7 is a structural diagram of a shift register in an embodiment of the present invention;

Fig. 8 is a diagram of the internal connections of the verification system in the embodiment of the present invention.

detailed description

Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

As shown in Figure 3, it is a schematic structural diagram of the FPGA refresh verification system of the present invention. As can be seen from the figure, the FPGA refresh verification system includes a refresh module 101, a refreshed SRAM type FPGA102, a PROM 104, and a peripheral signal module 103, and its specific connection relationship is as follows: the refresh modules 101 are respectively Connect to the configuration data port and the configuration clock port of the FPGA, the refresh module 101 is connected to the clock terminal and the data terminal of the PROM104 respectively, and the peripheral signal module 103 is respectively connected to the user data input terminal, the user control terminal and the user clock terminal of the FPGA. In addition, the FPGA passes through The user pin directly outputs the internal signal to be tested.

Among them, the refresh module 101 reads the configuration code stream from the PROM104 to refresh the SRAM FPGA102, and the peripheral signal module 103 provides clock signals, enable signals and input signals to the shift register group of the SRAM FPGA102, wherein the clock signal drives the shift register Group shifting, the input signal updates the first bit of the shift register group each time, and the enable signal controls the shifting of the shift register to stop. The SRAM type FPGA 102 can realize the set logic function through software programming, and the function of the PROM 104 is to store the configuration code stream of the FPGA. The refresh module 101 in the verification system should have the ability to suspend refresh. The peripheral signal module 103 in the verification system needs to connect the output clock and signal to the user IO of the SRAM type FPGA 102 . The SRAM-type FPGA102 in the verification system is a device to be refreshed, and its internal configuration is a look-up table shift register group. The shift register has clock terminals, data input terminals, data output terminals, etc. The initial value of the shift register has significant characteristics.

As shown in Figure 4, it is the internal structure diagram of each shift register unit of the present invention, the shift register group formed by the look-up table includes a plurality of shift register units, as shown in Figure 4, each shift register unit includes storage Unit 202, the first multiplexer 201 with 2 inputs and 1 output, and the second multiplexer 203 with 1 input and 2 outputs. The two multiplexers 201 and 203 control the gating path through the control terminal, and choose to read and write storage through the configuration path. unit 202, or choose to read and write storage unit 202 through the user path. Through such a structure, the look-up table shift register can be switched arbitrarily in two modes of configuration read-write and user read-write.

As shown in Figure 5, it is the flow chart of the refresh verification method of the present invention, the present invention utilizes the look-up table shift register to carry out the method for SRAM type FPGA refresh effect verification and comprises the steps:

(1), design FPGA logic, build the shift register group that is made of look-up table in SRAM type FPGA, and set initial value for shift register group;

(2) Complete the power-on of the SRAM-type FPGA, and configure the code stream for the SRAM-type FPGA through the PROM. The peripheral signal module inputs serial data to the shift register group to drive the shift register group to shift. The input serial data and The initial values of the settings described in step (1) are different.

(3) When the shift register group has newly shifted in the value, when the saved value in the current shift register is different from the initial value of the shift register, preferably there is a significant difference, the peripheral signal module can stop inputting the string to the shift register group row data. In the present invention, it is preferred that when the saved value in the current shift register is different from the initial value of the shift register, and the number of changed values accounts for more than 50% of the number of initial saved values, the input of serial data to the shift register group is stopped.

(4), the refresh module refreshes the SRAM type FPGA by the code stream stored in the PROM, and stops refreshing when all stored values of the shift register group are refreshed;

(5), the peripheral signal module inputs the serial data to the shift register group again to drive the shift register group to shift, and all the stored values in the shift register group are moved out;

(6), compare whether the removed value in step (5) is the same as the initial value set in step (1), if they are completely the same, it is judged that the refresh is successful, and if they are different, it is judged that the refresh is not successful. In the present invention, compare whether the shifted-out value in step (5) is the same as the initial value set in step (1) by an oscilloscope, a logic analyzer or other digital signal acquisition devices.

The selection of the refresh step in the above step (4) is realized by configuring the path to read and write the storage unit 202;

Figure 6 is a waveform schematic diagram of the refresh verification of the present invention. When the refresh control signal is not refreshed, if the shift enable control bit of the shift register group is valid (401 in the figure), the signal at the output end of the shift register is delayed for a certain period. After the user input signal (404 in the figure), the number of delay cycles is the depth of the shift register. When the refresh is valid, the shift enable control bit of the shift register is invalid (402 in the figure). If the refresh is successful, then when the refresh is suspended And when the shift enable is restored to be valid (403 in the figure), the signal at the output end of the shift register first outputs the initial value (405 in the figure), and then outputs the user input signal (406 in the figure) after a certain period of delay. , the output signal is not the initial value. The refresh enable control and the shift enable of the user shift register cannot be valid at the same time, otherwise the output signal is in an indeterminate state.

Example

As shown in Figure 7, design a shift register consisting of a lookup table with a bit width of 1 bit and a data depth of 16 bits through the FPGA development software. The shift register includes a 1-bit clock input terminal clk, a 1-bit signal input terminal in, 1 The bit high effectively enables the control terminal enable and the 1-bit signal output terminal out. All input and output are connected to the user pins of the FPGA, and the shift_out is directly output to the detection hole of the verification board. The 16-bit deep shift register is set to an initial value of 16'b1010101010011001. The connection between the refresh module and the FPGA configuration port is as shown in Figure 8. The output terminal TDI_F of the refresh module is connected to the TDI of the FPGA, the output terminal TCK_F of the refresh module is connected to the TCK of the FPGA, the output terminal TMS_F of the refresh module is connected to the TMS of the FPGA, and the input terminal TDO_F of the refresh module is connected to TDOs of FPGAs. The connection between the refresh module and the PROM is shown in Figure 8. The refresh module input Data_P is connected to the Data port of the PROM, the refresh module output Clk_P is connected to the Clk port of the PROM, the refresh module output CE_P is connected to the PROM CE port, and the refresh module output OE_P is connected to the PROM the OE side. The Pause input terminal of the refresh module can be selected to be pulled up to high level or pulled down to low level. The connection between the peripheral signal module and the FPGA is shown in Figure 8. The output terminal shift_clk of the peripheral signal module is connected to the clock input terminal clk of the shift register of the FPGA, and the output terminal shift_in of the peripheral signal module is connected to the data input terminal in of the shift register of the FPGA. , the output terminal shift_enable of the peripheral signal module is connected to the active high enable terminal enable of the FPGA shift register.

The first step is to burn the generated lookup table shift register code stream file into the PROM, power on again, and load the code stream. In the second step, the shift_clk (clock signal of the shift register group) output by the peripheral signal module outputs a 1MHz square wave clock, the shift_in (input signal of the shift register group) output by the peripheral signal module outputs a high level, and the output of the peripheral signal module shift_enable (the enable signal of the shift register group) outputs a high level. The Pause signal of the refresh module is grounded to stop the refresh. The waveform detected at the out end of the shift register first outputs 16’b1010101010011001, and then the output signals are all 1. In the third step, the shift_enable (enable signal of the shift register group) output by the peripheral signal module outputs a low level, and the shift register group stops shifting. The input terminal Pause of the refresh module is pulled up to a high level to start the refresh. In the fourth step, the input terminal Pause of the refresh module is pulled down to a low level, and after all the stored values of the shift register are refreshed, the refresh is paused. Step 5, the shift_clk (clock signal of the shift register group) output by the peripheral signal module outputs a 1MHz square wave clock, the shift_in (input signal of the shift register group) output by the peripheral signal module outputs a high level, and the output of the peripheral signal module shift_enable (the enable signal of the shift register group) outputs a high level to resume shifting. The sixth step is to detect the out terminal of the shift register. If the detected waveform first outputs 16'b1010101010011001, and then the output signal is all 1, it means that the function of the refresh module is correct. If the detected waveform is always all 1, it means that the function of the refresh module Incorrect.

The above description is only the best specific implementation mode of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of changes or modifications within the technical scope disclosed in the present invention. Replacement should be covered within the protection scope of the present invention.

The content that is not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art.

Claims (7)

1. utilize look-up table shift register to carry out the SRAM type FPGA method refreshing compliance test result, it is characterised in that:

(1), in SRAM type FPGA, build the shift register group being made up of look-up table, and initial value is set for shift register group；

(2), complete the configuration that powers on of SRAM type FPGA, drive shift register group to shift to shift register group input serial data；

(3), when, after shift register group newly immigration value, when the save value in present shift register is different from the initial value of shift register, stopping to shift register group input serial data；

(4), SRAM type FPGA is refreshed, until all storage values of shift register group are all refreshed；

(5), again to shift register group input serial data drive shift register group to shift, the save value in shift register group is all removed；

(6) whether the initial value arranged in the removal value, in contrast step (5) and step (1) is identical, if identical, judges Flushing success, if difference, judges to refresh unsuccessful.

2. utilize look-up table shift register to carry out the SRAM type FPGA method refreshing compliance test result, refresh checking system by FPGA to realize, described FPGA refreshes checking system and includes SRAM type FPGA to be refreshed, refresh module, PROM and peripheral signal module, wherein PROM is used for storing SRAM type FPGA code stream, and concrete methods of realizing is as follows:

(1), in SRAM type FPGA, build the shift register group being made up of look-up table, and initial value is set for shift register group；

(2), completing powering on of SRAM type FPGA, be that SRAM type FPGA carries out code stream configuration by PROM, peripheral signal module drives shift register group to shift to shift register group input serial data；

(3), when, after shift register group newly immigration value, when the save value in present shift register is different from the initial value of shift register, peripheral signal module can stop to shift register group input serial data；

(4), refresh module SRAM type FPGA is refreshed, until when all storage values of shift register group are all refreshed；

(5), peripheral signal module again to shift register group input serial data drive shift register group shift, the save value in shift register group is all removed；

(6) whether the initial value arranged in the removal value, in contrast step (5) and step (1) is identical, if identical, judges Flushing success, if difference, judges to refresh unsuccessful.

3. the method utilizing look-up table shift register to carry out SRAM type FPGA refreshing compliance test result according to claim 1 and 2, it is characterized in that: the described shift register group being made up of look-up table includes multiple shift register cell, each shift register cell includes memory element (202), 2 enter 1 the first Port Multiplier (201) and 1 gone out enters 2 the second Port Multipliers (203) gone out, two Port Multipliers (201, 203) by controlling end control gating path, select by configuration path read-write memory cell (202), or select by user path read-write memory cell (202).

4. the method utilizing look-up table shift register to carry out SRAM type FPGA refreshing compliance test result according to claim 3, it is characterised in that: in described step (4), refresh step selects to be realized by configuration path read-write memory cell (202)；Shift step in described step (2), (5) selects by user path read-write memory cell (202).

5. the method utilizing look-up table shift register to carry out SRAM type FPGA refreshing compliance test result according to claim 1 and 2, it is characterized in that: in described step (3), when save value in present shift register is different from the initial value of shift register, and changing value account for initial save value more than 50% time, stop to shift register group input serial data.

6. the method utilizing look-up table shift register to carry out SRAM type FPGA refreshing compliance test result according to claim 1 and 2, it is characterised in that: described step (4) is refreshed by the code stream of storage in PROM.

7. the method utilizing look-up table shift register to carry out SRAM type FPGA refreshing compliance test result according to claim 1 and 2, it is characterised in that: whether identical with the initial value of setting in step (1) by the removal value in oscillograph, logic analyser or digital signal acquiring device contrast step (5) in described step (6).