CN111031233A - Digital image processing frame rate control method and device - Google Patents
Digital image processing frame rate control method and device Download PDFInfo
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- CN111031233A CN111031233A CN201911110067.XA CN201911110067A CN111031233A CN 111031233 A CN111031233 A CN 111031233A CN 201911110067 A CN201911110067 A CN 201911110067A CN 111031233 A CN111031233 A CN 111031233A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/60—Control of cameras or camera modules
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
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Abstract
The invention discloses a digital image processing frame rate control method, a device, a terminal device and a readable storage medium, wherein the method comprises the following steps: updating the value of the software frame rate control register to a corresponding hardware frame rate control register according to preset software configuration; analyzing a frame header of the image data through an output protocol register of the camera; comparing corresponding bits of a shift register and the hardware frame rate control register, and discarding or reserving a current frame of the image data according to a comparison result; when the processing of one frame of image is finished, the counters at different positions are compared with the corresponding software state control register, and the state of the rate state register is updated according to the comparison result; and updating the hardware frame rate control register according to the state information of the frame rate state register. The invention can realize the automatic control of the image frame rate under the condition of not changing the setting of the camera.
Description
Technical Field
The present invention relates to the field of image processing technologies, and in particular, to a method and an apparatus for controlling a frame rate of digital image processing, a terminal device, and a readable storage medium.
Background
In the digital image processing system, the digital image processing unit processes the image data transmitted by the camera unit and finally uploads the processed image data to the memory or directly displays the processed image data. The camera unit is mostly located outside the digital image processing unit chip, and the digital image processing unit chip controls the camera through an off-chip bus. In practical operation, the digital image processing unit chip may need to reduce the frame rate of the input image due to system performance, and it is a tedious process to control the camera frame rate through the commonly used off-chip bus.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide a method, an apparatus, a terminal device and a readable storage medium for controlling a digital image processing frame rate, which can realize automatic control of an image frame rate without changing a camera setting.
In order to solve the above technical problem, an embodiment of the present invention provides a method for controlling a frame rate of digital image processing, including:
updating the value of the software frame rate control register to a corresponding hardware frame rate control register according to preset software configuration;
analyzing a frame header of the image data through an output protocol register of the camera;
comparing corresponding bits of a shift register and the hardware frame rate control register, and discarding or reserving a current frame of the image data according to a comparison result;
when the processing of one frame of image is finished, the counters at different positions are compared with the corresponding software state control register, and the state of the rate state register is updated according to the comparison result;
and updating the hardware frame rate control register according to the state information of the frame rate state register.
Further, the comparing the shift register with the corresponding bit of the hardware frame rate control register, and discarding or retaining the current frame of the image data according to the comparison result specifically includes:
judging whether the corresponding bits of the shift register and the hardware frame rate control register are the same or not;
if so, reserving the current frame of the image data;
and if not, discarding the current frame of the image data.
Further, the updating the hardware frame rate control register according to the state information of the frame rate state register specifically includes:
judging whether hardware needs to be reconfigured according to the state information of the frame rate state register;
if so, updating the software configuration, and updating the hardware frame rate control register according to the updated software configuration;
and if not, updating the hardware frame rate control register according to the value of a preset weight register.
In order to solve the same technical problem, the present invention also provides a digital image processing frame rate control device, comprising:
the hardware initialization module is used for updating the value of the software frame rate control register to the corresponding hardware frame rate control register according to the preset software configuration;
the image analysis module is used for analyzing the frame header of the image data through an output protocol register of the camera;
the data frame screening module is used for comparing corresponding bits of the shift register and the hardware frame rate control register and discarding or reserving a current frame of the image data according to a comparison result;
the state updating module is used for comparing counters at different positions with corresponding software state control registers when processing of one frame of image is finished, and updating the state of the rate state register according to the comparison result;
and the frame rate control module is used for updating the hardware frame rate control register according to the state information of the frame rate state register.
Further, the data frame screening module is specifically configured to: judging whether the corresponding bits of the shift register and the hardware frame rate control register are the same or not;
if so, reserving the current frame of the image data;
and if not, discarding the current frame of the image data.
Further, the frame rate control module is specifically configured to: judging whether hardware needs to be reconfigured according to the state information of the frame rate state register;
if so, updating the software configuration, and updating the hardware frame rate control register according to the updated software configuration;
and if not, updating the hardware frame rate control register according to the value of a preset weight register.
In order to solve the same technical problem, the present invention further provides a digital image processing frame rate control terminal device, which includes a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, wherein the memory is coupled to the processor, and when the processor executes the computer program, any one of the digital image processing frame rate control methods is implemented.
In order to solve the same technical problem, the present invention further provides a computer-readable storage medium storing a computer program, wherein when the computer program runs, a device in which the computer-readable storage medium is located is controlled to execute any one of the digital image processing frame rate control methods.
Compared with the prior art, the invention has the following beneficial effects:
the embodiment of the invention provides a method, a device, equipment and a readable storage medium for controlling a digital image processing frame rate, wherein the method comprises the following steps: updating the value of the software frame rate control register to a corresponding hardware frame rate control register according to preset software configuration; analyzing a frame header of the image data through an output protocol register of the camera; comparing corresponding bits of a shift register and the hardware frame rate control register, and discarding or reserving a current frame of the image data according to a comparison result; when the processing of one frame of image is finished, the counters at different positions are compared with the corresponding software state control register, and the state of the rate state register is updated according to the comparison result; and updating the hardware frame rate control register according to the state information of the frame rate state register. The invention can realize the automatic control of the image frame rate under the condition of not changing the setting of the camera.
Drawings
FIG. 1 is a flowchart illustrating a frame rate control method for digital image processing according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a software processing flow of a frame rate control method for digital image processing according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a hardware processing flow of a frame rate control method for digital image processing according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a frame rate control apparatus for digital image processing according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, an embodiment of the present invention provides a method for controlling a frame rate of digital image processing, including:
s1, updating the value of the software frame rate control register to the corresponding hardware frame rate control register according to the preset software configuration;
s2, analyzing the frame header of the image data through an output protocol register of the camera;
s3, comparing the shift register with the corresponding bit of the hardware frame rate control register, and discarding or retaining the current frame of the image data according to the comparison result;
in the embodiment of the present invention, further, step S3 specifically includes:
judging whether the corresponding bits of the shift register and the hardware frame rate control register are the same or not;
if so, reserving the current frame of the image data;
and if not, discarding the current frame of the image data.
S4, when finishing the processing of a frame of image, comparing the counters at different positions with the corresponding software state control register, and updating the state of the rate state register according to the comparison result;
and S5, updating the hardware frame rate control register according to the state information of the frame rate state register.
In the embodiment of the present invention, further, step S5 specifically includes:
judging whether hardware needs to be reconfigured according to the state information of the frame rate state register;
if so, updating the software configuration, and updating the hardware frame rate control register according to the updated software configuration;
and if not, updating the hardware frame rate control register according to the value of a preset weight register.
It should be noted that, the embodiment of the present invention provides a method for controlling a frame rate of digital image processing, and as an example, the implementation process thereof is as follows:
referring to fig. 2, after initialization, the hardware configuration register is configured according to preset software;
the configured hardware registers include: an output protocol register, a software frame rate control register, a hardware frame rate control register, a software state control register and a weight register of the camera; wherein:
each value in the output protocol register of the camera represents a protocol of the image output data of the camera, wherein the protocol comprises various protocols of the image output data of the camera;
the software frame rate control register can be divided into N registers, and each register MNThe bit is used for judging which software frame rate control register value is updated to the hardware frame rate control register according to the frame rate state register and the weight register when each frame is ended or the hardware is started under the condition of non-software intervention;
the hardware frame rate control register is an actual register used for controlling the frame rate;
the software state control register can be divided into X registers, and each register YXThe bit is used for judging whether each position is in an idle state or not when the digital image processing system processes a frame of image;
the weight register is used for distributing weight coefficients of different positions of the system;
the frame rate state register records the idle state of each position when the digital image processing system processes a frame of image, wherein the idle state is X bits in total, and corresponds to different positions in the system as X of the software state control register.
It should be noted that, in the embodiment of the present invention, after enabling hardware by software, it may be selected whether software operation is required;
if the software operation is not needed, the software operation is ended;
if the software operation is needed, the interrupt control is opened, whether the configuration register needs to be updated or not is judged by reading the status register, and if the configuration register does not need to be updated, the interrupt obtaining step is continued; reconfiguring the registers later enables the hardware if necessary.
Referring to FIG. 3, after the software enables the hardware, the hardware starts to work;
the hardware updates the corresponding software frame rate control register to the hardware frame rate control register according to the software configuration, and meanwhile, counters at different positions in the system start to count when the system is idle; it is understood that the hardware herein refers to, by way of example, a digital image processing chip or a chip carrying an image interface, a codec, etc.
The hardware analyzes the frame header of the image data through an output protocol register of the camera;
the hardware internally uses a shift register and compares whether the shift register is the same with the corresponding bit of the hardware frame rate control register to judge whether the frame is discarded or not;
if the frame is discarded, the frame does not enter the subsequent unit of the image processing unit, and the step of re-calling the frame header for analyzing the image data is carried out;
if not, the current frame enters a subsequent unit of the system;
simultaneously, counters at different positions in the system start counting when the system is idle;
when the processing of one frame of image is finished, the counter is compared with the corresponding software state control register, and the state is updated to the frame rate state register;
the software can judge whether the register needs to be updated according to the state updating result of the frame rate state register of the hardware; for example, if the frame rate status register at a given location has no idle time or is idle for less than a predetermined threshold, reconfiguration may be selected.
If the register needs to be updated by software, returning to the software configuration register, and after the register is reconfigured, restarting the hardware;
if the register is not updated by the software, the frame rate state register preferentially judges which software frame rate control register value is updated to the hardware frame rate control register according to the value of the weight register preset by the software, thereby realizing the automatic control of the frame rate. It can be understood that in a specific application, according to an actual application scene and requirements, a designated register is preset, and then automatic control can be realized.
Compared with the prior art, the embodiment of the invention provides a method for automatically controlling the image frame rate under the condition of not changing the setting of a camera; the method can realize the optimization of software efficiency by completely automatically processing the software without software intervention in the running process, and the automatic processing mode of the hardware is preset by the software; the hardware processing mode preset by software provided by the invention can be used for setting specific parameters according to a specific system, so that the frame rate of an input image at an entrance is determined according to the running condition of the system; the invention also provides an interface for software intervention in the hardware operation process, so as to realize the flexibility of the system in different scenes.
It should be noted that the above method or flow embodiment is described as a series of acts or combinations for simplicity, but those skilled in the art should understand that the present invention is not limited by the described acts or sequences, as some steps may be performed in other sequences or simultaneously according to the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are exemplary embodiments and that no single embodiment is necessarily required by the inventive embodiments.
Referring to fig. 4, in order to solve the same technical problem, the present invention further provides a frame rate control apparatus for digital image processing, comprising:
the hardware initialization module 1 is used for updating the value of the software frame rate control register to the corresponding hardware frame rate control register according to the preset software configuration;
the image analysis module 2 is used for analyzing the frame header of the image data through an output protocol register of the camera;
the data frame screening module 3 is used for comparing corresponding bits of the shift register and the hardware frame rate control register and discarding or reserving a current frame of the image data according to a comparison result;
the state updating module 4 is used for comparing counters at different positions with corresponding software state control registers when processing of one frame of image is completed, and updating the state of the rate state register according to the comparison result;
and the frame rate control module 5 is configured to update the hardware frame rate control register according to the state information of the frame rate state register.
Further, the data frame screening module 3 is specifically configured to: judging whether the corresponding bits of the shift register and the hardware frame rate control register are the same or not;
if so, reserving the current frame of the image data;
and if not, discarding the current frame of the image data.
Further, the frame rate control module 5 is specifically configured to: judging whether hardware needs to be reconfigured according to the state information of the frame rate state register;
if so, updating the software configuration, and updating the hardware frame rate control register according to the updated software configuration;
and if not, updating the hardware frame rate control register according to the value of a preset weight register.
It is to be understood that the foregoing device item embodiments correspond to the method item embodiments of the present invention, and the frame rate control device for digital image processing according to the embodiment of the present invention can implement the method for controlling the frame rate of digital image processing according to any one of the method item embodiments of the present invention.
In order to solve the same technical problem, the present invention further provides a digital image processing frame rate control terminal device, which includes a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, wherein the memory is coupled to the processor, and when the processor executes the computer program, any one of the digital image processing frame rate control methods is implemented.
The digital image processing frame rate control terminal device can be a desktop computer, a notebook computer, a palm computer, a cloud server and other computing devices. The Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc., and the processor is a control center of the digital image processing frame rate control terminal device, and various interfaces and lines are used to connect various parts of the entire digital image processing frame rate control terminal device.
The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function, and the like; the storage data area may store data created according to the use of the mobile phone, and the like. In addition, the memory may include high speed random access memory, and may also include non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), at least one magnetic disk storage device, a Flash memory device, or other volatile solid state storage device.
In order to solve the same technical problem, the present invention further provides a computer-readable storage medium storing a computer program, wherein when the computer program runs, a device in which the computer-readable storage medium is located is controlled to execute any one of the digital image processing frame rate control methods.
The computer program may be stored in a computer readable storage medium, which when executed by a processor, may implement the steps of the various method embodiments described above. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain content that is subject to appropriate increase or decrease as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media does not include electrical carrier signals and telecommunications signals as is required by legislation and patent practice.
It should be noted that the above-described device embodiments are merely illustrative, where the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. In addition, in the drawings of the embodiment of the apparatus provided by the present invention, the connection relationship between the modules indicates that there is a communication connection between them, and may be specifically implemented as one or more communication buses or signal lines. One of ordinary skill in the art can understand and implement it without inventive effort.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.
Claims (8)
1. A method for controlling a frame rate in digital image processing, comprising:
updating the value of the software frame rate control register to a corresponding hardware frame rate control register according to preset software configuration;
analyzing a frame header of the image data through an output protocol register of the camera;
comparing corresponding bits of a shift register and the hardware frame rate control register, and discarding or reserving a current frame of the image data according to a comparison result;
when the processing of one frame of image is finished, the counters at different positions are compared with the corresponding software state control register, and the state of the rate state register is updated according to the comparison result;
and updating the hardware frame rate control register according to the state information of the frame rate state register.
2. The method as claimed in claim 1, wherein the comparing the corresponding bits of the shift register and the hardware frame rate control register, and discarding or retaining the current frame of the image data according to the comparing result, specifically:
judging whether the corresponding bits of the shift register and the hardware frame rate control register are the same or not;
if so, reserving the current frame of the image data;
and if not, discarding the current frame of the image data.
3. The method as claimed in claim 1, wherein the step of updating the hardware frame rate control register according to the status information of the frame rate status register comprises:
judging whether hardware needs to be reconfigured according to the state information of the frame rate state register;
if so, updating the software configuration, and updating the hardware frame rate control register according to the updated software configuration;
and if not, updating the hardware frame rate control register according to the value of a preset weight register.
4. A digital image processing frame rate control apparatus, comprising:
the hardware initialization module is used for updating the value of the software frame rate control register to the corresponding hardware frame rate control register according to the preset software configuration;
the image analysis module is used for analyzing the frame header of the image data through an output protocol register of the camera;
the data frame screening module is used for comparing corresponding bits of the shift register and the hardware frame rate control register and discarding or reserving a current frame of the image data according to a comparison result;
the state updating module is used for comparing counters at different positions with corresponding software state control registers when processing of one frame of image is finished, and updating the state of the rate state register according to the comparison result;
and the frame rate control module is used for updating the hardware frame rate control register according to the state information of the frame rate state register.
5. The apparatus according to claim 4, wherein the data frame filtering module is specifically configured to: judging whether the corresponding bits of the shift register and the hardware frame rate control register are the same or not;
if so, reserving the current frame of the image data;
and if not, discarding the current frame of the image data.
6. The apparatus as claimed in claim 4, wherein the frame rate control module is specifically configured to: judging whether hardware needs to be reconfigured according to the state information of the frame rate state register;
if so, updating the software configuration, and updating the hardware frame rate control register according to the updated software configuration;
and if not, updating the hardware frame rate control register according to the value of a preset weight register.
7. A terminal device for controlling frame rate in digital image processing, comprising a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, wherein the memory is coupled to the processor, and the processor executes the computer program to implement the frame rate control method according to any one of claims 1 to 3.
8. A computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and wherein when the computer program runs, the computer-readable storage medium controls an apparatus to execute the method according to any one of claims 1 to 3.
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