CN1277199C - Method and apparatus for accelerating processor to read and write scratch memory - Google Patents
Method and apparatus for accelerating processor to read and write scratch memory Download PDFInfo
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- CN1277199C CN1277199C CN 02152633 CN02152633A CN1277199C CN 1277199 C CN1277199 C CN 1277199C CN 02152633 CN02152633 CN 02152633 CN 02152633 A CN02152633 A CN 02152633A CN 1277199 C CN1277199 C CN 1277199C
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Abstract
The present invention relates to a method for accelerating a processor to read/write a temporary storage device and a device thereof. The present invention is characterized in that the processor is externally connected with an extended memory, and the address of the temporary storage device arranged inside the extended memory is mapped to the idle address of a special function register (SFR) arranged inside the processor in a memory mapping mode; a mark is used to switch the processor to be in an online simulation mode or a normal operation mode; when the processor is in the online simulation mode, the processor still uses external data transfer instructions to read/write the external temporary storage device; if the processor is switched to be in the normal operation mode, the processor uses internal data transfer instructions to read/write the external temporary storage device. The mode of the present invention can solve the problems of consumption of human power and material resources existing in a built-in online simulation mode and reduced reading/writing speed existing in an external connection online simulation mode.
Description
(1) technical field
The present invention relates to a kind of method and device of processor read, relate in particular to a kind of method and device that utilizes memory mapped (MEMORY MAPPING) mode OverDrive Processor ODP read.
(2) background technology
In the single-chip of 8051 series, specific function working storage (SFR) is being played the part of very important role, its be one 128 byte (Bytes) but the memory areas of first level address.Its first level address is 80H ~ FFH, is the working storage that is used for depositing peripheral device control, state and data, and functions such as every use is interrupted, series connection port, timing/counter all must be gone ahead of the rest and be set in each relevant control working storage of SFR.
Yet, in case used the working storage among the SFR, debugging (debug) and other demands in order to develop, often must be in processor at the built-in in-circuit emulator of aforementioned specific function (ICE, In-CircuitEmulator), to debug.But the making of ICE needs the support of many manpowers such as S/W, F/W, H/W and material resources, so must pay very considerable resource.And be to reduce resource cost, be to take outside expansion to connect (being the MOVX zone) mode to realize, it mainly is ICE pattern (MODE) function of utilizing 8051 processors to support, forbid (DISABLE) its inner working storage, the pins such as PORT 0, PORT2, ALE, RESET, CLK that make processor again connect outside ICE in mode one to one, with the usefulness as debug.Utilize not only function-stable of this mode, and because of need not self-built ICE, so can significantly reduce expending of human and material resources.
But aforementioned external ICE mode is obviously not good in the performance of read, mainly common of the internal data move instruction of using because of processor reading and writing internal working storage (MOV) needs a Machine cycle (MACHINECYCLE), read-write to expand the external data transmission instruction (MOVX) that connects the storer use and then all needs two Machine cycles.And the MOVX data movement instruction is carried out, and after being finished by totalizer (ACC) computing, write-back (WRITE BACK) is to original working storage again, more influences its read or write speed between back and forth.In addition, when reading and writing other working storages, also necessary predecessor address (at Ri or DPTR), thus its extreme difference in the performance of read or write speed, and required program capacity is also bigger.Also can't satisfy simultaneously many occasions of having relatively high expectations for read-write.
From the above, SFR in the user utilizes processor must utilize ICE to carry out debug on various specific functions, but built-in ICE consumes resources is very big, external ICE then read-write efficiency performs poor, the awkward puzzlement that causes relevant at present serial processor to develop.
(3) summary of the invention
Therefore, fundamental purpose of the present invention promptly is to provide a kind of being easy to that processor is carried out debug and taken into account the method that read-write shows.
The present invention's time purpose is at the device that a kind of OverDrive Processor ODP read is provided.
For realizing aforementioned purpose, the major technique means of taking according to an aspect of the present invention be by the external extended storage of processor as working storage, the idle address of the working storage map addresses in the extended storage being established specific function working storage (SFR) in processor again in memory mapped (MEMORY MAPPING) mode; Utilize a sign handoff processor to be ICE pattern or normal manipulation mode again, and make processor: under the ICE pattern, connect working storage with outside expansion of MOVX data movement instruction read-write; Under normal manipulation mode,, the outside expansion is connect working storage be modeled as inner working storage, so can read and write by the MOV data movement instruction because of the memory mapped relation.
In previous designs, owing to be to set up the function working storage with external memorizer, so can make things convenient for external ICE to carry out debug, again under normal manipulation mode, then the outside is expanded and connect working storage simulated interior working storage, so can utilize the short MOV data movement instruction of Machine cycle to read and write data,, and then build the double-barreled question of ICE inside and outside solving with its read-write motion of effective acceleration.
Said external expand connect working storage be can bit address (byte address) and block address (block address) map to the idle address of doing scattered distribution in the specific function working storage respectively.
Aforementioned ICE pattern and normal manipulation mode are to be carried out by one group of macrodata move instruction respectively, and each organizes the macrodata move instruction is to be stored in respectively in other document, avoids misreading so that directly carry out corresponding document behind the switch mode.
A kind of device of OverDrive Processor ODP read is provided according to a further aspect of the invention, and it includes: processor has external data at least and transmits instruction I/O (I/O) port and internal data move instruction I/O (I/O) port; Storer is the external memory storage as processor, establishes a plurality of function working storages on it; First switch unit is to be connected between processor and the storer, delivers to instructing or the internal data move instruction for external data transmits of storer in order to switch selection processor;
Second switch unit is in order to switch external data transmission instruction I/O port or the internal data move instruction I/O port that selection memory data pin is the connection processing device; Decoding unit has two input ends, and it transmits instruction I/O port with the external data of processor respectively and internal data move instruction I/O port is connected, and utilizing a sign is to send external data to transmit instruction or internal data move instruction with decision processor; Also having output terminal, is to be connected with the selection pin of aforementioned first, second switch unit respectively, switches transmission instruction of output external data or internal data move instruction in order to control first, second switch unit according to aforementioned judged result; Latch unit is located between first switch unit and storer, in order to specify the address of data in the read-write memory.
For clearer understanding purpose of the present invention, characteristics and advantage, preferred embodiment of the present invention is elaborated below in conjunction with accompanying drawing.
(4) description of drawings
Fig. 1 is specific function working storage (SFR) arrangement plan;
Fig. 2 is the equivalent configuration diagram of the present invention under the ICE pattern;
Fig. 3 is the equivalent configuration diagram of the present invention under normal manipulation mode;
Fig. 4 is that expansion of the present invention connects the working storage arrangement plan;
Fig. 5 is a circuit block diagram of the present invention;
Fig. 6 is the calcspar of the present invention's first switch unit.
(5) embodiment
At first the present invention makes the external extended storage of processor connect working storage set up to expand, and in present embodiment, is to be example with 8051 processors.In memory mapped (MEMORY MAPPING) mode expansion is connect the working storage map addresses is established specific function working storage (SFR) in processor idle address again.
And SFR is one 128 byte (Bytes) (but the memory areas of direct addressing (seeing also shown in Figure 1) of 80H ~ FFH), except existing many groups working storage own, many idle addresses are still arranged, so the present invention connects expansion the map addresses of working storage to the idle address of SFR, so that under normal manipulation mode, expansion is connect working storage be modeled as inner working storage, and then can the internal data move instruction read and write to expand and connect working storage, mode compared to read and write outside working storage with outside data movement instruction can significantly promote its read or write speed.
In addition, the present invention utilizes one to indicate with the handoff processor to be ICE pattern or normal manipulation mode:
When processor switches to the ICE pattern, processor is looked and is expanded that to connect working storage be outside working storage, its framework is as shown in Figure 2, reads and writes so make processor connect working storage with outside data movement instruction (MOVX) to this expansion, can make things convenient for outside ICE that processor is carried out debug under this state.
When processor switches to normal manipulation mode, processor is looked because of memory mapped relation and is expanded that to connect working storage be inner working storage, its equivalent framework is as shown in Figure 3, so processor is read and write with internal data move instruction (MOV) data movement instruction, because the Machine cycle of internal data move instruction transmits instruction less than external data, so can improve the speed of processor read.
When reality is carried out, aforementioned ICE pattern and normal manipulation mode are to carry out by one group of macrodata move instruction respectively, each is organized the macrodata move instruction and is stored in respectively in other document, so that directly carry out corresponding document behind the switch mode, mat can be avoided misreading situation and take place.
Still see also shown in Figure 1, because being non-systematicness, the working storage address among the SFR distributes, being block (BLOCK) in its idle address segment set distributes, the idle address of part is that unit does scattered distribution with byte (byte) or position (bit), at this kind distribution character, can plan that it is block form (blocktype), byte form (byte type) or position form (bit type) (as shown in Figure 4) that expansion connects the working storage address, on the idle address that maps to corresponding form among the SFR respectively.
From the above, the present invention sets up the function working storage with external memorizer, carry out debug with convenient external ICE, again under normal manipulation mode, because of connecing working storage, the outside expansion is modeled as inner working storage by the memory mapped mode, thus can use the short internal data move instruction read of Machine cycle, with its read or write speed of effective lifting, as for the device that can carry out aforementioned functional as shown in Figure 5, it includes:
Decoding unit 50, have two input ends, it transmits instruction I/O port with the external data of processor 10 respectively and internal data move instruction I/O port is connected, in order to decision processor 10 is to send external data to transmit instruction or internal data move instruction, its output terminal is to be connected with the selection pin of aforementioned first, second switch unit 30,40 respectively, switches transmission instruction of output external data or internal data move instruction in order to control first, second switch unit 30,40 according to aforementioned judged result;
Aforesaid first, second switch unit 30,40 can be made of traffic pilot respectively, wherein first switch unit 30 is made up of as shown in Figure 6 many groups traffic pilot 31～34, to select as the switching of processor 10 each state pin outputs respectively, as traffic pilot 31 is the CS pin output of selecting to be transmitted by inside or external data instruction in order to switch, traffic pilot 32 is the RD pin output of selecting to be transmitted by inside or external data instruction in order to switch, traffic pilot 33 is the WR pin output of selecting to be transmitted by inside or external data instruction in order to switching, 34 DI (7:0) pin outputs of selecting to be transmitted by inside or external data instruction in order to switching of traffic pilot.It is to be controlled by decoding unit 50 by its pin S that the state of each traffic pilot 31～34 switches.
Utilize the previous constructions can be in order to switch ICE pattern and normal manipulation mode, in order to carry out debug and operate as normal respectively:
Under the ICE pattern, processor 10 transmits instruction I/O port by external data and sends external data transmission instruction, except that delivering to first switch unit 30, also deliver to decoding unit 50 decodings simultaneously, to switch first, second switch unit 30,40 to external data transmission instruction mode, this moment, the external data transmission instruction (MOVX) of processor 10 was promptly delivered to storer 20 via first switch unit 30, and the address of cooperation latch unit 60, the data of read-write memory 20 particular addresss are sent data through second switch unit 40 by storer 20 again, external data transmits instruction I/O port and sends processor 10 back to.
And under normal manipulation mode, processor 10 is sent the internal data move instruction by internal data move instruction I/O port, except that delivering to first switch unit 30, also deliver to decoding unit 50 decodings simultaneously, to switch first, second switch unit 30,40 to internal data move instruction pattern, this moment, the internal data move instruction (MOV) of processor 10 was promptly delivered to storer 20 via first switch unit 30, and the address of cooperation latch unit 60, the data of read-write memory 20 particular addresss are sent data through second switch unit 40 by storer 20 again, internal data move instruction I/O port is sent processor 10 back to.
As shown in the above description, the design that utilizes the present invention to propose, processor can be divided into ICE pattern and normal manipulation mode, wherein the ICE pattern is to use when debug, under this pattern, processor can connect outside ICE, and the external data that processor is sent transmits instruction and can be external ICE institute receiving and analyzing, and promptly processor need not self-built ICE can be reached other functions that debug and ICE provide.
Treat under normal manipulation mode, expand the SFR that the address that connects working storage maps to processor respectively, and be modeled to inner working storage, so processor promptly can internal data move instruction read-write expansion connect working storage, because the Machine cycle of internal data move instruction significantly transmits instruction less than external data, can significantly promote the speed of processor read by this.And, because aforesaid design can effectively solve the awkward puzzlement that built-in ICE and external ICE divide the tool relative merits.
Claims (5)
1. the method for an OverDrive Processor ODP read is characterized in that, comprises the following steps:
Make the processor external memorizer connect working storage as expansion;
In the memory mapped mode expansion is connect the working storage map addresses is established the specific function working storage in processor idle address;
Utilize a sign that processor is switched between first pattern and second pattern, and make processor:
Under first pattern, read and write described expansion with outside data movement instruction and connect working storage;
Under second pattern, because of memory mapped concerns with internal data move instruction read.
2. the method for OverDrive Processor ODP read as claimed in claim 1, it is characterized in that, it is to form with block form, byte form or position form respectively that this expansion connects working storage, and maps to the idle address that is the corresponding form distribution in the specific function working storage respectively.
3. the method for OverDrive Processor ODP read as claimed in claim 1 is characterized in that, this first pattern and second pattern are to be carried out by one group of macrodata move instruction respectively, and each organizes the macrodata move instruction is to be stored in respectively in other document.
4. the device of an OverDrive Processor ODP read is characterized in that, includes:
Processor has an external data at least and transmits an instruction input/output end port and an internal data move instruction input/output end port;
Storer is the external memory storage as processor, establishes a plurality of function working storages on it;
First switch unit is to be connected between described processor and the described storer, selects described processor to deliver to instructing or the internal data move instruction for external data transmits of described storer in order to switch;
Second switch unit between described storer and described processor, selects described storer to deliver to instructing or the internal data move instruction for external data transmits of described processor in order to switch;
Decoding unit with the external data transmission instruction input/output end port and the electric connection of internal data move instruction input/output end port of processor, is to send external data to transmit instruction or internal data move instruction in order to decision processor; Have an output terminal,, utilize a sign to control the switching of this switch unit with the selection pin electric connection of aforementioned switch unit.
Latch unit is located between first switch unit and storer, in order to specify the address of data in the described storer of read-write.
5. device as claimed in claim 4 is characterized in that, this switch unit at least one traffic pilot of serving as reasons constitutes, to select as the switching of each state pin output of processor respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02152633 CN1277199C (en) | 2002-11-28 | 2002-11-28 | Method and apparatus for accelerating processor to read and write scratch memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02152633 CN1277199C (en) | 2002-11-28 | 2002-11-28 | Method and apparatus for accelerating processor to read and write scratch memory |
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| CN1504885A CN1504885A (en) | 2004-06-16 |
| CN1277199C true CN1277199C (en) | 2006-09-27 |
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| CN 02152633 Expired - Fee Related CN1277199C (en) | 2002-11-28 | 2002-11-28 | Method and apparatus for accelerating processor to read and write scratch memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP4783567B2 (en) * | 2004-12-21 | 2011-09-28 | Ｏｋｉセミコンダクタ株式会社 | Semiconductor device |
| CN100395816C (en) * | 2005-01-06 | 2008-06-18 | 鸿富锦精密工业（深圳）有限公司 | Code sharing system of liquid crystal display microprocessor |
| TWI743611B (en) * | 2019-12-04 | 2021-10-21 | 新唐科技股份有限公司 | Processing device and data access method thereof |
| CN113282240A (en) * | 2021-05-24 | 2021-08-20 | 深圳市盈和致远科技有限公司 | Storage space data read-write method, equipment, storage medium and program product |
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Granted publication date: 20060927 Termination date: 20091228 |