CN112363959A - Data addressing method, storage device, chip and data storage system - Google Patents
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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Abstract
A data addressing method, a storage device, a chip and a data storage system are provided, wherein the data addressing method comprises the following steps: and configuring the mapping relation between a first base address register and a memory space, and transferring the data received by the first base address register to the memory space which has the mapping relation with the first base address register. According to the technical scheme, the method has the following beneficial technical effects that on one hand, in the embodiment of the application, on the one hand, the software and hardware matching design of the method does not need the cpu inside the soc of the Pcie endpoint equipment to intervene, and only the upper computer is used for carrying out large-range soc internal addressing. On the other hand, the upper computer can configure the mapping address and the storage space size of the second base address register to the first base address register through the second base address register so as to achieve the purpose of sliding the window; and the two first base address registers can enable the upper computer to access the register space inside the Pcie endpoint equipment chip, so that the large-range soc internal addressing can be carried out between the upper computer and the Pcie endpoint equipment.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a data addressing method, a storage device, a chip, and a data storage system.
Background
Under a basic Pcie protocol, the upper computer addressing Pcie endpoint equipment only supports fixed base address register space addressing, although a GB-level space can be set in a base address register, due to the memory limitation of the upper computer host, the address range which can be reserved for the upper computer can only be in MB level, and therefore the upper computer addressing Pcie endpoint equipment can only address the MB level space generally.
For the condition that the Pcie endpoint equipment needs to be addressed in a large range by the upper computer, the Pcie endpoint equipment is generally addressed in a Direct Memory Access (DMA) mode, and the direct DMA mode is suitable for performing instruction interaction by using a small amount of base address register space.
However, DMA addressing typically requires an intervention of the cpu inside the endpoint device soc to execute firmware. Therefore, DMA addressing is only suitable for moving transfers between a host computer of large contiguous code and a Pcie endpoint device, which can be extremely time consuming when transferring short data. In addition, if the whole chip needs to be started through the pcie interface, if the DMA mode is used for addressing, the power-on scheme of the chip is very complicated and is not easy to implement.
Disclosure of Invention
Objects of the invention
The invention aims to provide a data addressing method, a storage device, a chip and a data storage system, which are suitable for the condition that a chip is powered on and started on a pcie endpoint device. The invention simplifies the complexity of power-on starting through the pcie endpoint device, does not need the intervention of a CPU, and can completely depend on the upper computer to operate all registers and memories in the endpoint device chip, so when the CPU in the chip has a problem, the upper computer can still be used for debugging the endpoint device soc and other operations.
(II) technical scheme
To solve the above problem, according to an aspect of the present invention, there is provided a data addressing method including: configuring a mapping relation between a first base address register and a memory space;
and unloading the data received by the first base address register to the memory space which has a mapping relation with the first base address register.
Further, the configuring the mapping relationship between the first base address register and the memory space includes: receiving configuration data, wherein the configuration data is the mapping relation between the first base address register and a storage space;
and unloading the configuration data to enable the configuration register corresponding to the first base address register to receive the configuration data so as to complete the configuration.
Further, the configuration data is a mapping relationship between a base address of the first base address register and a base address of the storage space.
According to a second aspect of the present invention, there is provided a data storage device comprising:
the configuration module is used for configuring the mapping relation between the first base address register and the memory space;
the first base address register is used for transferring the received data to the memory space which has a mapping relation with the first base address register.
Further, the configuration module includes:
the second base address register is used for receiving configuration data, wherein the configuration data is the mapping relation between the first base address register and a storage space, and the configuration data is stored in a dump way;
and the configuration register corresponding to the first base address register is used for receiving the configuration data to complete the configuration.
Further, the configuration data is a mapping relationship between a base address of the first base address register and a base address of the storage space.
Furthermore, the number of the first base address registers is at least two, one of the two first base address registers is an IO type base address register, and the other one is a mem type base address register.
According to a third aspect of the present invention, there is provided a chip comprising a data storage device as described in any one of the preceding claims and a memory space coupled to said first base address register;
the memory space is used to store the data that is transferred by the first base address register.
Furthermore, the number of the memory spaces is at least two, and one of the two memory spaces is used for storing block data, and the other memory space is used for storing IO data.
According to a fourth aspect of the present invention, there is provided a data storage system comprising: the upper computer and the chip;
the upper computer sends configuration data and data to be stored in sequence;
the chip configures the mapping relation between a first base address register and a memory space according to the received configuration data, and transfers the data received by the first base address register to the memory space having the mapping relation with the first base address register according to the received data to be stored.
(III) advantageous effects
The technical scheme of the invention has the following beneficial technical effects:
1. the software and hardware matching design of the invention achieves the purpose that the CPU inside the soc of Pcie endpoint equipment is not needed to intervene, and the upper computer is only used for addressing the inside of the soc in a large range;
2. and the upper computer can modify all configurations of the Pcie endpoint equipment through the second base address register. The modification comprises that the upper computer can modify the mapping address and the storage space size of the first base address register by configuring a second base address register so as to achieve the purpose of sliding the window;
3. the chip provided by the embodiment of the invention can be provided with two first base address registers, and the two first base address registers can enable an upper computer to access the register space in the Pdie endpoint equipment chip. One first base address register is set to be 4k in size and io type, and the other first base address register is set to be 1MB in size and mem type, so that large-range soc internal addressing is carried out between the upper computer and Pcie endpoint equipment;
4. the invention is suitable for the condition of electrifying and starting the chip through the pcie endpoint equipment, simplifies the complexity of electrifying and starting the chip through the pcie endpoint equipment, and can completely depend on the upper computer to operate all registers and memories in the endpoint equipment chip without the intervention of the cpu of the endpoint equipment, so when the cpu in the chip goes wrong, the operation such as debug and the like can still be carried out on the soc by the upper computer.
Drawings
FIG. 1 is a flow chart of a data addressing method provided by the present invention;
FIG. 2 is a flow chart of a data addressing method provided by the present invention;
fig. 3 is a schematic structural diagram of a memory device according to the present invention.
Reference numerals:
100-an upper computer, 200-a data storage device, 210-a configuration module and 220-a processing module.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
Under a basic Pcie protocol, the upper computer addressing Pcie endpoint equipment only supports fixed base address register space addressing, although a GB-level space can be set in a base address register, due to the memory limitation of the upper computer host, the address range which can be reserved for the upper computer can only be in MB level, and therefore the upper computer addressing Pcie endpoint equipment can only address the MB level space generally.
For the condition that the Pcie endpoint equipment needs to be addressed in a large range by the upper computer, the Pcie endpoint equipment is generally addressed in a Direct Memory Access (DMA) mode, and the direct DMA mode is suitable for performing instruction interaction by using a small amount of base address register space.
Based on the addressing method in the related art, DMA addressing generally requires an intervention of a cpu inside the end-point device soc to execute firmware (driver). Therefore, DMA addressing is only suitable for moving transfers between a host computer of large contiguous code and a Pcie endpoint device, which can be extremely time consuming when transferring short data. In addition, if the whole chip needs to be started through the pcie interface, if the DMA mode is used for addressing, the power-on scheme of the chip is very complicated and is not easy to implement.
In view of the above technical problems, the present application proposes the following technical solutions.
In the related embodiment, for the above technical problem, the following solution is performed:
firstly, a base address register space of the Pcie endpoint equipment is configured firstly, so that the Pcie endpoint equipment can receive data of the upper computer, and a storage space of the base address register of the Pcie endpoint equipment is configured to be small enough as much as possible so that enough memory space can be provided for address mapping of the upper computer equipment. After the base address register of the Pdie endpoint equipment is configured, the base address register of the Pdie endpoint equipment has a fixed mapping address and a fixed storage space size, and then the upper computer can carry out data transfer between the storage of the upper computer and the storage of the Pdie endpoint equipment soc through the base address register of the Pdie endpoint equipment.
The scheme has the disadvantage that although the host computer can rapidly access the base address register space of the Pdie endpoint equipment end in an addressing mode, large-area data transfer cannot be carried out due to the limitation of the size of the base address register space.
And secondly, actively initiating a data transfer operation through a Direct Memory Access (DMA) inside a Pcie (peripheral component interconnect express) endpoint device, and transferring data of an upper computer end into the Pcie endpoint device or transferring data of the Pcie endpoint device end into the upper computer. The DMA transfer process comprises the steps that firstly, an upper computer sends a source address, a destination address and a transfer length to a storage space of a Pcie endpoint device soc through a certain base address register, then, interruption of a cpu of the Pcie endpoint device soc is triggered, the cpu of the soc reads information from a memory mapped by the base address register and analyzes the source address, the destination address and the transfer length, and the DMA is configured according to an analysis result, so that the DMA carries out data transfer operation.
The method has the defect that the method is only suitable for large-segment continuous data transfer because the CPU of the upper computer and the Pcie endpoint equipment soc are required to be subjected to handshake operation and DMA is required to be configured each time. And DMA operation requires the intervention of a chip internal cpu to control DMA operation, and when the chip internal cpu of the Pdie endpoint equipment is unavailable, the method cannot realize data moving.
And thirdly, enabling the Pdie endpoint equipment soc to actively initiate data transfer operation, and sending the internal memory data of the soc to the upper computer or reading the internal memory data of the upper computer to the internal memory of the soc. The process is as follows: the host computer sends the source address, the destination address and the moving length to the soc storage space through a certain base address register, then the interrupt of the cpu of the Pcie endpoint equipment soc is triggered, the cpu of the soc reads information from the memory mapped by the base address register space, the source address, the destination address and the moving length are analyzed, and then the cpu of the soc controls the Pcie endpoint equipment to send a data moving instruction, so that the data stored in the host computer and stored in the soc are moved.
The method has the disadvantages that the data moving speed is low, and chip CPU resources are occupied for data moving operation. And the CPU inside the chip is required to intervene to control Pdie endpoint equipment to carry out data movement.
Aiming at the technical problems, the invention provides the following technical scheme to solve the problems in the prior art:
the present invention will be described in detail below with reference to the accompanying drawings and examples.
In one embodiment, as shown in fig. 1-2, the present invention provides a data addressing method, including: s101, configuring a mapping relation between a first base address register and a memory space;
s103, transferring the data received by the first base address register to a memory space which has a mapping relation with the first base address register.
The mapping relation between the first base address register and the memory is configured, so that the data in the first base address register can be transferred to the memory space, and the data transfer is realized. The first base address register and the memory space are both arranged in the Pcie endpoint equipment, and the memory space is the storage space of the Pcie endpoint equipment soc.
Further, configuring a mapping relationship between the first base address register and the memory space includes:
s201, establishing a base address mapping relation with an upper computer;
and the storage space corresponding to the second base address register of the Pceie endpoint equipment is mapped to the configuration space of the Pceie endpoint equipment by default, and the upper computer is operated to configure the mapping relation between the memory space of the upper computer and the storage space corresponding to the second base address register.
And similarly, operating the upper computer to configure the mapping relation between the memory space of the upper computer and the corresponding storage space of the first base address register. S203, receiving configuration data, wherein the configuration data is the mapping relation between the first base address register and the storage space;
when a second base address register of the Pcie endpoint equipment has a base address mapping relation with the upper computer, the second base address register can receive configuration data sent by the upper computer.
S205, the configuration data is transferred and stored, so that the configuration register corresponding to the first base address register receives the configuration data to complete configuration.
The Pcie endpoint equipment is internally provided with a configuration space, the configuration space comprises a configuration register, and the configuration space is used for receiving configuration data transmitted by the upper computer which is transferred by the second base address register.
Further, the configuration data is a mapping relation between a base address of the first base address register and a base address of the storage space. The memory space is the memory space of the Pcie endpoint device soc, and the memory space of the soc comprises a register space and a DDR (Double Data Rate synchronous dynamic random access memory). In hardware, it must be ensured that a slave bus of the pci endpoint device can access critical addresses such as DDR and registers inside a chip of the pci endpoint device. It will also be appreciated that there is a default mapping of the first base address register, which maps to the Pcie endpoint device's DDR or registers by default. Specifically, the mapping relationship between the first base address register and the Pcie endpoint device may be fixed inside the circuit in the ic design stage, or a default pointer may be set in firmware (driver).
In some embodiments, the configuration space of the Pcie endpoint device includes two configuration registers, where the first base address register may be two, one base address register is set as an IO type base address register, and the other base address register is a mem type base address register. The IO (Input/Output) type base address register size may be 4KB (Kilobyte kilobytes) and the mem (memory) type base address register size may be 1MB (MByte).
The two configuration registers correspond to the two first base address registers one to one, and based on configuration data of the second base address register, each configuration register stores configuration data corresponding to one first base address register, and the configuration data includes address mapping between the first base address register and a storage space of the Pcie endpoint device soc. The address mapping of the first base address and the storage space of the Pcie endpoint device soc may be altered by the configuration data to implement the sliding window function.
Further, the first base address register based on the IO type can sequentially perform data transfer between the upper computer and the Pcie endpoint device soc, so as to implement large-range addressing between the upper computer and the Pcie endpoint device soc. The first base address register based on the mem type can carry out block data moving between the upper computer and the Pdie endpoint equipment soc so as to realize large-range addressing between the upper computer and the Pdie endpoint equipment soc.
In the embodiment of the application, the method has the following characteristics: 1. the software and hardware matching design of the invention achieves the purpose that the inner addressing of the Pcie endpoint equipment soc is carried out in a large range only by depending on an upper computer without the intervention of a cpu in the Pcie endpoint equipment soc; 2. and the upper computer can modify all configurations of the Pcie endpoint equipment through the second base address register. The modification comprises that the upper computer can modify the mapping address and the storage space size of the first base address register by configuring a second base address register so as to achieve the purpose of sliding the window; 3. the two first base address registers can enable the upper computer to access the register space inside the Pdie endpoint equipment chip. One first base address register is set to be 4k in size and io type, and the other first base address register is set to be 1MB in size and mem type, so that large-range soc internal addressing is carried out between the upper computer and the Pcie endpoint equipment; 4. the invention is suitable for the condition of electrifying and starting the chip through the pcie endpoint equipment, simplifies the complexity of electrifying and starting the chip through the pcie endpoint equipment, and can completely depend on the upper computer to operate all registers and memories in the endpoint equipment chip without the intervention of the cpu of the endpoint equipment, so when the cpu in the chip goes wrong, the operation such as debug and the like can still be carried out on the soc by the upper computer.
According to a second aspect of the present invention, as shown in fig. 3, the present invention provides a data storage device 200 comprising a configuration module 210 and a first base address register. The configuration module 210 is configured to configure a mapping relationship between a first base address register and a memory space, where the first base address register is used to dump received data to the memory space having the mapping relationship with the first base address register.
The data storage device 200 may be a Pcie endpoint device, and the configuration module 210 configures a mapping relationship between the first base address register and the memory, so that data in the first base address register can be transferred to the memory space, thereby implementing data transfer. The configuration module 210, the first base address register, and the memory space are all disposed in the Pcie endpoint device, the memory space is a storage space of the processing module 220 of the Pcie endpoint device, and the processing module 220 may be an SOC.
Further, the configuration module 210 includes a second base address register and a configuration register corresponding to the first base address register. The second base address register is used for receiving configuration data, the configuration data is the mapping relation between the first base address register and the storage space, and the configuration data is transferred and stored. The first base address register corresponds to the configuration register for receiving configuration data to complete the configuration.
When a base address mapping relationship exists between a second base address register of the Pcie endpoint equipment and the upper computer 100, the second base address register can receive configuration data sent by the upper computer 100.
Further, the configuration data is a mapping relation between a base address of the first base address register and a base address of the storage space. The memory space is a memory space of the Pcie endpoint device processing module 220, and the memory space of the processing module 220 includes a register space and a DDR (Double Data Rate synchronous dynamic random access memory). In hardware, it must be ensured that a slave bus of the pci endpoint device can access critical addresses such as DDR and registers inside a chip of the pci endpoint device.
Furthermore, the number of the first base address registers is at least two, the two first base address registers are IO type base address registers, and the other one is mem type base address register.
Specifically, the configuration space of the Pcie endpoint device includes two configuration registers, where the first base address register may be two, one base address register is set as an IO type base address register, and the other base address register is a mem type base address register. The IO (Input/Output) type base address register size may be 4KB (Kilobyte kilobytes) and the mem type base address register size may be 1MB (MByte).
The two configuration registers correspond to the two first base address registers one to one, and based on configuration data of the second base address register, each configuration register stores configuration data corresponding to one first base address register, where the configuration data includes address mapping between the first base address register and a storage space of the Pcie endpoint device processing module 220. The sliding window function may be implemented by configuring the data to alter the address mapping of the first base address to the memory space of the Pcie endpoint device processing module 220.
Further, the first base address register based on the IO type may sequentially perform data transfer between the upper computer 100 and the Pcie endpoint device processing module 220, so as to implement large-range addressing between the upper computer 100 and the Pcie endpoint device processing module 220. The first base address register based on the mem type can carry out block data transfer between the upper computer 100 and the Pdie endpoint device processing module 220, so as to realize large-range addressing between the upper computer 100 and the Pdie endpoint device processing module 220.
In the embodiment of the application, the method has the following characteristics: 1. the software and hardware matching design of the invention achieves the purpose that the internal addressing of the Pcie endpoint equipment processing module 220 in a large range is carried out only by the upper computer 100 without the intervention of a cpu in the Pcie endpoint equipment processing module 220; 2. the upper computer 100 can modify all configurations of the Pcie endpoint equipment through the second base address register. The modification comprises that the upper computer 100 can modify the mapping address and the storage space size of the first base address register by configuring a second base address register so as to achieve the purpose of sliding the window; 3. both first base address registers enable the upper computer 100 to access the register space inside the Pdie endpoint device chip. One first base address register is set to be 4k in size and io type, and the other first base address register is set to be 1MB in size and mem type, so that large-range internal addressing of the processing module 220 is carried out between the upper computer 100 and the Pcie endpoint equipment; 4. the invention is suitable for the condition of powering on and starting the chip through the pcie endpoint device, simplifies the complexity of powering on and starting through the pcie endpoint device, and can completely depend on the upper computer 100 to operate all registers and memories in the endpoint device chip without intervention of the cpu of the endpoint device, so when the cpu in the chip has a problem, the upper computer 100 can still depend on the processing module 220 to perform debug and other operations.
According to a third aspect of the present invention, the present invention provides a chip, including the data storage apparatus 200 of any one of the above embodiments, and a memory space connected to the first base address register, where the memory space is a memory space of the Pcie endpoint device processing module 220, and the memory space is used for storing data offloaded by the first base address register.
Furthermore, the number of the memory spaces is at least two, one of the two memory spaces is a DDR (Double Data Rate Double Data synchronous dynamic random access memory) for storing block Data, and the other memory space is a storage register for storing IO Data.
According to a fourth aspect of the present invention, the present invention provides a data storage system, which includes the upper computer 100 and the above chip, where the upper computer 100 sequentially sends configuration data and data to be stored, the chip configures a mapping relationship between a first base address register and a memory space according to the received configuration data, and according to the received data to be stored, the chip transfers the data received by the first base address register to the memory space having a mapping relationship with the first base address register.
Specifically, the chip is powered on based on the pcie (peripheral component interconnect express high-speed serial computer expansion bus standard). The invention simplifies the complexity of power-on starting through the Pcie, and can completely depend on the upper computer 100 to operate all registers and memories in the chip of the Pcie endpoint equipment without the intervention of the cpu, so that when the cpu in the chip has a problem, the upper computer 100 can still depend on to perform debug and other operations on the processing module 220.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.
Claims (10)
1. A method of addressing data, comprising:
configuring a mapping relation between a first base address register and a memory space;
and unloading the data received by the first base address register to the memory space which has a mapping relation with the first base address register.
2. The data addressing method of claim 1, wherein configuring the mapping of the first base address register to the memory space comprises:
receiving configuration data, wherein the configuration data is the mapping relation between the first base address register and a storage space;
and unloading the configuration data to enable the configuration register corresponding to the first base address register to receive the configuration data so as to complete the configuration.
3. The data addressing method of claim 2, wherein the configuration data is a mapping of a base address of the first base address register to a base address of the memory space.
4. A data storage device, comprising:
the configuration module is used for configuring the mapping relation between the first base address register and the memory space;
the first base address register is used for transferring the received data to the memory space which has a mapping relation with the first base address register.
5. The data storage device of claim 4, wherein the configuration module comprises:
the second base address register is used for receiving configuration data, wherein the configuration data is the mapping relation between the first base address register and a storage space, and the configuration data is stored in a dump way;
and the configuration register corresponding to the first base address register is used for receiving the configuration data to complete the configuration.
6. The data storage device of claim 5,
the configuration data is a mapping relation between a base address of the first base address register and a base address of the storage space.
7. The data storage device of any one of claims 4-6,
the number of the first base address registers is at least two, one of the two first base address registers is an IO type base address register, and the other one is a mem type base address register.
8. A chip comprising a data storage device according to any of claims 4 to 7 and a memory space connected to said first base address register;
the memory space is used to store the data that is transferred by the first base address register.
9. The chip of claim 8, wherein the number of the memory spaces is at least two, and one of the two memory spaces is used for storing block data, and the other is used for storing IO data.
10. A data storage system, comprising: a host computer and a chip as claimed in claim 8 or 9;
the upper computer sends configuration data and data to be stored in sequence;
the chip configures the mapping relation between a first base address register and a memory space according to the received configuration data, and transfers the data received by the first base address register to the memory space having the mapping relation with the first base address register according to the received data to be stored.
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Cited By (2)
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| CN112817899A (en) * | 2021-04-19 | 2021-05-18 | 浙江华创视讯科技有限公司 | PCIE-based data transmission method and device, storage medium and electronic equipment |
| CN115827546A (en) * | 2023-02-15 | 2023-03-21 | 北京象帝先计算技术有限公司 | PCIe device, electronic assembly, electronic device and address mapping method |
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| CN1731371A (en) * | 2005-09-07 | 2006-02-08 | 大唐微电子技术有限公司 | Method of storage unit access in digital signal processing system and processing system therefor |
| CN101639810A (en) * | 2009-08-26 | 2010-02-03 | 杭州华三通信技术有限公司 | Method and device for accessing PCI memory space |
| US20120030401A1 (en) * | 2009-09-25 | 2012-02-02 | Cowan Joe P | Mapping non-prefetchable storage locations into memory mapped input/output space |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112817899A (en) * | 2021-04-19 | 2021-05-18 | 浙江华创视讯科技有限公司 | PCIE-based data transmission method and device, storage medium and electronic equipment |
| CN115827546A (en) * | 2023-02-15 | 2023-03-21 | 北京象帝先计算技术有限公司 | PCIe device, electronic assembly, electronic device and address mapping method |
| CN115827546B (en) * | 2023-02-15 | 2023-04-18 | 北京象帝先计算技术有限公司 | PCIe device, electronic assembly, electronic device and address mapping method |
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