CN1275809A - Semiconductor device having capacitance element and formation method thereof - Google Patents
Semiconductor device having capacitance element and formation method thereof Download PDFInfo
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- CN1275809A CN1275809A CN 00109321 CN00109321A CN1275809A CN 1275809 A CN1275809 A CN 1275809A CN 00109321 CN00109321 CN 00109321 CN 00109321 A CN00109321 A CN 00109321A CN 1275809 A CN1275809 A CN 1275809A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims description 35
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 239000012212 insulator Substances 0.000 claims abstract description 99
- 238000002955 isolation Methods 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000009413 insulation Methods 0.000 claims abstract description 11
- 239000011229 interlayer Substances 0.000 claims abstract description 6
- 230000004888 barrier function Effects 0.000 claims description 40
- 239000003990 capacitor Substances 0.000 claims description 32
- 238000005498 polishing Methods 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- 238000005530 etching Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 239000000126 substance Substances 0.000 description 4
- 239000002352 surface water Substances 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 3
- 238000005260 corrosion Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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Abstract
A semiconductor device comprises; a semiconductor substrate having an isolation groove, and an isolation film within the isolation groove. The isolation film has within it a shallower groove. A bottom electrode of a capacitive element is buried within the shallower groove in the isolation film. An insulation film comprises a capacitive dielectric film of the capacitive element over the bottom electrode and the isolation film, and a gate insulation film over the semiconductor substrate; There is a top electrode of the capacitive element on the capacitive dielectric film and a gate electrode on the gate insulation film. The top electrode and the gate electrode have substantially the same level as each other. A surface-planarized inter-layer insulator, lies over the semiconductor substrate so that the top electrode and the gate electrode are completely buried within the surface-planarized inter-layer insulator.
Description
The present invention relates to semiconductor device and forming method thereof, particularly have semiconductor device with the capacity cell of electrode buried in barrier film and forming method thereof.
Usually, capacity cell has following array structure.Fig. 1 is the part sectional front view that expression has the conventional semiconductor device of capacity cell.In Semiconductor substrate 10, form isolation channel.In isolation channel, form barrier film 11.On the barrier film on the upper surface of Semiconductor substrate 10 and in isolation channel 11, form silicon oxide film 14.On silicon oxide film 14 and form the bottom electrode 12 of capacity cell above the barrier film 11 selectively.On bottom electrode 12, form dielectric oxide film 13.On dielectric oxide film 13, form top electrode 15.Bottom electrode 12, dielectric oxide film 13 and top electrode 15 form capacity cell.On silicon oxide film 14, form transistorized grid selectively.Form the interlevel insulator 17 that covers capacity cell and transistorized grid 16, thereby capacity cell and grid 16 are completely buried in the interlevel insulator.Interlevel insulator is flattened.The top of the top electrode 15 of capacity cell has first degree of depth " D " apart from interlevel insulator 17 flattened surfaces.The top of transistor gate 16 has second degree of depth " E " apart from the planar surface of interlevel insulator 17.Second degree of depth " E " is darker than first degree of depth " D ".
Before interlevel insulator 17 surperficial flattened, this surperficial horizontal plane is along with capacity cell and transistorized grid 16 and change.That is, interlevel insulator 17 have first on the capacity cell than thickness portion and on grid 16 second than thickness portion.Because the height of the transistorized grid 16 of aspect ratio of capacity cell, therefore first is thicker than thickness portion than second than thickness portion.The surface that the horizontal plane of interlevel insulator 17 changes is by the chemico-mechanical polishing complanation.The first first processing capacity that is subjected in the glossing than thickness portion of the interlevel insulator 17 on the capacity cell is handled, and the second second largest processing capacity that is subjected in the glossing than thickness portion of the interlevel insulator 17 on transistor gate 16 is handled.First processing capacity is handled than second largest processing capacity and is handled greatly.That is, first of the interlevel insulator on the capacity cell 17 maximum processing capacity that is subjected in the glossing than thickness portion is handled.In addition, form first contact hole in the interlevel insulator 17 on capacity cell, first contact hole is connected with the upper surface of the top electrode 15 of capacity cell.The degree of depth of first contact hole is first degree of depth " D ".Form second contact hole in the interlevel insulator 17 on transistorized grid 16, second contact hole is connected with the upper surface of the grid 16 of capacity cell.The degree of depth of second contact hole is second degree of depth " E ".If by utilizing the resist figure to form first and second contact holes simultaneously with identical anisotropic etch, the anisotropic etch that then forms first contact hole was finished before forming second contact hole.Promptly, when first contact hole is formed and contacts with the top electrode 15 of capacity cell, second contact hole on the grid 16 does not arrive grid 16, therefore anisotropic etch is proceeded so that second contact hole arrives transistorized grid 16, and the top electrode 15 of capacity cell is subjected to the damage of excessive processing of the further anisotropy rot etching technique of self-forming second contact hole thus.
In Japan special permission publication communique No.63-186444, disclose polysilicon electrode has been buried in technology in the field oxide film.This will cause the very big difference of the horizontal plane of dielectric film.
In the Japan special permission publication communique No.7-60859, disclose cell electrode and be buried in technology in the barrier film.
This routine techniques is not the top electrode that grid and capacity cell are provided in the interlevel insulator with identical or uniform thickness, and therefore this routine techniques and the present invention are irrelevant.
As mentioned above, above-mentioned routine techniques has following point.
Before the surface of complanation interlevel insulator 17, the surface water plane is along with capacity cell and transistorized grid and change.That is, interlevel insulator 17 have first on the capacity cell than thickness portion and on grid 16 second than thickness portion.Because transistorized grid 16 height of aspect ratio of capacity cell, therefore first is thicker than thickness portion than second than thickness portion.The surface that the horizontal plane of interlevel insulator 17 changes is by the chemico-mechanical polishing complanation.First of interlevel insulator 17 on the capacity cell is subjected to the big processing capacity of first in the glossing than thickness portion and handles, and second of the interlevel insulator 17 on transistor gate 16 is accepted the big processing capacity of second in the glossing than thickness portion and handled.First processing capacity is handled than second processing capacity and is handled greatly.That is, first of the interlevel insulator on the capacity cell 17 maximum processing capacity that is subjected in the glossing than thickness portion is handled.In addition, form first contact hole in the interlevel insulator 17 on capacity cell, first contact hole is connected with the upper surface of the top electrode 15 of capacity cell.The degree of depth of first contact hole is first degree of depth " D ".Form second contact hole in the interlevel insulator 17 on transistor gate 16, second contact hole is connected with the upper surface of the grid 16 of capacity cell.The degree of depth of second contact hole is second degree of depth " E ".If form first and second contact holes simultaneously by the identical anisotropic etch that utilizes the resist figure, the anisotropic etch that then forms first contact hole was finished before forming second contact hole.Promptly, when first contact hole is formed and contacts with the top electrode 15 of capacity cell, second contact hole on the grid 16 does not arrive grid 16, therefore anisotropic etch continues further to carry out so that second contact hole arrives transistorized grid 16, and the top electrode 15 of capacity cell is subjected to the excessive damage of the further anisotropy rot etching technique of self-forming second contact hole thus.
In these cases, need a kind of novel semi-conductor device that does not have the problems referred to above of development with capacity cell.
Thereby, the purpose of this invention is to provide the new semiconductor device that does not have the problems referred to above with capacity cell.
Another object of the present invention provides the semiconductor device with capacity cell, can not apply any excessive processing to capacity cell at the planarization technology that is used for the complanation interlevel insulator.
A further object of the present invention provides the novel semi-conductor device with capacity cell, can not apply any excessive processing to capacity cell in the CMP (Chemical Mechanical Polishing) process that is used for the complanation interlevel insulator.
Another purpose of the present invention provides the novel semi-conductor device with capacity cell, wherein first thickness of the interlevel insulator on the capacity cell is substantially equal to second thickness of the interlevel insulator on the transistor gate, thereby can in identical anisotropy rot etching technique, form first and second contact holes on capacity cell and the transistor gate simultaneously, wherein first and second contact holes arrive capacity cell and grid simultaneously, and capacity cell is not subjected to handling any damage that causes by excessive corrosion thus.
The invention provides a kind of semiconductor device, comprising: Semiconductor substrate with isolation channel; Barrier film in isolation channel, this barrier film have the groove more shallow than isolation channel; The bottom electrode of capacity cell is buried in the shallow slot of barrier film; Dielectric film comprises the capacitor dielectric film of the capacity cell on bottom electrode and the barrier film and the gate insulating film on the Semiconductor substrate; The top electrode of the capacity cell on the capacitor dielectric film; Grid on the gate insulating film, wherein top electrode has consistent basically horizontal plane with grid; Surface planarization interlayer insulator on Semiconductor substrate, thus top electrode and grid are buried in the surface planarization interlayer insulator fully.
Make above and other objects of the present invention, characteristics and advantage more obvious by following description.
Introduce according to a preferred embodiment of the invention in detail with reference to the accompanying drawings.
Fig. 1 is that expression has the front view that the part of conventional semiconductor device of capacity cell is analysed and observe.
Fig. 2 is the front view that the part of the first novel semi-conductor device with capacity cell in the expression preferred embodiment of the present invention is analysed and observe.
Fig. 3 A-3H is the first aspect figure that the part of the semiconductor device with capacity cell in the consecutive steps that is illustrated in the new method that is included in the semiconductor device in the formation first preferred embodiment of the invention is analysed and observe.
A first aspect of the present invention provides a kind of semiconductor device, comprising: the Semiconductor substrate with isolation channel; Barrier film in isolation channel, this barrier film have the groove more shallow than isolation channel; The bottom electrode of capacity cell is buried in the shallow slot of barrier film; Dielectric film is included in the capacitor dielectric film of the capacity cell on bottom electrode and the barrier film and the gate insulating film on the Semiconductor substrate; The top electrode of the capacity cell on the capacitor dielectric film; Grid on the gate insulating film, wherein top electrode has consistent basically horizontal plane with grid; Surface on Semiconductor substrate is with the interlevel insulator complanation, thereby top electrode and grid are buried in the flattened interlevel insulator in surface fully.
The planar surface that the top electrode of capacity cell and transistorized grid are preferably apart from interlevel insulator has the substantially the same degree of depth.
Capacitor dielectric film and gate insulating film also preferably have substantially the same thickness.
Second aspect present invention is provided at the capacity cell in the semiconductor device, and this semiconductor device has the transistor that has grid.This capacity cell comprises: the bottom electrode in the shallow slot in barrier film, in the isolation channel of this barrier film in Semiconductor substrate; Capacitor dielectric film on bottom electrode, this capacitor dielectric film is included in a part of insulation film that extends on the Semiconductor substrate; With the top electrode on the capacitor dielectric film, this top electrode has the horizontal plane substantially the same with the grid on the insulation film, and this top electrode and grid are buried in the interlevel insulator.
The planar surface that the top electrode of capacity cell and transistorized grid are preferably apart from interlevel insulator has the substantially the same degree of depth.
Capacitor dielectric film and gate insulating film also are preferably has substantially the same thickness.
Third aspect present invention provides the method that forms semiconductor device, may further comprise the steps: form isolation channel selectively in Semiconductor substrate; In isolation channel, form barrier film; Form shallow slot in barrier film selectively, wherein shallow slot is more shallow than isolation channel; Form the bottom electrode of capacity cell in the shallow slot in barrier film; Formation comprises the capacitor dielectric film of the capacity cell on bottom electrode and the barrier film and the dielectric film of the gate insulating film on the Semiconductor substrate; Form the top electrode of capacity cell and form grid on the capacitor dielectric film on gate insulating film, wherein top electrode has consistent basically horizontal plane with grid; With on Semiconductor substrate, form interlevel insulator, top electrode and grid are buried in the interlevel insulator fully.
Preferably that the surface of interlevel insulator is further flattened.
More preferably carry out chemico-mechanical polishing with the interlevel insulator complanation.
The planar surface that the top electrode of capacity cell and transistorized grid are preferably apart from interlevel insulator has the substantially the same degree of depth.
Capacitor dielectric film and gate insulating film are preferably has substantially the same thickness.
Fourth aspect present invention provides the method that forms capacity cell, may further comprise the steps: form bottom electrode in the shallow slot of the barrier film in the isolation channel of Semiconductor substrate; On bottom electrode, form the capacitor dielectric film, and the capacitor dielectric film is included in a part of insulation film that extends on the Semiconductor substrate; With on the capacitor dielectric film, form top electrode, top electrode has basically and the identical horizontal plane of grid on the insulation film, and top electrode and grid are buried in the interlevel insulator.
The surface of interlevel insulator is preferably by further complanation.
More preferably carry out chemico-mechanical polishing with surface planarization with interlevel insulator.
The planar surface that the top electrode of capacity cell and transistorized grid are preferably apart from interlevel insulator has the substantially the same degree of depth.
Capacitor dielectric film and gate insulating film are preferably has substantially the same thickness.
Introduce according to the first embodiment of the present invention in detail referring now to accompanying drawing.Fig. 2 is illustrated in the front view of analysing and observe according to the part of the first novel semi-conductor device with capacity cell in the first embodiment of the present invention.In Semiconductor substrate 10, form isolation channel.In isolation channel, form barrier film 11.On the upper surface of Semiconductor substrate 10 and on the barrier film 11 in the isolation channel, form silicon oxide film.Below silicon oxide film and in the barrier film 11, form the bottom electrode 12 of capacity cell selectively.That is, the bottom electrode 12 of capacity cell is buried in the barrier film 11 in the isolation channel fully, thus the upper surface flush of the upper surface of the upper surface of bottom electrode 12 and barrier film 11 and Semiconductor substrate 10.Silicon oxide film on the bottom electrode 12 of capacity cell is used as the deielectric-coating 13 of capacity cell.Also on silicon oxide film, form transistorized grid 16 selectively.Silicon oxide film on the transistorized grid 16 is used as transistorized gate oxidation films 14.On dielectric oxide film 13, form top electrode 15.That is, the top electrode 15 of capacity cell and transistorized grid 16 are formed on the same silicon oxide film.Also form top electrode 15 and the transistorized grid 16 of interlevel insulator 17, thereby capacity cell and grid 16 are embedded in the interlevel insulator fully with the covering capacity cell.Interlevel insulator 17 has planar surface.The top of the top electrode 15 of capacity cell has first degree of depth " A " apart from the planar surface of interlevel insulator 17.The top of transistorized grid 16 has the 3rd degree of depth " C " apart from the planar surface of interlevel insulator 17.The 3rd degree of depth " C " is substantially equal to first degree of depth " A ".Second degree of depth " B " between the bottom of the bottom of isolation channel or barrier film 11 and the bottom electrode of capacity cell 12 is decided according to driving voltage.
Before interlevel insulator 17 surperficial flattened, the surface water plane changes according to the top electrode 15 and the transistorized grid 16 of capacity cell.That is, interlevel insulator 17 have first on the capacity cell than thickness portion and on grid 16 second than thickness portion.Because the height with transistorized grid 16 is identical basically for the height of the top electrode 15 of capacity cell, therefore first thickness than thickness portion is substantially equal to second thickness than thickness portion.Utilize the surface of the horizontal plane variation of chemico-mechanical polishing complanation interlevel insulator 17 then.First first processing capacity that is subjected in the glossing than thickness portion of the interlevel insulator 17 on the top electrode 15 of capacity cell is handled, and second second processing capacity that is subjected in the glossing than thickness portion of the interlevel insulator on transistorized grid 16 is handled.First processing capacity is handled basically and is handled identical with second processing capacity.That is, first of the interlevel insulator 17 on the top electrode 15 of the capacity cell processing capacity that is subjected to the minimizing in the glossing than thickness portion is handled.In addition, form first contact hole in the interlevel insulator 17 on the top electrode 15 of capacity cell, so that first contact hole is connected on the upper surface of top electrode 15 of capacity cell.The degree of depth of first contact hole is above-mentioned first degree of depth " A ".Also form second contact hole in the interlevel insulator 17 on transistorized grid 16, so that second contact hole is connected on the upper surface of grid 16 of capacity cell.The degree of depth of second contact hole is above-mentioned the 3rd degree of depth " C ", and this degree of depth " C " is substantially equal to first degree of depth " A " of first contact hole.If first and second contact holes are to utilize the resist figure to form simultaneously with identical anisotropic etch, the anisotropic etch that then forms first contact hole is finished simultaneously with the anisotropic etch that forms second contact hole basically.That is, be formed and with when the top electrode 15 of capacity cell contacts, second contact hole on the grid 16 also arrives grid 16, so the top electrode 15 of capacity cell is not subjected to the damage of the excessive processing of anisotropy rot etching technique at first contact hole.
As mentioned above, above-mentioned new technology has the following advantages.
Before interlevel insulator 17 surperficial flattened, the surface water plane changes according to the top electrode 15 and the transistorized grid 16 of capacity cell.That is, interlevel insulator 17 have first on the capacity cell than thickness portion and on grid 16 second than thickness portion.Because the height with transistorized grid 16 is identical basically for the height of the top electrode 15 of capacity cell, therefore first thickness than thickness portion is substantially equal to second thickness than thickness portion.Utilize the surface of the horizontal plane variation of chemico-mechanical polishing complanation interlevel insulator 17 then.First first processing capacity that is subjected in the glossing than thickness portion of the interlevel insulator 17 on the top electrode 15 of capacity cell is handled, and second second processing capacity that is subjected in the glossing than thickness portion of the interlevel insulator on transistorized grid 16 is handled.First processing capacity is handled basically and is handled identical with second processing capacity.That is, first of the interlevel insulator 17 on the top electrode 15 of the capacity cell processing capacity that is subjected to the minimizing in the glossing than thickness portion is handled.In addition, form first contact hole in the interlevel insulator 17 on the top electrode 15 of capacity cell, so that first contact hole is connected on the upper surface of top electrode 15 of capacity cell.The degree of depth of first contact hole is above-mentioned first degree of depth " A ".Also form second contact hole in the interlevel insulator 17 on transistorized grid 16, so that second contact hole is connected on the upper surface of grid 16 of capacity cell.The degree of depth of second contact hole is above-mentioned the 3rd degree of depth " C ", and this degree of depth " C " is substantially equal to first degree of depth " A " of first contact hole.If first and second contact holes are to form simultaneously by the identical anisotropic etch that utilizes the resist figure, the anisotropic etch that then forms first contact hole is finished simultaneously with the anisotropic etch that forms second contact hole basically.That is, be formed and with when the top electrode 15 of capacity cell contacts, second contact hole on the grid 16 also arrives grid 16, so the top electrode 15 of capacity cell is not subjected to the damage of the excessive processing of anisotropy rot etching technique at first contact hole.
Thereby the top electrode 15 of capacity cell is not subjected to putting on any excessive processing of capacity cell in the planarization technology that is used for the complanation interlevel insulator (CMP (Chemical Mechanical Polishing) process that promptly is used for the complanation interlevel insulator).
Because first thickness of the interlevel insulator on the capacity cell is substantially equal to second thickness of the interlevel insulator on the transistor gate, therefore first and second contact holes on capacity cell and the transistor gate form in same anisotropic etch simultaneously, wherein first and second contact holes arrive capacity cell and grid simultaneously in the anisotropy rot etching technique, and the top electrode of capacity cell is not subjected to because excessive corrosion is handled any damage that causes thus.
Introduce above-mentioned new semiconductor device below with capacity cell.Fig. 3 A-3H is the part sectional front view of expression according to the semiconductor device with capacity cell of the first embodiment of the present invention in being included in the new method consecutive steps that forms semiconductor device.
With reference to Fig. 3 A, utilize photoetching process in Semiconductor substrate 10, to form isolation channel 18.In isolation channel 18, form barrier film 11.
With reference to Fig. 3 B, utilize in the barrier film 11 of photoetching process in isolation channel 18 and form shallow slot 19 selectively.Shallow slot 19 is more shallow than isolation channel 18.The degree of depth of shallow slot 19 is decided according to the driving voltage that is used for logical device.
With reference to Fig. 3 C, on Semiconductor substrate 10 He in the shallow slot 19, be completed into conducting film 12.
With reference to Fig. 3 D, utilize chemico-mechanical polishing complanation conducting film 12, so that conducting film 12 remains in the shallow slot 19, in shallow slot 19, form the bottom electrode 12 of capacity cell thus.
With reference to Fig. 3 E, on the Semiconductor substrate 10, forming silicon oxide film on the barrier film 11 and on the bottom electrode 12 at capacity cell.This silicon oxide film comprises capacitor dielectric film 13 on the bottom electrode 12 of barrier film 11 and capacity cell and the gate oxidation films 14 on the Semiconductor substrate 10.
With reference to Fig. 3 F, on capacitor dielectric film 13 and gate oxidation films 14, form top electrode 15 and grid 16 respectively selectively.
With reference to Fig. 3 G, deposit interlevel insulator 17 on whole Semiconductor substrate 10 is so that top electrode of capacity cell 15 and transistorized grid 16 are completely buried in the interlevel insulator 17.
With reference to Fig. 3 H, utilize the surface of CMP (Chemical Mechanical Polishing) process complanation interlevel insulator 17.
In addition, utilize photoetching process in the interlevel insulator 17 of complanation, to form the top electrode 15 and the transistorized grid 16 of capacity cell respectively.
Before interlevel insulator 17 surperficial flattened, the surface water plane changes according to the top electrode 15 and the transistorized grid 16 of capacity cell.That is, interlevel insulator 17 have first on the capacity cell than thickness portion and on grid 16 second than thickness portion.Because the height with transistorized grid 16 is identical basically for the height of the top electrode 15 of capacity cell, therefore first thickness than thickness portion is substantially equal to second thickness than thickness portion.Utilize chemico-mechanical polishing with the vicissitudinous surface planarization of the horizontal plane of interlevel insulator 17 then.First first processing capacity that is subjected in the glossing than thickness portion of the interlevel insulator 17 on the top electrode 15 of capacity cell is handled, and second second processing capacity that is subjected in the glossing than thickness portion of the interlevel insulator on transistorized grid 16 is handled.First processing capacity is identical with second processing capacity basically.That is, first of the interlevel insulator 17 on the top electrode 15 of the capacity cell processing capacity that is subjected to the minimizing in the glossing than thickness portion is handled.In addition, form first contact hole in the interlevel insulator 17 on the top electrode 15 of capacity cell, so that first contact hole is connected on the upper surface of top electrode 15 of capacity cell.The degree of depth of first contact hole is above-mentioned first degree of depth " A ".Also form second contact hole in the interlevel insulator 17 on transistorized grid 16, so that second contact hole is connected on the upper surface of grid 16 of capacity cell.The degree of depth of second contact hole is above-mentioned the 3rd degree of depth " C ", and this degree of depth " C " is substantially equal to first degree of depth " A " of first contact hole.If first and second contact holes are to form simultaneously by the identical anisotropic etch that utilizes the resist figure, the anisotropic etch that then forms first contact hole is finished simultaneously with the anisotropic etch that forms second contact hole basically.That is, be formed and with when the top electrode 15 of capacity cell contacts, second contact hole on the grid 16 also arrives grid 16, so the top electrode 15 of capacity cell is not subjected to the damage of the excessive processing of anisotropy rot etching technique at first contact hole.
Thereby the top electrode 15 of capacity cell is not subjected to putting on any excessive processing of capacity cell at the planarization technology that is used for the complanation interlevel insulator (CMP (Chemical Mechanical Polishing) process that promptly is used for the complanation interlevel insulator).
Because first thickness of the interlevel insulator on the capacity cell is substantially equal to second thickness of the interlevel insulator on the transistorized grid, therefore be in identical anisotropic etch, to form simultaneously at capacity cell with first and second contact holes on the transistor gate, wherein first and second contact holes arrive capacity cell and grid simultaneously, and the top electrode of capacity cell is not subjected to because excessive corrosion is handled any damage that causes thus.
Modification of the present invention is obviously to those skilled in the art, and these modifications belong in the scope of the present invention, should be understood that not providing constraints with described embodiment of being schematically shown.Thereby claims should cover all modifications that falls in the spirit and scope of the invention.
Claims (16)
1. semiconductor device comprises:
Semiconductor substrate with isolation channel;
Barrier film in described isolation channel, described barrier film have the groove more shallow than described isolation channel;
The bottom electrode of capacity cell is buried in the described shallow slot in the described barrier film;
Dielectric film is included in the capacitor dielectric film and the gate insulating film on described Semiconductor substrate of the described capacity cell on described bottom electrode and the described barrier film;
The top electrode of the described capacity cell on described capacitor dielectric film;
Grid on described gate insulating film, wherein said top electrode has consistent basically horizontal plane with described grid; With
Surface planarization interlayer insulator on described Semiconductor substrate is so that described top electrode and described grid are buried in the described surface planarization interlayer insulator fully.
2. semiconductor device according to claim 1, the described planar surface of the described top electrode of wherein said capacity cell and the described interlevel insulator of described transistorized described gate distance have a substantially the same degree of depth.
3. semiconductor device according to claim 1, wherein said capacitor dielectric film and described gate insulating film have substantially the same thickness.
4. the capacity cell in the semiconductor device, this semiconductor device has the transistor that has grid, and described capacity cell comprises:
Bottom electrode is in the shallow slot of the barrier film in the isolation channel of Semiconductor substrate;
Capacitor dielectric film on described bottom electrode, and described capacitor dielectric film is included in a part of insulation film that extends on the described Semiconductor substrate; With
Top electrode on described capacitor dielectric film, described top electrode have with described insulation film on the substantially the same horizontal plane of described grid, described top electrode and described grid are buried in the interlevel insulator.
5. capacity cell according to claim 4, the planar surface of the described top electrode of wherein said capacity cell and the described interlevel insulator of described transistorized described gate distance has the substantially the same degree of depth.
6. capacity cell according to claim 4, wherein said capacitor dielectric film and described gate insulating film have substantially the same thickness.
7. method that forms semiconductor device may further comprise the steps:
In Semiconductor substrate, form isolation channel selectively;
In described isolation channel, form barrier film;
Form shallow slot in described barrier film selectively, wherein said shallow slot is more shallow than described isolation channel;
Form the bottom electrode of capacity cell in the described shallow slot in described barrier film;
Form dielectric film, this dielectric film is included in the capacitor dielectric film and the gate insulating film on described Semiconductor substrate of the described capacity cell on described bottom electrode and the described barrier film;
Form the top electrode of described capacity cell and form grid on described capacitor dielectric film on described gate insulating film, wherein said top electrode has consistent basically horizontal plane with described grid; With
On described Semiconductor substrate, form interlevel insulator, so that described top electrode and described grid are buried in the described interlevel insulator fully.
8. method according to claim 7, the surface of wherein said interlevel insulator is also flattened.
9. method according to claim 8 is wherein carried out chemico-mechanical polishing with the described surface planarization with described interlevel insulator.
10. method according to claim 8, the surface of the described complanation of the described top electrode of wherein said capacity cell and the described interlevel insulator of described transistorized described gate distance has the substantially the same degree of depth.
11. method according to claim 8, wherein said capacitor dielectric film and described gate insulating film have substantially the same thickness.
12. a method that forms capacity cell may further comprise the steps:
Form bottom electrode in the shallow slot of the barrier film in the isolation channel of Semiconductor substrate;
On described bottom electrode, form the capacitor dielectric film, and described capacitor dielectric film is included in a part of insulation film that extends on the described Semiconductor substrate; With
On described capacitor dielectric film, form top electrode, described top electrode have with described insulation film on the substantially the same horizontal plane of described grid, and described top electrode and described grid are buried in the interlevel insulator.
13. method according to claim 12, the surface of wherein said interlevel insulator is also flattened.
14. method according to claim 13 is wherein carried out chemico-mechanical polishing with the described surface planarization with described interlevel insulator.
15. method according to claim 13, the described planar surface of the described top electrode of wherein said capacity cell and the described interlevel insulator of described transistorized described gate distance has the substantially the same degree of depth.
16. method according to claim 13, wherein said capacitor dielectric film and described gate insulating film have substantially the same thickness.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11148480A JP2000340645A (en) | 1999-05-27 | 1999-05-27 | Semiconductor device and its manufacture |
| JP148480/1999 | 1999-05-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1275809A true CN1275809A (en) | 2000-12-06 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 00109321 Pending CN1275809A (en) | 1999-05-27 | 2000-05-26 | Semiconductor device having capacitance element and formation method thereof |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP2000340645A (en) |
| CN (1) | CN1275809A (en) |
| GB (1) | GB2352328A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7863664B2 (en) | 2007-03-16 | 2011-01-04 | Fujitsu Semiconductor Limited | Semiconductor device and method for manufacturing the same |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4994437B2 (en) * | 2009-11-18 | 2012-08-08 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device and manufacturing method thereof |
| JP5563811B2 (en) * | 2009-12-09 | 2014-07-30 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method of semiconductor device |
| JP7086018B2 (en) | 2019-03-12 | 2022-06-17 | ルネサスエレクトロニクス株式会社 | Semiconductor devices and their manufacturing methods |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG45497A1 (en) * | 1995-09-05 | 1998-01-16 | Chartered Semiconductors Manuf | Low profile shallon trench double polysilicon capacitor |
-
1999
- 1999-05-27 JP JP11148480A patent/JP2000340645A/en active Pending
-
2000
- 2000-05-26 GB GB0012982A patent/GB2352328A/en not_active Withdrawn
- 2000-05-26 CN CN 00109321 patent/CN1275809A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7863664B2 (en) | 2007-03-16 | 2011-01-04 | Fujitsu Semiconductor Limited | Semiconductor device and method for manufacturing the same |
| CN101266975B (en) * | 2007-03-16 | 2011-04-06 | 富士通半导体股份有限公司 | Semiconductor device and method for manufacturing the same |
| US8258040B2 (en) | 2007-03-16 | 2012-09-04 | Fujitsu Semiconductor Limited | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0012982D0 (en) | 2000-07-19 |
| GB2352328A (en) | 2001-01-24 |
| JP2000340645A (en) | 2000-12-08 |
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