CN1274850A - Integrated circuit having frequency division operation testing function - Google Patents
Integrated circuit having frequency division operation testing function Download PDFInfo
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- CN1274850A CN1274850A CN 00108972 CN00108972A CN1274850A CN 1274850 A CN1274850 A CN 1274850A CN 00108972 CN00108972 CN 00108972 CN 00108972 A CN00108972 A CN 00108972A CN 1274850 A CN1274850 A CN 1274850A
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Abstract
When a reset terminal 6 is separate off from the exterior input source to input a clock pulse to a clock input terminal 1, the first frequency dividing circuit 2 changes the a first frequency of the clock pulse to lower frequency and transmittes the pulse signal to the reset terminal 6 via a signal control circuit 5.An operation of the first frequency dividing circuit 2 is confirmed from the pulse signal of the reset terminal 6. When a second dividing circuit 3 is tested, the clock pulse input to the clock input terminal 1 is stopped after an 'H' signal is supplied once to the reset terminal 6.
Description
The present invention relates to a kind of integrated circuit with frequency division operation testing function.
One with the multifrequency frequency divider source signal from a frequency transformation to the integrated circuit of lower frequency, need to carry out a kind of test usually always, whether correctly work to determine frequency divider, thereby satisfy the requirement of high precision and reliability.Disclose a kind of integrated circuit with frequency division operation testing function in the Japanese patent publication number 52214/1995, this is a known embodiment can easily carrying out this class testing.Be described in disclosed measuring technology in this patent briefly below with reference to Fig. 4.
At first, by an input reset terminal R being connected to a power supply potential, resetting one integrated circuit with first, second and tri-frequency divider 101,102 and 103.Then, quicken time clock to one and be input to reset terminal R, so that end resetting of tri-frequency divider 103 when resetting applying to first frequency divider 101.Integrated circuit carries out a test, with determine second and tri-frequency divider 101,103 whether just in operate as normal.A favorable characteristics of this integrated circuit is that its configuration is simple, because can test with reset terminal.
Yet, this integrated circuit second and tri-frequency divider 102,103 utilize the test of the output of tri-frequency divider 103 when working.Like this, integrated circuit has a problem: it can not carry out the work test of first frequency divider 101.In order to express this problem in more detail, if all divider circuit be divided into one the preceding level and one after level, then can only test than after level, this is inconvenient.
In addition, when hope gives an additional function to said integrated circuit, for example during warning function, just must be provided for the additional control end of this function, thereby strengthen chip size and increase production cost.
In view of the foregoing, one object of the present invention is to provide a kind of integrated circuit, and it can test its first frequency divider can test its second frequency divider again, and without any need for additional test lead.
In one aspect of the invention, a kind of integrated circuit with frequency division operation testing function comprises a clock pulse input terminal, can be from the outside to one first clock pulse signal of this input end input; One first frequency divider, it transforms to a lower frequency to first clock pulse signal from its original frequency; A reset terminal can be from the outside to signal and second clock pulse signal of an expectation of this reset terminal input; A signal control circuit, it is contained between the first frequency divider output terminal and the reset terminal, be used to forbid that an external input signal to reset terminal is sent to the output terminal of first frequency divider, and a signal that is equivalent to first output signal of frequency divider is outputed to reset terminal; A selector switch, it or select the output signal of first frequency divider, perhaps choose the input signal of reset terminal output usefulness; One second frequency divider, it transforms to a lower frequency to the output signal of above-mentioned selector switch from its original frequency; Identify circuit for one, it exports a signal specific when above-mentioned wanted signal is input to reset terminal; With a latch circuit, when it is in a kind of level of expectation at first clock pulse signal that is input to input end of clock, keep to identify the output state of circuit, wherein second frequency divider above-mentioned wanted signal is input to reset terminal during proceed to reset; Wherein selector switch latch circuit keep above-mentioned signal specific during select and export a signal that will be input to input end of clock, and latch circuit keep a signal that is different from above-mentioned signal specific during select and export the output signal of first frequency divider; And wherein when one of selector switch selection will be input to the signal of input end of clock, the second clock pulse signal is input to reset terminal from outside.
So the integrated circuit of configuration can be tested first and second frequency dividers individually, and without any need for additional test lead.This just might reduce the chip area of integrated circuit and reduce its cost.At last, for the problems referred to above of prior art, promptly Chang Gui integrated circuit be merely able to test whole frequency dividing circuit after level, the invention provides a solution.
In another aspect of the present invention, a kind of integrated circuit with frequency division operation testing function comprises a clock pulse input terminal, can be from the outside to clock pulse signal of this input end input; One first frequency divider, it transforms to a lower frequency to first clock pulse signal from its original frequency; A reset terminal can be from the outside to this reset terminal input one first signal, a secondary signal and a second clock pulse signal; A signal control circuit, it is contained between the first frequency divider output terminal and the reset terminal, be used to forbid an output terminal transmission of arriving the external input signal of reset terminal, and a signal that is equivalent to first output signal of frequency divider is transmitted towards reset terminal towards first frequency divider; A selector switch, it or select the output signal of first frequency divider, perhaps choose the input signal of reset terminal output usefulness; One second frequency divider, it transforms to a lower frequency to the output signal of above-mentioned selector switch from its original frequency; Identify circuit for one, it has one first output terminal and one second output terminal, and when first signal was input to reset terminal, first output terminal was exported the 3rd signal, and when secondary signal was input to reset terminal, second output terminal was exported the 4th signal; A latch circuit when it is in a kind of level of expectation at first clock pulse signal that is input to input end of clock, keeps the output state of first output terminal; With a functional circuit, it carries out the operation of an expectation when output the 4th signal, and wherein second frequency divider is proceeded to reset during input first signal; Wherein selector switch latch circuit keep the 3rd signal during select and export a signal that will be input to input end of clock, and latch circuit keep a signal that is different from the 3rd signal during select and export the output signal of first frequency divider; And wherein when one of selector switch selection will be input to the signal of input end of clock, the second clock pulse signal is input to reset terminal from outside.
This integrated circuit also solves the problems referred to above of prior art.In addition, even when the functional circuit that is used to carry out desired operation to adds this integrated circuit to, also do not need to be provided for the additional control end of functional circuit.Thereby might reduce the chip area of integrated circuit and reduce its cost.
Of the present invention aspect another, signal control circuit be one by an impact damper and the series circuit that resistor is formed, the input side of impact damper is connected to the output terminal of first frequency divider, one end of resistor is connected to the outgoing side of impact damper, and the other end of resistor is connected to reset terminal.
The integrated circuit of Gou Chenging also solves the problems referred to above of prior art like this.In addition, this makes that the output might make first frequency divider can be owing to the adverse effect that is subjected to a kind of state of the signal that will be input to reset terminal simple in structure.
Fig. 1 is a calcspar, and an integrated circuit is described in accordance with a preferred embodiment of the present invention;
Fig. 2 is a sequential chart, is used for the operation of the integrated circuit of key diagram 1;
Fig. 3 also is a sequential chart, is used for the operation of the integrated circuit of key diagram 1; With
Fig. 4 is a calcspar, and the configuration of a custom circuit is described.
With reference to the accompanying drawings, a specific embodiment of the present invention is described.
In Fig. 1, clock pulse input terminal 1 can be imported a time clock as first clock pulse signal.For example, this time clock is fed from an external crystal oscillator.
First frequency divider 2 and second frequency divider 3 are to operate at the place of smearing of input pulse, and second frequency divider 3 sends to its output the output terminal 4 of frequency divider.In this embodiment, the divide ratio of first frequency divider 2 and second frequency divider 3 can proportionately change.In addition, these frequency dividers 2,3 can be a kind of in its type of the forward position place starting of input pulse separately.
Signal control circuit 5 is made up of an impact damper 51 and a resistor 52.Resistor 52 has enough big resistance, connects with impact damper 51.The input side of impact damper 51 is connected to the output terminal F1 of first frequency divider 2, and an end of resistor 52 is connected to the outgoing side of impact damper 51, and the other end of resistor 52 is connected to reset terminal 6.In this circuit arrangement, the output of first frequency divider 2 is sent to reset terminal 6, as the output of impact damper 51.This means, a signal that is equivalent to the output of first frequency divider 2 from signal control circuit 5 reset terminal 6 of feeding.Yet, do not allow a external input signal to be sent to the output terminal F1 of first frequency divider 2 to reset terminal 6 owing to the existence of impact damper 51.This makes the output that might make first frequency divider 2 can not be subjected to an adverse effect to the input signal of reset terminal 6.Because resistor 52 has enough big resistance value, so might send to an evaluation circuit 7 to " H " and " L " input that will be input to reset terminal 6 by a circuit with enough small resistor values, identifying that circuit 7 has provides the priority ranking that these " H " and " L " import in the output of first frequency divider 2, as following detailed description.Thereby might send to input signal with a kind of reliable mode and identify circuit 7, thereby improve the evaluation degree of accuracy of identifying circuit 7 fully greatly by the resistance value that makes resistor 52 to reset terminal 6.
Identify the state of circuit 7, detect the situation of reset terminal 6 according to the signal of importing from signal control circuit 5.In this embodiment, identify whether circuit 7 evaluation first signals and wanted signal are imported into reset terminal 6, this wanted signal perhaps continues one section " L " mutually of the same period signal (hereinafter being called secondary signal) as one as " H " signal (hereinafter being called first signal) that continues one section designated period of time (it is longer than the pulse width of the output pulse of first frequency divider 2).When identifying that circuit 7 identifies that first signal is imported into reset terminal 6, evaluation circuit 7 is just exported " H " signal as the 3rd signal from its first output terminal 71, and when identifying that circuit 7 identifies that secondary signal is imported into reset terminal 6, evaluation circuit 7 is just exported " H " signal as the 4th signal from its second output terminal 72.When first or secondary signal when not being input to reset terminal 6, identify circuit 7 just neither from first output terminal 71 again from second output terminal, 72 output " H " signals, but send " L " signal.Like this, for the evaluation circuit 7 of present embodiment, can use the circuit that can determine following item: which input is a current effective in these three possible inputs, promptly, be that first signal is transfused to, secondary signal is transfused to, still first or secondary signal be not transfused to.
Latch circuit 8 be at input signal from input end of clock 1 expectation level during when " L " signal (in having a present embodiment), keep identifying the output state of first output terminal 71 of circuit 7.On the other hand, the period that can make latch circuit 8 keep the output state of first output terminal 71, the period that to become an input signal from input end of clock 1 be " H " signal.
The selector switch 9 that provides as switchgear is according to the output of latch circuit 8, selects and exports one from the input of first frequency divider 2 or from the input of reset terminal 6.
A warning circuit 10 that is used as functional circuit begins operation according to the output from second output terminal 72 of identifying circuit 7; Use produces the output of reporting to the police from the output of first and second frequency dividers 2,3; With it is transported to a warning output terminal 11.Can revised version embodiment, make warning circuit 10 not use output from first and second frequency dividers 2,3.
In this embodiment, input end of clock 1, the first frequency divider 2, the second frequency dividers 3, frequency divider output terminal 4, signal control circuit 5, reset terminal 6 is identified circuit 7, latch circuit 8, selector switch 9, warning circuit 10 and warning output terminal 11 are assembled into an independent integrated circuit.
Referring now to Fig. 2 and 3, the operation of this integrated circuit is described.
At first, operation under the normal condition is discussed with reference to Fig. 2, CK wherein, F1, R, RH, SEL, F2 and O be the CK shown in the presentation graphs 1 respectively, F1, R, RH, SEL, the voltage waveform of F2 and O end.
Under normal operating condition, the external clock pulse shown in waveform CK among Fig. 2 is imported into input end of clock 1.First frequency divider 2 is transformed into lower frequency to this time clock from its original frequency, and provides the output shown in waveform F1 among the figure at output terminal F1.When reset terminal 6 separated with its outside input source under these conditions, the output of first frequency divider 2 just was sent to reset terminal 6 by signal control circuit 5; As a result, reset terminal 6 is just exported a signal shown in waveform R among Fig. 2, and this is consistent with the output of first frequency divider 2.Like this, might under normal operating condition, carry out the operational testing of one first frequency divider 2 by checking the signal of feeding from reset terminal 6.
Because reset terminal 6 separates with its outside input under these conditions, so be the output of impact damper 51 to the input signal of evaluation circuit 7, this is consistent with the output of first frequency divider 2.Thereby with waveform RH among Fig. 2, " L " state shown in the RL keeps identifying two output terminals 71,72 of circuit 7.Therefore, the output that keeps latch circuit 8 with " L " state shown in the waveform SEL among Fig. 2.If provide this " L " input, then selector switch 9 is selected and is exported from the output shown in the waveform F2 among Fig. 2 of first frequency divider 2.Thereafter, second frequency divider 3 transforms to a lower frequency to the output of first frequency divider 2 from its original frequency, and the output of gained frequency divider is sent to frequency divider output terminal 4.
As mentioned above, might use the signal of feeding from reset terminal 6 to carry out the operational testing of first frequency divider 2 under normal operating condition, wherein: external clock pulse is imported into input end of clock 1, and reset terminal 6 separates with its outside input source.In addition, might export at the frequency divider that frequency divider output terminal 4 obtains being produced by first frequency divider 2 and second frequency divider 3 from the time clock that is input to clock pulse input terminal 1.In a word, might under normal operating condition, obtain the frequency divider output of comfortable frequency divider output terminal 4.
Referring now to Fig. 3, a kind of reset operation is described.When carrying out reset operation, from outside first signal (" H " level) is input to reset terminal 6, make it remain on " H " state shown in the waveform R among Fig. 3.Make a pulse width of being longer than the time clock that is input to clock pulse input terminal 1 period that reset terminal 6 is remained on " H " state.At this, provide " H " signal that to import reset terminal 6 from the outside by a circuit with enough small resistor values.As previously mentioned, make the resistance value of resistor 52 in the signal control circuit 5 fully big.In two signals that are imported in the signal control circuit 5, the i.e. signal of externally importing from reset terminal 6 and from the signal that first frequency divider 2 is fed, which signal priority is identified in the circuit 7 with being input in another signal, is to have less resistance value according to which circuit in the supply circuit of two signals to determine.In this embodiment, give " H " signal priority ranking, this signal is externally to import from reset terminal 6 by a circuit with enough small resistor values, thereby it is supplied with evaluation circuit 7.If provide this input signal, identify that then circuit 7 provides " H " signal at first output terminal 71.When the time clock from clock pulse input terminal 1 input rested on Fig. 3 " L " state shown in the waveform SEL, latch circuit 8 kept " H " signal of feeding from first output terminal 71.When the output of latch circuit 8 became " H " state, selector switch 9 selected to pass through " H " signal of signal control circuit 5 inputs, and it is outputed to second frequency divider 3.In addition, by " H " signal of feeding from first output terminal 71, second frequency divider 3 resets.As mentioned above because first signal (" H ") is input to from the outside reset terminal 6 during second frequency divider 3 that continues to reset, so keep output with " L " level during this period from frequency divider output terminal 4.
When hope cancellation reset operation, should eliminate " H " level signal that is input to reset terminal 6 from the outside.When doing like this, identify that first output terminal 71 of circuit 7 changes to " L " from " H ", and second frequency divider 3 resets no longer.After this, integrated circuit carries out aforesaid operations under normal operation.
Refer again to Fig. 3, the test of second frequency divider 3 is described below.When carrying out this test operation, an outside " H " signal is imported into reset terminal 6, so that with aforesaid way second frequency divider 3 that resets, remains to the input signal of clock pulse input terminal 1 then with " L " state.When an external clock pulse is imported into reset terminal 6 with when the second clock pulse signal, identify that circuit 7 stops to provide " H " signal to first output terminal 71, and first output terminal 71 is arranged to " L " state.As a result, cancel resetting of second frequency divider 3.Because at this moment there is not time clock to be input to clock pulse input terminal 1, so latch circuit 8 keeps " H " state, so that selector switch 9 continues to select to pass through the signal of signal control circuit 5 inputs.Like this, second frequency divider 3 receives the external clock pulse that is imported into reset terminal 6, and, because this external clock pulse begins operation.So it delivers to frequency divider output terminal 4 to the output of frequency divider.Thereby might carry out the operational testing of second frequency divider 3 by at this moment checking its output.
When one " L " when signal is input to reset terminal 6, is just delivered to it and identify circuit 7, make it produce " H " signal at second output terminal 72 one period greater than the pulse width of the time clock that will be input to clock pulse input terminal 1.This output that warning circuit 10 uses from second output terminal 72 begins operation, and warning output terminal 11 is delivered in the output of reporting to the police.
As mentioned above, because first half-sum of the divider circuit of being made up of first frequency divider 2 and second frequency divider 3 the second half can be tested fully independently of one another, so might reduce test required time and cost.Also might reduce the physical size of integrated circuit,, and not increase the number of its control end because it can control its warning function.
In the integrated circuit of present embodiment, though with " H " state hold reset end 6 time, carry out reset operation, the output of with " L " state hold reset end 6 time, produce reporting to the police, but the setting that can put upside down " H " and " L ", perhaps revised version embodiment suitably in other cases.
In addition,, the invention is not restricted to this, also can when suitable, adopt other forms of functional circuit though above-mentioned integrated circuit comprises the warning circuit 10 as functional circuit.For example, a circuit that the frequency or the working cycle of the output of the frequency divider that provides at frequency divider output terminal 4 under normal operating condition are changed can be provided integrated circuit.
Claims (3)
1. integrated circuit with frequency division operation testing function, described integrated circuit comprises:
A clock pulse input terminal can be to it from one first clock pulse signal of outside input;
One first frequency divider, it can transform to lower frequency to first clock pulse signal from its original frequency;
A reset terminal can be to it from an outside wanted signal of input and a second clock pulse signal;
A signal control circuit, it is loaded between described first frequency divider output terminal and the described reset terminal, so that forbid that an external input signal to described reset terminal is sent to the output terminal of described first frequency divider and so that towards signal of described reset terminal output corresponding to described first output signal of frequency divider;
A selector switch, it or select the output signal of described first frequency divider, perhaps choose the input signal for output usefulness of described reset terminal;
One second frequency divider, it transforms to lower frequency to the output signal of described selector switch from its original frequency;
Identify circuit for one, it exports a signal specific when described wanted signal is input to described reset terminal; With
A latch circuit when it is in an expectation level at first clock pulse signal that is input to described clock pulse input terminal, keeps the output state of described evaluation circuit;
Wherein said second frequency divider one described wanted signal is input to described reset terminal during continue to be reset;
When wherein said selector switch keeps described signal specific at described latch circuit, select and export a signal that will be input to described clock pulse input terminal, and when described selector switch is different from the signal of described signal specific one of described latch circuit maintenance, select and export the output signal of described first frequency divider; With
Wherein when described selector switch is selected to be input to the signal of described clock pulse input terminal, the second clock pulse signal is input to described reset terminal from outside.
2. integrated circuit with frequency division operation testing function, described integrated circuit comprises:
A clock pulse input terminal can be to it from one first clock pulse signal of outside input;
One first frequency divider, it can transform to lower frequency to first clock pulse signal from its original frequency;
A reset terminal can be to it from outside input one first signal, a secondary signal and a second clock pulse signal;
A signal control circuit, it is loaded between described first frequency divider output terminal and the described reset terminal, so that forbid that an external input signal that arrives described reset terminal is towards the output terminal transmission of described first frequency divider with so that towards signal corresponding to described first output signal of frequency divider of described reset terminal output;
A selector switch, it or select the output signal of described first frequency divider, perhaps choose the input signal for output usefulness of described reset terminal;
One second frequency divider, it transforms to lower frequency to the output signal of described selector switch from its original frequency;
Identify circuit for one, have first output terminal of one the 3rd signal of output when described first signal is input to described reset terminal and second output terminal of one the 4th signal of output when described secondary signal is input to described reset terminal;
A latch circuit when it is in an expectation level at first clock pulse signal that is input to described clock pulse input terminal, keeps the output state of described first output terminal; With
A functional circuit, it carries out the operation of an expectation when described the 4th signal of output;
Wherein said second frequency divider continues to be reset during described first signal of input;
Wherein said selector switch a described latch circuit keep described the 3rd signal during select and export a signal that will be input to described clock pulse input terminal, and described selector switch a described latch circuit keep a signal that is different from described the 3rd signal during select and export the output signal of described first frequency divider; With
Wherein select the cycle that will be input to the signal of described clock pulse input terminal, the second clock pulse signal is input to described reset terminal from outside at described selector switch.
3. integrated circuit according to claim 1 or 2 with frequency division operation testing function, wherein said signal control circuit be one by an impact damper and the series circuit that resistor forms, an input side of described impact damper is connected to the output terminal of described first frequency divider, one end of described resistor is connected to the outgoing side of described impact damper and the other end of described resistor is connected to described reset terminal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14511199A JP3482156B2 (en) | 1999-05-25 | 1999-05-25 | Integrated circuit with frequency division test function |
| JP145111/1999 | 1999-05-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1274850A true CN1274850A (en) | 2000-11-29 |
| CN1129007C CN1129007C (en) | 2003-11-26 |
Family
ID=15377651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 00108972 Expired - Fee Related CN1129007C (en) | 1999-05-25 | 2000-05-24 | Integrated circuit having frequency division operation testing function |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP3482156B2 (en) |
| CN (1) | CN1129007C (en) |
| HK (1) | HK1031428A1 (en) |
| TW (1) | TW493082B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106168751A (en) * | 2015-05-18 | 2016-11-30 | 精工电子有限公司 | Frequency dividing circuit, the control method of frequency dividing circuit and analog electronic clock |
| CN106990347A (en) * | 2017-03-22 | 2017-07-28 | 中国电子科技集团公司第五十五研究所 | Suitable for the On-wafer measurement system and method for testing of millimeter wave divider |
| CN112631114A (en) * | 2019-09-24 | 2021-04-09 | 精工爱普生株式会社 | Circuit device, physical quantity measuring device, electronic apparatus, and moving object |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011112447A (en) * | 2009-11-25 | 2011-06-09 | Tdk Corp | Sweep oscillation circuit and powder sensor |
-
1999
- 1999-05-25 JP JP14511199A patent/JP3482156B2/en not_active Expired - Fee Related
-
2000
- 2000-04-14 TW TW89107020A patent/TW493082B/en not_active IP Right Cessation
- 2000-05-24 CN CN 00108972 patent/CN1129007C/en not_active Expired - Fee Related
-
2001
- 2001-03-26 HK HK01102153A patent/HK1031428A1/en not_active IP Right Cessation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106168751A (en) * | 2015-05-18 | 2016-11-30 | 精工电子有限公司 | Frequency dividing circuit, the control method of frequency dividing circuit and analog electronic clock |
| CN106168751B (en) * | 2015-05-18 | 2019-11-26 | 精工电子有限公司 | Frequency dividing circuit, the control method of frequency dividing circuit and analog electronic clock |
| CN106990347A (en) * | 2017-03-22 | 2017-07-28 | 中国电子科技集团公司第五十五研究所 | Suitable for the On-wafer measurement system and method for testing of millimeter wave divider |
| CN112631114A (en) * | 2019-09-24 | 2021-04-09 | 精工爱普生株式会社 | Circuit device, physical quantity measuring device, electronic apparatus, and moving object |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3482156B2 (en) | 2003-12-22 |
| CN1129007C (en) | 2003-11-26 |
| JP2000338186A (en) | 2000-12-08 |
| TW493082B (en) | 2002-07-01 |
| HK1031428A1 (en) | 2001-06-15 |
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