CN1265433C - Preparation method of silicon material on thick membrane graphic insulator - Google Patents
Preparation method of silicon material on thick membrane graphic insulator Download PDFInfo
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- CN1265433C CN1265433C CN 03141886 CN03141886A CN1265433C CN 1265433 C CN1265433 C CN 1265433C CN 03141886 CN03141886 CN 03141886 CN 03141886 A CN03141886 A CN 03141886A CN 1265433 C CN1265433 C CN 1265433C
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- silicon
- thin film
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Abstract
The present invention relates to a preparation method of a thick film pattern SOI material. An SIMOX technique is firstly adopted to inject oxygen for separation in film forming to form a thin film pattern SOI material. The present invention is characterized in that a CVD vapor phase epitaxy method is used for forming epitaxially one of a monocrystal silicon thin film germanium silicon thin film or a gallium arsenide thin film on the surface layer of a substrate, or monocrystal silicon continues to be extrapolated on the germanium silicon thin film to form a strained silicon structure. The present invention specifically comprises four steps: (1) photolithography of a mask for blocking ion implantation on a silicon base; (2) ion implantation, (3) high temperature annealing, (4) epitaxial growth of one of the monocrystal silicon thin film, the germanium silicon thin film or the gallium arsenide thin film by CVD. The thickness of an epitaxial layer is regulated by deposition rate, and the thickness is from 0.7 to 50 mum. The thick film pattern SOI material prepared by the present invention provides substrate materials for the integration of MEMS and MOEMS.
Description
Technical field
The present invention proposes silicon (SOI) preparation methods on a kind of thick film pattern dielectric body,, belong to microelectronics technology for microelectromechanical systems (MEMS) and the integrated backing material that provides of low-light electronic mechanical system (MOEMS).
Background technology
Silicon integrated circuit manufacturing process in the microelectric technique is highly integrated and technology high mature.Under the drive of microelectric technique, in order to combine with the silicon integrated circuit manufacturing process, the silicon-base micro-mechanical process technology, silica-based integrated optics has all obtained develop rapidly, and combines with silica-based microelectric technique and to have formed MEMS and MOEMS technology.Carry out MOEMS integrated on silicon substrate is the target that people pursue always.
In recent years, along with very lagre scale integrated circuit (VLSIC) (VLSI) industrial expansion, the SOI technology is because its unique advantages demonstrates more and more important effect.The SOI material also has important use in MEMS and silica-based optics except being used widely in low-voltage and low-power dissipation, anti-irradiation, integrated circuit such as high temperature resistant.But not all device can or be fit to be manufactured on the SOI substrate, wants good heat dissipation and high pressure resistant as high power device, is more suitable for being manufactured on the silicon body region territory.That is that all right is ripe for some device or the circuit manufacturing process on the SOI substrate, as radio circuit, dynamic random access memory (DRAM) etc., also can temporarily be manufactured on the silicon body region territory at present.In addition, for silica-based optics such as fiber waveguide, optical scanner, optical switch etc. to be manufactured on just need top layer silicon on the SOI substrate thickness at least more than 5 μ m.For most of MEMS devices, the top layer silicon of SOI material also needs thicker.Integrated in order to realize MEMS and MOEMS, make full use of the advantage of dissimilar devices, the patterned SOI material of thick film (＞1 μ m) is in demand.
The mainstream technology of preparation SOI material mainly contains two kinds at present: wafer bonding and notes oxygen are isolated (J.P.Colinge, Silicon-On-Insulator Technology:Materials to VLSI, 2nd Edition, Boston:Kluwer, 1997.).Bonding techniques can prepare buries SiO
2Layer (abbreviation buries oxygen) or all very thick SOI material of top layer silicon.But the wafer bonding technology is not suitable for preparing graphical SOI material, because can't accurately aim at during bonding, especially in deep-submicron and nanometer range.Need chemico-mechanical polishing (CMP) attenuate behind the bonding simultaneously, this is also very complicated on technology.Annotating oxygen isolation (SIMOX) technology is that big line high-energy oxonium ion directly is injected in the silicon chip, carries out the quality that high annealing produces oxygen buried layer and recovers top layer silicon then.The SIMOX technology has only ion to inject and two key steps of high annealing, and technology is simple, and is compatible mutually with VLSI technology fully.Can accurately control by energy of ions owing to inject the degree of depth of ion, so the thickness of top layer silicon is very even.SIMOX is particularly suitable for preparing graphical SOI material, because as long as stop the oxonium ion of injection fully with enough thick mask in needed silicon body region territory.Compare with wafer bonding technology, body silicon and SOI zone can very accurately be controlled by mask, reach deep-submicron even nanometer scale.But, the SIMOX technology has also that a very big shortcoming---top layer silicon is very thin, generally can not surpass 400nm (S.Bagchi, S.J.Krause, P.Roitman, Dose dependence of microstructural developmentof buried oxide in oxygen implanted silicon-on-insulator material, Applied Physics Letters, 71 (15), 1997, pp.2136-2138.).
The deficiency for preparing the graphical SOI material of thick film in view of above two kinds of methods, so produce a new design: after adopting SIMOX prepared film pattern SOI material, by other technology, obtain the graphical SOI material of thick film of adequate thickness as epitaxy technique, satisfying the integrated needs of MEMS and MOEMS, thereby draw purpose of the present invention.
Summary of the invention
In order to overcome the difficult point that exists in the prior art, the present invention proposes the graphical SOI preparation methods of a kind of thick film, it is characterized in that adopting earlier the SIMOX technology in body silicon, to annotate oxygen and isolate formation film pattern SOI material; Adopt the chemical vapor deposition (CVD) method to continue the vapor phase epitaxial growth method then and form a kind of in monocrystalline silicon thin film, germanium-silicon thin membrane or the gallium arsenide film on the top layer of substrate; Or on the germanium-silicon thin membrane of extension, continue epitaxial growth monocrystalline silicon to form the structure of strained silicon; The thickness of CVD gas-phase epitaxial layer is 0.7～50 μ m.
Concrete processing step of the present invention is as follows: (1) mask (2) ion that the photoetching blocks ions is injected on silicon substrate injects; (3) high annealing; (4) a kind of in CVD epitaxial growth monocrystalline silicon thin film, germanium-silicon thin membrane or the gallium arsenide film.
For the oxonium ion that injects being stopped fully, must cover enough thick mask in needed silicon body region territory in needed silicon body region territory.Because substrate need be than higher temperature when ion injected, and it is very high to inject the dosage of ion, so can not directly adopt photoresist to make mask.Mask in the step (1) can be SiO
2, Si
3N
4, ganoine thin films such as polysilicon or metal, first-selected mask is the SiO of thermal oxidation
2Film.The thickness of mask should be enough thick, and the mask that 200～800nm is thick can correspondingly stop the oxonium ion of 30～200keV.The photoetching of mask adopts conventional optical exposure and reactive ion etching (RIE) technology to get final product.
It is the key that forms high quality graphics SOI material that oxonium ion in the step (2) injects.Because the quality and the injection parameter of SIMOX SOI material have much relations.When injecting, the dosage and the energy of substrate temperature, injection ion are the parameters of three keys.For fear of the decrystallized of top layer monocrystalline silicon and dynamically annealing, substrate will keep higher temperature during injection, is generally 400～700 ℃.The energy that oxonium ion injects is 30～200keV, and dosage is 1.0 * 10
17～2.0 * 10
18Cm
-2Inject because the graphical SOI material of SIMOX is the oxonium ion part, the conventional high dose oxonium ion that injects forms SiO in annealing process
2Shi Tiji can expand 2.25 times, and therefore the transitional region at SOI and body silicon will produce a large amount of defectives, extends 2～3 μ m; Cause simultaneously silicon face have very big difference in height (S.Bagchi, Y.Yu, M.Mendicino, et al., Defect analysis of patterned SOI material, IEEEInternational SOI Conference, 1999, pp.121-122.).This graphical SOI material of high dose SIMOX that comprises a large amount of defectives and very big difference in height in the monocrystalline silicon of top layer is unfavorable for back CVD epitaxial monocrystalline silicon.In order to obtain high-quality graphical SOI material, the ion of injection must be a low dosage.Different with the high dose SIMOX of routine, low dosage SIMOX material does not have stoicheiometry when injecting the oxygen that buries forms, and just forms a large amount of oxygen precipitations.In annealing process, the oxygen of injection and pasc reaction generate SiO
2, the SiO of generation
2In order to obtain the volume that enough spaces hold expansion, a large amount of silicon atoms is discharged to formation silicon gap in the silicon crystal lattice.Because being infused in not form when injecting, low dosage buries oxygen, so gap of these silicon can be moved to silicon face at an easy rate, and at surface formation epitaxial loayer (J.Margail, J.Stoemenos, C.Jaussaud, et al., Reduced defectdensity in silicon-on-insulator structures formed by oxygenimplantation in two steps, Applied Physics Letters, 54 (6), 1989, pp.526-528.).So,, need to adopt low dosage SIMOX technology in order to obtain the graphical SOI material of low defective and surfacing.The reduction of dosage needs the also corresponding reduction of energy, otherwise can't form continuous oxygen buried layer, dosage and energy have one to optimize relation (M.Chen, X.Wang, J.Chen, etal., Does-energy match for the formation of high-integrity buriedoxide layers in low-dose separation-by-implantation-of-oxygenmaterials, Applied Physics Letters, 80 (3), 2002, pp.880-882.).When ion energy E was 30～200keV scope, corresponding low dosage D scope was 1.5～7.0 * 10
17Cm
-2, be formulated as: D (10
17Cm
-2)=(0.035 ± 0.005) * E (keV).
The ion that injects in the step (2) removes O
+Can also be outward O
2 +, HO
+, H
2O
+, N
+, N
2 +Deng containing oxygen or nitrogenous ion to form SiO
2Or Si
3N
4Buried regions.
Finish ion and inject and remove after the mask, the silicon chip of injection need carry out the high annealing of step (3).The temperature of annealing is 1200～1375 ℃, and annealing time is 1～24 hour, and annealing atmosphere is Ar or N
2With O
2Mist, O wherein
2Volume content can be 0.1%～20%.
Adopt the low dosage oxonium ion of optimizing to inject and high annealing, the graphical SOI material that is obtained is high-quality.Be in particular in: the oxygen that buries in SOI zone is highly complete, and the density of silicon island and pin hole is very low; Body silicon and SOI transition region are less than 100nm, and defect concentration is lower than 10
5Cm
-2The surface is also very smooth, and the difference in height between body silicon and the SOI zone is less than 5nm.
CVD silicon epitaxy technology is a technology very ripe in the semi-conductor industry, and its advantage is that equipment is simple, and extension speed is fast, and epitaxial loayer monocrystalline quality height can be produced in batches.The technology of step of the present invention (4) adopts CVD method epitaxial monocrystalline silicon exactly, forms enough thick graphical SOI material to satisfy the integrated needs of MEMS and MOEMS.Before the extension, graphical SOI substrate is removed the SiO that oxidation generates in the annealing process with the HF solution of dilution
2After substrate put into the epitaxial furnace reative cell, feed H at 1000～1200 ℃
2Toasted 0.5～2 hour, can remove the natural oxidizing layer of substrate surface, and improve the roughness of substrate surface, make surface more smooth (N.Sato, T.Yonehara, Hydrogen annealedsilicon-on-insulator, Applied Physics Letters, 65 (15), 1994, pp.1924-1926.).Can adopt SiCl during epitaxial growth
4, SiHCl
3, SiH
2Cl
2Or SiH
4As the silicon source, concrete course of reaction is as follows respectively:
Preferred silicon source is SiCl
4, because this is industrial with the most use and study at most the silicon source.Can import dopant during epitaxial growth simultaneously to prepare dissimilar epitaxial loayer (n type, p type or intrinsic).N type dopant commonly used is B
2H
6, p type dopant is PH
3Or AsH
3Use H
2Mix with dopant as diluent, and regulate doping content by the control flow.The thickness of epitaxial monocrystalline silicon can be controlled by deposition rate, and deposition rate can be regulated in 0.2～1 μ m/min scope.The thickness of epitaxial loayer can be regulated arbitrarily in 0.7～50 mu m range.
CVD epitaxy technique in the step (4) is a broad sense, and the film of institute's extension is monocrystalline silicon, germanium silicon (SiGe) film, GaAs (GaAs) film or their plural layers.For example, the epitaxy Si Ge of elder generation film, on the SiGe film of institute's extension, continue epitaxial monocrystalline silicon then to form structure (Device structure and electrical characteristics ofstrained-Si-on-insulator (strained-SOI) MOSFETs, S.Takagi, the N.Sugiyama of strained silicon, T.Mizuno, et al., Materials Science and Engineering B, 89,2002, pp.426-434.).
Method of the present invention is that SIMOX technology and CVD epitaxy technology are organically combined the graphical SOI material of preparation thick film.The thickness of the top layer silicon film of this graphical SOI material can be between 1～50 μ m be regulated arbitrarily, makes designs and manufacturing process that very big flexibility be arranged, and is very beneficial for MEMS and MOEMS is integrated.
Description of drawings
Fig. 1 is the combine processing step schematic diagram of the graphical SOI material of preparation thick film of SIMOX technology and CVD epitaxy technology.
(A) for making the schematic diagram behind the mask on the silicon chip by lithography;
(B) schematic diagram that injects for ion;
(C) be schematic diagram behind the high annealing;
(D) schematic diagram after the CVD silicon epitaxy.
Among the figure, 1 is monocrystalline substrate; 2 masks for the blocks ions injection; 3 is oxonium ion; 4 for being injected into the oxygen in the silicon substrate or the oxygen that buries of the back formation of annealing; 5 top layer silicon for SOI zone, annealing back; 6 is the CVD epitaxial loayer.
Embodiment
Following specific embodiment helps to understand the features and advantages of the present invention, but enforcement of the present invention never only is confined to following examples.
The SiO of thermal oxide growth 500nm on p type (100) monocrystalline silicon piece
2Film generates mask to stop the injection of oxonium ion in the photoetching of needed silicon body region territory.O
+The injection energy be 160keV, dosage is 5.5 * 10
17Cm
-2, substrate temperature is 680 ℃.Inject the back and float SiO with the HF solution that dilutes
2Mask.High annealing is at Ar+0.5%O
2Atmosphere in carry out, annealing temperature is 1300 ℃, anneals 5 hours.HF solution with dilution floats the SiO that generates in the annealing process
2And clean, in cylinder epitaxial furnace, carry out the extension of monocrystalline silicon.Use H before the extension
21180 ℃ of bakings 1.5 hours.Outer time-delay silicon source is SiCl
4, epitaxial temperature is 1180 ℃, epitaxial monocrystalline silicon under the deposition rate of 0.5 μ m/min, epitaxy layer thickness are 40 μ m.
Concrete steps and condition are with embodiment 1, and difference is that the thickness of epitaxial loayer is 1 μ m.
Concrete steps and condition are with embodiment 1, and difference is that the ion that injects is not O
+, but N
+
Concrete steps are with embodiment 1, and difference is that epitaxial loayer is not a monocrystalline silicon, but the SiGe alloy firm, thickness is 2 μ m, used silicon source is SiCl
4, the germanium source is GeCl
4
Concrete steps are with embodiment 4, and difference is on the SiGe alloy firm of institute's extension extension one deck monocrystalline silicon again, and thickness is 20nm, forms the structure of strained silicon.
Concrete steps are with embodiment 4, and difference is on the SiGe alloy firm of institute's extension extension one deck GaAs film again, and thickness is 200nm.Ga/AsCl can be adopted in outer time-delay Ga source and As source
3/ H
2System.
Claims (4)
1, the graphical SOI preparation methods of a kind of thick film, it is characterized in that adopting earlier the SIMOX technology in body silicon, to annotate oxygen and isolate formation film pattern SOI material, utilize CVD vapor phase epitaxial growth method to form a kind of in monocrystalline silicon thin film, germanium-silicon thin membrane or the gallium arsenide film on the top layer of substrate then, concrete technology is:
(1) mask that the photoetching blocks ions is injected on silicon substrate, mask is SiO
2, Si
3N
4, a kind of in polysilicon or the metallic film, its thickness is 200～800nm, to stop the oxonium ion of 30～200keV;
When (2) injecting, the energy of oxonium ion is 30～200keV, and dosage D is 1.0 * 10
17～2.0 * 10
18Cm
-2
(3) temperature of high annealing is 1200～1375 ℃, and annealing time is 1～24 hour, and annealing atmosphere is Ar or N
2With O
2Mist, O wherein
2Volume content can be 0.1%～20%;
(4) substrate is put into the epitaxial furnace reative cell, fed H at 1000～1200 ℃
2Toasted 0.5～2 hour; The epitaxial silicon source is SiCl
4, SiHCl
3, SiH
2Cl
2Or SiH
4In a kind of.
2,, it is characterized in that the ion that injects removes O by the graphical SOI preparation methods of the described thick film of claim 1
+Can also be outward O
2 +, HO
+, H
2O
+, N
+, N
2 +Contain a kind of in oxygen or the nitrogenous ion to form SiO
2Or Si
3N
4Buried regions.
3, by the graphical SOI preparation methods of the described thick film of claim 1, it is characterized in that epitaxial deposition speed is 0.2～1 μ m/min.
4, by the graphical SOI preparation methods of the described thick film of claim 1, the thickness that it is characterized in that the CVD gas-phase epitaxial layer is 0.7～50 μ m.
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|---|---|---|---|
| CN 03141886 CN1265433C (en) | 2003-07-29 | 2003-07-29 | Preparation method of silicon material on thick membrane graphic insulator |
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|---|---|---|---|
| CN 03141886 CN1265433C (en) | 2003-07-29 | 2003-07-29 | Preparation method of silicon material on thick membrane graphic insulator |
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| CN1265433C true CN1265433C (en) | 2006-07-19 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256949B (en) * | 2007-01-12 | 2010-09-29 | 国际商业机器公司 | Strained SOI substrate manufacture method and meth CMOS device on the substrate |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100336172C (en) * | 2004-12-22 | 2007-09-05 | 上海新傲科技有限公司 | Silicon-germanium material structure on insulator prepared through improved separation-by-implantation-of-oxygen technique and process thereof |
| US7651947B2 (en) | 2006-05-25 | 2010-01-26 | International Business Machines Corporation | Mask forming and implanting methods using implant stopping layer and mask so formed |
| CN102412124A (en) * | 2011-09-30 | 2012-04-11 | 上海晶盟硅材料有限公司 | Method for producing novel substrate, epitaxial wafer and semiconductor device |
| CN103219275B (en) * | 2012-01-19 | 2016-03-23 | 中国科学院上海微系统与信息技术研究所 | There is the preparation method of SGOI or sSOI of high relaxation and fabricating low-defect-density |
| CN102788556A (en) * | 2012-08-24 | 2012-11-21 | 中国电子科技集团公司第二十四研究所 | Method for measuring drift amount of buried graph after epitaxial growth |
| CN102980692B (en) * | 2012-11-19 | 2015-08-19 | 西安微纳传感器研究所有限公司 | Shock-resistant pressure transducer of a kind of high temperature and preparation method thereof |
| CN105043606B (en) * | 2015-07-10 | 2017-11-03 | 东南大学 | A kind of capacitance pressure transducer, and preparation method thereof |
-
2003
- 2003-07-29 CN CN 03141886 patent/CN1265433C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101256949B (en) * | 2007-01-12 | 2010-09-29 | 国际商业机器公司 | Strained SOI substrate manufacture method and meth CMOS device on the substrate |
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| CN1514472A (en) | 2004-07-21 |
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