CN1237794A - Semiconductor memory device equipped with access circuit for performing access control of flash memory - Google Patents
Semiconductor memory device equipped with access circuit for performing access control of flash memory Download PDFInfo
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- CN1237794A CN1237794A CN99107884A CN99107884A CN1237794A CN 1237794 A CN1237794 A CN 1237794A CN 99107884 A CN99107884 A CN 99107884A CN 99107884 A CN99107884 A CN 99107884A CN 1237794 A CN1237794 A CN 1237794A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000002800 charge carrier Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 claims description 3
- 230000005684 electric field Effects 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 239000002784 hot electron Substances 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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Abstract
Disclosed is a semiconductor memory device comprising a memory cell and a controller. In the memory cell capable of electrically writing-erasing data, the voltage applied between the drain and the well is lowered in withdrawing electrons from the floating gate. When electrons are withdrawn from the floating gate included in the memory cell, the controller serves to apply a voltage of -9V to the gate, a voltage of 6V to the drain, and a voltage of 0V to the back gate of a selected memory cell.
Description
The present invention relates to semiconductor memory, particularly have the semiconductor memory of the control circuit of the access control that is used to carry out flash memory.
In recent years, increasing to the demand of nonvolatile memory, this memory still can keep memory contents under the situation that power supply is turned off.The flash memory of the content that the unit in particularly, can the obliterated data piece is stored more and more attracts much attention.Different with common dynamic random access memory (DRAM) or static RAM (SRAM), flash memory requires to be different from supply voltage V
DdBe used to write or obliterated data with the voltage of ground voltage GND,, this voltage does not drop in the scope between supply voltage Vdd and ground voltage GND yet.
Open text No. puts down among the 6-150700 at Japan Patent, shows for example to be used to write in flash memory or the voltage of obliterated data.
In above-mentioned first prior art, 0V voltage (GND) puts in data and writes the fashionable control gate that links to each other with word line 149 shown in Fig. 9 A.And, write fashionablely in data, 20V voltage and GND put on drain electrode 145 and P-trap 143 respectively.At this moment, owing to, flow to drain electrode 145 by grid oxidation film 146, cause constituting the transistorized threshold value V of memory cell because the Fowler-Nordheim channel phenomenon is extracted electronics out from floating boom 147 in drain electrode 145 and 149 electrical potential differences that produce 20V of control gate
TmReduce.
On the contrary, when obliterated data, 20V voltage puts on control gate 149 shown in Fig. 9 B.And GND puts on source electrode 144 and P- trap 143, and 145 open circuits that drain.At this moment, because the electrical potential difference of the opposite 20V of the electrical potential difference direction that is produced when having produced,, make the threshold value V of memory cell because the Fowler-Nordheim channel phenomenon is injected into floating boom 147 from P-trap 143 by grid oxidation film 146 with write data
TmIncrease.
Figure 10 A and 10B show second prior art with erasing voltage write of relevant flash memory.
In second prior art, 10V voltage puts on control gate 149 when write data.And 6V voltage, GND and GND are applied to drain electrode 145, source electrode 144 and P-trap 143 respectively.At this moment, channel current 144 flow direction leakages 145 from the source.The electronics that forms channel current quickens by being added at P- trap 143 and 145 the high electric field of drain junction of draining, and forms hot electron.The electric field attracts that above-mentioned hot electron Be Controlled grid 149 and P-trap are 143 makes a part be injected into floating boom 147, makes the threshold value V of memory cell thus
TmIncrease.
When obliterated data ,-10V, 6V and 0V voltage are added on control gate 149, source electrode 144 and P-trap 143 respectively, and 145 open circuits that drain.At this moment, because extracting electronics out from control gate 149, the Fowler-Nordheim channel phenomenon flows to source electrode 144, result, threshold value V by grid oxidation film
TmReduce.
In first prior art, when write data, the high voltage of the 20V that is applied makes and the performance degradation of memory cell reduces reliability thus on trap and the drain electrode drain junction of asking.Because when write data, high electric field is added on the drain junction, so produced hot electron and hot hole.The hot hole of Chan Shenging is by high electric field attracts and be absorbed in oxide-film like this.As a result, the defective insulation as electric leakage one class takes place on gate insulating film, reliability is reduced.
And,, must use high voltage withstanding memory cell owing to when write data and obliterated data, all be added with high voltage.But, be difficult to make high voltage withstanding memory cell miniaturization.Should be noted that, in order to increase the withstand voltage of memory cell, source-leakage that must increase and the anti-avalanche voltage between the P-trap.So the impurity concentration in the P-trap must be lowered.But if the impurity concentration in the P-trap is lowered, depletion layer is probably from the drain junction expansion, and the result penetrates between source electrode and drain electrode probably.So in order to guarantee the high withstand voltage of memory cell, source electrode and drain electrode must fully separate mutually preventing and penetrate.Should be noted that also high voltage not only is added on memory cell but also is added on the peripheral circuit that is used to drive memory cell, this makes and must use high voltage withstanding element to form peripheral circuit.Naturally, be difficult to the same with memory cell minimizes peripheral circuit.
In second prior art, when carrying out write data, the channel current of milliampere level is allowed to flow through between source electrode and drain electrode, and causes big current drain.
In the integrated circuit of development recent years, microcomputer and flash memory are installed in on the chip piece, and 1.8 to 5 volts supply voltage boosts to produce high voltage by the booster circuit in chip.The high voltage of Chan Shenging is used to write and obliterated data like this.But the electric current deliverability of booster circuit is by the capacitance decision of electric capacity.Therefore, for big electric current stably is provided, must in chip, form electric capacity with millimeter level area.Clearly, it is unpractiaca forming big like this electric capacity in chip, because the size of chip itself is exactly millimetre-sized.In this case, consider nearest technology, must reduce write current to reduce power consumption to the trend that can develop by the direction of battery-driven flash memory.
First purpose of the present invention is to provide a kind of control circuit, and this circuit makes that using low withstand voltage memory cell to form flash memory becomes possibility.
Second purpose is to provide control circuit, and this circuit makes that reducing power consumption becomes possibility.
According to the invention provides a kind of semiconductor memory, comprising:
Memory cell, this memory cell comprises Semiconductor substrate, be formed on the trap of first conduction type in the described Semiconductor substrate, first and second zones of second conduction type that in described trap, forms, make channel region in the described first and second interregional formation, be formed on the described floating boom of stating above the channel region, this floating boom has and places first dielectric film that is used to accumulate charge carrier therebetween, with the control gate that is formed on the described floating boom, this control gate has second dielectric film that places therebetween;
Control circuit, this control circuit, is used for first voltage of first polarity is added on described control gate when described floating boom is extracted out at charge carrier, will be added on described first area with second voltage of first opposite polarity second polarity.
By when extracting charge carrier out, the voltage of opposed polarity is added on control gate and first area, produce bigger electrical potential difference between the two.As a result, charge carrier can be drawn out of easily.In addition, because high voltage is not added in tying between trap and first area, high electric field is not added on and ties, and makes it can be suppressed at hot hole and thermionic generation in the knot.
In order more completely to understand the present invention and its advantage, can be with reference to following description taken together with the accompanying drawings, in the drawings;
Fig. 1 is the block diagram that shows according to the described semiconductor memory of the first embodiment of the present invention;
Fig. 2 has shown the voltage that is added on memory cell array when write data;
Fig. 3 has shown the voltage that is added on memory cell array when obliterated data;
Fig. 4 is the cross-sectional view that shows memory cell;
Fig. 5 is the cross-sectional view that shows memory cell;
Fig. 6 A has shown in the described semiconductor memory according to the first embodiment of the present invention, is added on the voltage and the movement of electrons of memory cell during write data;
Fig. 6 B is the cross-sectional view that is presented near the zone drain junction under the state shown in Fig. 6 A with the form of amplifying;
Fig. 7 is presented at according in the described semiconductor memory of the first embodiment of the present invention, is added on the voltage of memory cell and the cross-sectional view of movement of electrons during obliterated data;
Fig. 8 shown in the described semiconductor memory according to the first embodiment of the present invention, added voltage when write data, read data and obliterated data,
Fig. 9 A is the voltage when being presented at write data in first prior art and the cross-sectional view of movement of electrons;
Fig. 9 B is the voltage when being presented at obliterated data in first prior art and the cross-sectional view of movement of electrons;
Figure 10 A is the voltage when being presented at write data in second prior art and the cross-sectional view of movement of electrons
Figure 10 B is the voltage when being presented at obliterated data in second prior art and the cross-sectional view of movement of electrons.
Referring now to Fig. 1 the semiconductor memory according to the first embodiment of the present invention is described.As shown in the figure, memory circuit according to the present invention comprises: memory cell array 4, this array is made up of the memory cell that is arranged to array, described memory cell constitutes electric writable and eresable and removes ROM (EEPROM), this electricity writable and eresable remove ROM can bit line B0 to Bn and word line W0 to the crosspoint of Wn on write data and can wipe the data of being write; Column decoder 2, be used to start the voltage that provides by power line 22, promptly, supply voltage Vdd and GND, to drive bit line B0 to Bn row decoder 3 according to the column address that provides by bus 21, be used to start the voltage that provides by power line 32, promptly, supply voltage Vdd and GND, to drive bit line W0 to Wn and controller 1 according to the row address that provides by bus 31, according to address that provides by bus 11 and the control data that provides by bus 12, be used for providing back gate terminal BG by power line 14 to memory cell array with the back grid voltage, source voltage is provided to source terminal S by power line 13, column address is provided to bus 21, bit-line drive voltage is provided to power line 22, row address is provided to bus 31, and word line driving voltage is provided to power line 32.
The memory cell that now concise and to the point description is used in the present embodiment.
Shown in Figure 4 and 5, memory cell is included in the N-trap 42 interior P-traps 43 that form on the P-substrate 41; Be formed on source region 44 and drain region 45 in the P-trap 43; In the channel region of source region 44 and 45 formation of drain region by SiO
2First dielectric film (gate oxidation films) 46 of the 80 dust thickness that form; The floating boom 47 that on gate oxidation films 46, forms, this floating boom 47 has the length of 0.4um and the width of 1.1um; Second dielectric film (dielectric film between grid) 48 that forms on floating boom 47, it is the SiO of 120 dusts corresponding to the thickness of capacitive form
2Film; And be formed on that the length on the dielectric film 48 is 0.4um control gate 49 between grid.Memory cell has the raceway groove that width is 0.6um.Each memory cell is disconnected from each other by element isolation zone 50.
Be described in detail in below be added in the operating process word line W0 to Wn, bit line B0 to Bn, the voltage of source electrode line S0, S1 and trap (back grid).Fig. 8 has shown the above-mentioned voltage in operating process.
At first, the situation that the data that relate to write the memory cell in the circle among Fig. 2 is described.Write fashionablely in data ,-9V, 6V and 0V (GND) voltage is added on word line W2 (control grid), bit line B1 (drain electrode) and the back grid of the memory cell that data as shown in Figure 2 will write respectively, and the source electrode open circuit.If storage system is driven by the power supply of 3.3V system, in this system, use GND and 3.3V, and-9V and 6V voltage must generate by controller 1.For these voltage is provided, controller 1 will be reduced to-and voltage that the voltage of 9V is provided to row decoder 3 by power line 32 and will be elevated to 6V is provided to column decoder 2 by power line 21, so that the voltage with rising that will reduce is provided to word line and the bit line of choosing respectively.On the other hand, 0V voltage is connected to each unchecked word line and bit line, and source S 0 and S1 open circuit.
If memory cell is at erase status, that is, threshold voltage vt m=5V is in the initial condition of writing ,-7 * 10
-15The electronics of coulomb (fc) appears at floating boom 47.Above-mentioned electronics and 0.7 capacity ratio make floating boom 47 bear-electromotive force of 8V.Above-mentioned " capacity ratio " refers to when all parasitic capacitance that is added on floating boom 47 are set at 1, the ratio of the capacitance that floating boom 47 and control gate are 49.As a result, in drain electrode 45 and 47 electrical potential differences that produce 14V of floating boom, shown in Figure 10 A, so that produce the FN channel phenomenon.So the electronics extraction is entered into drain electrode 45 by grid oxidation film 46.The electrical potential difference of 14V makes the surface energy degree of depth of drain electrode 45 exhaust.In addition, because higher in the impurity concentration of drain surface, forbidden band reduced width spatially is to several dusts.Thus, the electron tunneling arrival conduction band in valence band generates electronics and hole shown in Figure 10 B, and Figure 10 B has shown at drain junction state on every side in the mode of amplifying.
At this moment, the electric current that flow to P-trap 43 from 45 tunnellings by interband that drain approximately is that every memory cell 100nA is so little, makes it possible to power saving.Because the impurity concentration in P-trap 45 is higher, that is, and 2 * 10
17/ cm
3So the anti-avalanche voltage in drain junction is 9V.At the P-trap with the electrical potential difference between leaking when being 6V, the anti-avalanche voltage of this voltage ratio 9V hangs down 3V, is not to be higher than 5 * 10 at the highest electric field of drain junction
5/ cm
3, and the width of knot depletion layer is narrower,, is about 0.2 μ m that is.In this case, the impurity concentration in source and leakage is about 1 * 10 in shallow district
20/ cm
3, be about 1 * 10 at Shen Qu
17/ cm
3So the charge carrier that is produced by the potential barrier of tunnelling interband causes obtaining high reliability because of the possibility of the heating of flowing in depletion layer diminishes.In addition, the narrower width of knot depletion layer is the parameter that is beneficial to miniaturization.In the present embodiment, source electrode open circuit.But, be substantially fully based on Fowler-Nordheim electric current (FN electric current) owing to write, even write the time and the write current feature also remains unchanged when source electrode is configured to 0V.If extract electronics in this way out, threshold voltage vt m is lowered to 1V in about 500 μ s.In this state, floating boom 47 electric neutrality basically.In writing by finishing.
As mentioned above, the electrical potential difference of drain electrode 45 and 43 of P-traps reduce simultaneously by reduce the voltage of leakage 45 with the electronics of extracting out and reduce control gate 49 electromotive force and in the control gate 49 and 45 electrical potential differences that maintenance is bigger that drain, as a result, at drain junction, can suppress the generation of the charge carrier of heat.
Should be noted that, be added on drain electrode 45 voltage, so can be increased in P-trap 43 interior impurity concentrations and do not reduce reliability, make it can suppress to penetrate owing to can reduce.
When obliterated data,, the voltage of 11V is added on each word line W0 to Wn about the memory cell in the erase unit piece, general-4V voltage is added on each source electrode line S0 and S1, and general-4V voltage is added on back grid BG (P-trap), and bit line B0 is to Bn (drain electrode) open circuit, as shown in Figure 3 simultaneously.So, controller 1 generate 11V and-voltage of 4V, so that 11V voltage is provided to row decoder 3 by power line 32, general-4V voltage provides to source S by power line 13, and general-4V voltage provides to back grid BG by power line 14, thus needed voltage is provided to word line, source electrode line and back grid.
In the starting stage of data erase, have the memory cell of the state of being write and do not write the memory cell of state, the threshold voltage vt m=1V of the memory cell of being write, the threshold voltage Vtm=5V of the memory cell of not write.Owing to wipe the state of selected threshold voltage vt m=5V, so the state of the memory cell of its threshold voltage Vtm=SV does not change.Therefore, existing memory cell to threshold voltage vt m=1V is described.
In the memory cell of threshold voltage vt m=1V, floating boom 47 be neutrality substantially, and is described when the write data as the front.This situation and 0.7 capacity ratio make floating boom 47 bear the electromotive force of 6.5V.So electrical potential difference between floating boom 47 and back grid BG and the electrical potential difference between floating boom 47 and source electrode line S0, S1 all are 10.5V.As a result, produce the FN channel phenomenon, allow electronics to inject floating boom, to increase the value of transistorized threshold voltage, as shown in Figure 7 from back grid BG and source electrode 44.In the present embodiment, threshold voltage Vtm is increased to 5V (Vtm=5V) in the time of 50ms.
At this moment, the surface of P-trap 43 is converted to the N-type, forms the raceway groove between source electrode and drain electrode.But owing to be connected to the drain electrode maintenance open circuit of bit line B0 to Bn, channel current does not flow through between source electrode and drain electrode.The channel current that should be noted that interband does not flow, although there is the Fowler-Nordheim electric current (FN electric current) of 1 μ A/ memory cell to flow through approximately, the result can wipe the content of the memory cell in cell block with very low power.
Also should be noted that, can be lowered by the voltage that in electronics injection, reduces P-trap and source electrode 44, constitute the element of peripheral circuit owing to be added on the voltage of control gate, as transistor, withstand voltage can being lowered, make the miniaturization of peripheral circuit become possibility.
In addition, because drain electrode 45 keeps open circuit when electronics inject, channel current is at source electrode 44 and drain 45 and flow through, make it possible to reduce the electronics injection need power.Can reduce power consumption thus.
In read data, the address that is provided to controller 1 is used for providing the bit line of choosing to by the column address that is provided to column decoder 2 with 1V voltage, provides the word line of choosing to by the row address that is provided to row decoder 3 with the voltage of 3.3V=Vdd.Whether data are written to the memory cell chosen can be decided by the electric current that memory cell is flow through in detection.
For the purpose of simplifying the description, present embodiment relates to the situation of single memory cell block.Much less, still, technical conceive of the present invention also can be applicable to the semiconductor memory that contains a plurality of memory cell blocks.
As mentioned above, the present invention can prevent the generation of hot carrier in electronics is extracted out, thereby improves the reliability of memory cell.Simultaneously, owing to can prevent to penetrate, memory cell can realize minimizing.In addition, the withstand voltage of peripheral circuit can reduce by the voltage that reduction is added on control gate, thereby reduces the power consumption of injecting at electronics.
Although the preferred embodiments of the present invention are described in detail, should be appreciated that various changes, substitute and conversion can be made under the condition that does not deviate from the spirit and scope of the present invention that limited by claims.
Claims (9)
1. semiconductor memory comprises:
Memory cell, this memory cell comprises Semiconductor substrate, be formed on the trap of first conduction type in the described Semiconductor substrate, first and second zones that in described trap, form, so that at the described first and second interregional formation channel regions, be formed on the described top floating boom of stating channel region, this floating boom has and places first dielectric film that is used to accumulate charge carrier therebetween, with the control gate that is formed on the described floating boom, this control gate has second dielectric film that places therebetween;
Control circuit, this control circuit when described floating boom is extracted out, are added on described control gate with first voltage of first polarity at charge carrier, will be added on described first area with second voltage of first opposite polarity second polarity.
2. semiconductor memory according to claim 1 is characterized in that: described control circuit when described floating boom is extracted out, and is added on described trap with the reference voltage of amplitude between described first voltage and described second voltage at described charge carrier.
3. semiconductor memory according to claim 1, it is characterized in that: when described control circuit is injected into described floating boom at described charge carrier, the tertiary voltage of described second polarity is added on described control gate, the 4th voltage of described first polarity is added on described second area, and the 5th voltage of described first polarity is added on described trap.
4. semiconductor memory according to claim 1 is characterized in that: in charge carrier is extracted out, from described first voltage of described control circuit output and the second voltage height to allowing the Fowler-Nordheim electric current to flow through described first dielectric film.
5. semiconductor memory according to claim 3 is characterized in that: in the charge carrier injection process from tertiary voltage, the 4th voltage and the 5th voltage height of described control circuit output to allowing the Fowler-Nordheim electric current to flow through described first dielectric film.
6. semiconductor memory according to claim 5 is characterized in that: described the 4th voltage has identical level with described the 5th voltage.
7. semiconductor memory according to claim 3 is characterized in that: described first area keeps establishing by cable the road.
8. semiconductor memory comprises:
Memory cell, this memory cell comprises Semiconductor substrate, be formed on the trap of first conduction type in the described Semiconductor substrate, first and second zones of second conduction type that in described trap, forms, make channel region in the described first and second interregional formation, be formed on the described top floating boom of stating channel region, this floating boom has and places first dielectric film that is used to accumulate charge carrier therebetween, with the control gate that is formed on the described floating boom, this control gate has second dielectric film that places therebetween;
When controller, this controller inject at described charge carrier, the tertiary voltage of described second polarity is added on described control gate, first voltage of described first polarity is added on described second area, second voltage of described first polarity is added on described trap.
9. semiconductor memory according to claim 8 is characterized in that: described first voltage and second voltage are high to allowing the Fowler-Nordheim electric current to flow through described first dielectric film.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP151263/98 | 1998-06-01 | ||
| JP15126398A JPH11345495A (en) | 1998-06-01 | 1998-06-01 | Semiconductor storage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1237794A true CN1237794A (en) | 1999-12-08 |
Family
ID=15514850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99107884A Pending CN1237794A (en) | 1998-06-01 | 1999-05-31 | Semiconductor memory device equipped with access circuit for performing access control of flash memory |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH11345495A (en) |
| KR (1) | KR20000005702A (en) |
| CN (1) | CN1237794A (en) |
| TW (1) | TW424327B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1937078B (en) * | 2005-09-23 | 2010-05-12 | 旺宏电子股份有限公司 | Multi-operation mode nonvolatile memory |
| CN107644659A (en) * | 2016-07-21 | 2018-01-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of multiple timings programmable storage and electronic installation |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100479193C (en) * | 2004-08-17 | 2009-04-15 | 北京大学 | Floating gate flash field effect transistor |
-
1998
- 1998-06-01 JP JP15126398A patent/JPH11345495A/en active Pending
-
1999
- 1999-05-24 KR KR1019990018626A patent/KR20000005702A/en not_active Application Discontinuation
- 1999-05-31 CN CN99107884A patent/CN1237794A/en active Pending
- 1999-05-31 TW TW088109087A patent/TW424327B/en active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1937078B (en) * | 2005-09-23 | 2010-05-12 | 旺宏电子股份有限公司 | Multi-operation mode nonvolatile memory |
| CN107644659A (en) * | 2016-07-21 | 2018-01-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of multiple timings programmable storage and electronic installation |
| CN107644659B (en) * | 2016-07-21 | 2020-08-18 | 中芯国际集成电路制造(上海)有限公司 | Multi-time-sequence programmable memory and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11345495A (en) | 1999-12-14 |
| KR20000005702A (en) | 2000-01-25 |
| TW424327B (en) | 2001-03-01 |
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