TW424327B - Semiconductor memory device equipped with access circuit for performing access control of flash memory - Google Patents

Abstract

Disclosed is a semiconductor memory device comprising a memory cell and a controller. In the memory cell capable of electrically writing-erasing data, the voltage applied between the drain and the well is lowered in withdrawing electrons from the floating gate. When electrons are withdrawn from the floating gate included in the memory cell, the controller serves to apply a voltage of -9V to the gate, a voltage of 6V to the drain, and a voltage of 0V to the back gate of a selected memory cell.

Description

324327 V. Description of the Invention (!) [Background of the Invention] The present invention relates to a semiconductor memory element, and more particularly to a semiconductor memory element, which has a control circuit for performing flash memory access control. In recent years, the demand for non-volatile memory capable of retrieving stored contents even after the power is turned off has increased. In addition, a flash memory capable of erasing stored contents in units of blocks has attracted attention. Different from the general dynamic random access memory {meaning body (DRAM, dynamic random access memory) or If state random access memory, it- (SRAM 5 static random access memory), the flash memory is writing When erasing data, the required dust and power voltage Vdd or ground voltage GND are different, that is, the voltage is not between the power voltage V dd and the ground voltage GND. Examples of voltages when writing and erasing data to and from a flash memory are shown in Japanese Patent Laid-Open Publication No. Hei 6-15070. In this first conventional technique, at the time of writing data, a voltage of 10 V (GND) is applied to a control unit 149 connected to a word line, as shown in FIG. 9A. Also, when writing data, 20 V and G N D voltages are applied to the drain electrode 145 and a P well 143 respectively. At this time, since a potential difference of 20 V is generated between the drain electrode I 4 5 and the control gate 1 4 9, the electrons are extracted from the floating valve 1 4 7 to the drain electrode 1 through an oxide film 1 4 6 due to the FN channel phenomenon. 4 ΰ 'causes the threshold voltage V t ra of the transistor constituting the memory element to decrease. In contrast, when erasing data, a voltage of 20 V is applied to the control gate 1 4 9 as shown in Fig. 9B. In addition, G N D is applied to each of the source electrodes 1 4 4 and P wells 1 4 3, and the drain electrodes 1 4 5 remain open. At this time, due to a potential difference of 20 V in one direction and in the opposite direction during writing, the electrons pass through the gate oxide film 1 4 6 due to the F N channel phenomenon.

Page 5 424327 V. Description of the invention (2) The injection of the P well 1 4 3 into the floating gate 1 4 7 causes the threshold voltage V t m of the memory element to increase. Figures 10A and 10B show a second conventional technique for writing and erasing flash memory. In the second conventional technique, a voltage of 10 V is applied to the control gate 1 4 9 ^ when writing data, and 6 V, GND, and GND are applied to the drain 1 4 5 and the source 1 4 respectively. 4 and P wells 1 4 3. At this time, a channel current flows from the source 1 4 3 to the light pole 1 4 5. The electrons forming the channel current are accelerated by a strong electric field applied to the junction of the drains between the P wells 1 4 3 and the poles 1 4 5 to form hot electrons. The thermoelectron is partially injected into the floating gate 1 4 7 by the electric field pulling force between the control gate 1 4 9 and the P well 1 4 3, which increases the threshold voltage of the memory element. When erasing data, voltages of -10 V, 6 V, and 0 V were applied to the control gate 1 4 9, source 1 4 4 and P well 1 4 3, respectively, and the drain 1 4 5 remained open. At this time, due to the F N channel phenomenon, the electrons are extracted from the control gate 149 through the gate oxide film to the source 144, which causes the threshold voltage V t m to decrease. However, in the first conventional technique, a high voltage of 20 V is applied to the drain junction between the well and the drain during data writing, which deteriorates the characteristics of the memory element and reduces reliability. Since a strong electric field is applied to the drain junction when writing data, hot electrons and hot holes are generated. The thermal holes generated in this way are attracted by the strong electric field and sink into the oxide film. As a result, an insulation defect such as a leakage occurs in the insulating film, and a decrease in reliability as mentioned before occurs. In addition, since a high voltage is applied during data writing and data erasing, a high-time pressure memory element must be used. However, it is difficult to shrink a high-inch pressure memory element. It should be noted that in order to increase the memory components

424327 V. Description of the invention (3) Withstand voltage, the breakdown pressure between source-drain and P well must be improved. Therefore, it is necessary to reduce the impurity concentration in the P well. However, if the impurity concentration in the P-well decreases, the empty layer will expand from the junction of the drain, resulting in the possibility of a punch-through phenomenon between the source and the drain. Secondly, in order to ensure the high withstand voltage of the memory element, the source and the drain must be far away from each other to avoid punch-through. It should be noted that high voltage is not only applied to the memory elements, but also to the peripheral circuits that drive the memory elements. This makes it necessary to use high withstand voltage elements when forming peripheral circuits. Of course, it is difficult to shrink peripheral components like a memory element. In the second conventional technique, a channel current of milliampere level is allowed to flow between the source and the source during data writing ', resulting in a large current consumption of one. In the integrated circuit developed in recent years, a microcomputer and a flash memory are mounted on the same chip ^ 1. The power supply of 1.8 to 5 V is boosted by a booster circuit in the chip to generate a high voltage ° The resulting high voltage is used to write and erase data. However, the current supply capability of the boost circuit depends on the capacitance of the capacitor. Therefore, in order to stably supply a large current, it is necessary to form a capacitor in the 'one meter level region on the wafer. Clearly, because the wafer itself is millimeter-scale, it is not practical to form such a large capacitance on the wafer. In this case, in view of recent technological trends, it is necessary to reduce the write current of battery-driven flash memory to reduce its power consumption. [Summary of the Invention] The first object of the present invention is to provide a control circuit to form a flash memory using a memory device with a low withstand voltage. A second object of the present invention is to provide a control circuit to reduce power consumption.

Page 7 424327 V. Description of the invention (4) According to the present invention, a semiconductor memory element is provided, including: a memory element having: a semiconductor substrate; a well of a first conductivity type formed in the semiconductor substrate The first and second regions of the second conductivity type are formed in the well; a channel region is formed between the first and second regions; a floating gate is formed on the channel region; A first insulating film that is placed between the floating gate and the channel region to accumulate carriers; a control gate that is formed on the floating gate; a second insulating film that is placed between the control gate and the floating gate; and A control circuit, when a carrier is extracted from the floating gate, the circuit applies a first voltage of a first polarity to the control gate, and applies a second voltage of a second polarity opposite to the first polarity to the first region. When carriers are extracted, applying a different polarity of electric current M to the control gate and the first region will cause a large potential difference between them. In this way, the carriers can be easily extracted. In addition, since a high voltage is not applied to the junction between the ytterbium and the first region, a high electric field is not applied to the junction, so that hot holes and hot electrons generated at the junction can be reduced. [Brief description of the drawings] In order to more fully understand the present invention and its advantages, the following description will refer to the corresponding drawings, wherein: FIG. 1 is a block diagram showing a semiconductor memory element according to a first embodiment of the present invention Figure 2 shows the voltage applied to the memory element array when writing data; Figure 3 shows the voltage applied to the memory element array when data is erased; Figure 4 is a cross-sectional view showing the memory element;

Page 8 424327 V. Description of the invention (5) FIG. 5 is a cross-sectional view showing a memory element; FIG. 6A shows a voltage applied to the memory element and semiconductor memory when writing data according to the first embodiment of the present invention The movement of electrons in the element; FIG. 6B shows an enlarged cross-sectional view of the region near the junction of the drain electrode in the state of FIG. 6A; FIG. 7 is a cross-sectional view showing the first embodiment of the present invention. The voltage applied to the memory element and the movement of electrons in the semiconductor memory element at the time; FIG. 8 shows the voltage applied when writing data, reading data, and erasing data according to the first embodiment of the present invention; FIG. 9 A is a A cross-sectional view showing the applied voltage and the movement of electrons when writing data according to the first conventional technique; Figure 9B is a cross-sectional view showing the applied voltage when erasing data according to the first conventional technique And the motion of electrons; 圊 1 (] A is a cross-sectional view showing the voltage applied when writing data and the motion of electrons according to the second conventional technique; and FIG. 10B is a cross-sectional view showing the basis of The second conventional technique is the voltage and the movement of electrons when erasing data. [Explanation of symbols] 1 ~ controller 1 1 ~ busbar 1 2 ~ busbar 1 3 ~ power line 1 4 ~ power line

Page 9 424327 V. Description of the invention (6) 143 ~ P well 1 4 4 ~ source 1 4 5 ~ drain 1 4 6 ~ gate oxide film 1 4 7 ~ floating valve 1 4 8 ~ gate insulation film 1 4 9 to control gate 2 to row decoder 2 1-bus 2 2 to power line 3 to column decoder 3 1 to bus 3 2 to power line 4 to memory element array 4 1 to P substrate 42 to N 丼 43 ~ P well 4 4 ~ source region 4 5 ~ ί and pole region 4 6 ~ first insulating film 4 7 ~ floating gate 4 8 ~ second insulating film 4 9 ~ control gate 5 0 ~ element isolation region

Page 10 243 ^ 7 V. Description of the invention (7) B 0 to B η ~ bit line BG ~ back gate CG ~ control gate 'D ~ drain terminal S ~ source terminal S 0 ~ power line S 1 ~ power line W0 to word line [Detailed description of the preferred embodiment] A semiconductor memory element according to a first embodiment of the present invention: an example will be described with reference to FIG. 1. As shown in the figure, the memory circuit according to the present invention includes: a memory element array 4 formed by arranging memory elements to form an array, and the memory elements include electrically erasable programmable read-only memory (EEPR Ο Μ, electrically writable-erasable). ROM), which can write and erase data at the intersections between the bit lines BO to B η and the word lines W 0 to W η; a row of decoders 2 supplies a voltage via a power line 22, that is, the power supply voltages Vdd and GND To drive the bit lines B0 to Bn to respond to the row addresses supplied via the bus 21; a column of decoders 3 supplies voltages via a power line 32, that is, the power voltages V dd and GND to drive the word lines W 0 to W η respond to the column address supplied via the bus 31;-the controller 1 supplies a back-gate voltage to the back-gate β G of the memory element array via the power line 14 and the power line 1 3 Supply a source voltage to the source terminal S, supply the row address to the bus 21, and supply the bit drive voltage to the power supply

Page 11 424327 V. Description of the invention (8) Line 2 2 supplies the column address to the bus 3 1 and supplies the word line drive voltage to the power line 3 2 to the address supplied via the bus 1 1 and Respond via the control data supplied by the bus 1 2. The controller 1 receives address data and control data supplied from a control unit such as a central processing unit (not shown) via the bus bars 1 1 and 12 to control the memory element to write based on the received address data and control data. In, out and read the actual material in and out. The controller also generates voltages required for these operations in addition to the power supply voltages Vdd and GND. The following briefly describes the memory element used in this embodiment. As shown in FIGS. 4 and 5, the memory element includes: a p-well 43 formed in the N-well 42 of the P substrate 41; a source region 44 and a drain region 45 formed in P 丼 43; A first insulating film (gate oxide film) 46 is formed of silicon dioxide and has a thickness of 80 angstroms and is located in a channel region between the source region 44 and the drain region 45. A floating gate 4 7 is formed at On gate oxide film 46, length 0.4 / m width 1 · 1 pm; a second insulating film (inter-gate insulating film) 4 8 formed on floating gate 47, equivalent to thickness according to capacitance value conversion A silicon dioxide film of 120 angstroms; and a control gate 49, which is formed on the inter-gate insulation film 48 and has a length of 0.4 μm. The memory element has a channel with a width of 0.6 / i m. Each memory element is separated from each other by an element isolation region 50. The voltages applied to the word lines W 0 to W η, the bit lines B0 to Bn, the power supply lines SO and S1, and the well (back gate) during operation are discussed in detail below. Figure 8 shows the voltage during operation.

Page 12 4243 2 7 V. Description of the invention (9) First, the memory element in which data is written in this description is shown in the circle in FIG. 2. When writing materials, voltages of -9 \, 6 V, and 0 V (GND) are applied to the word line W 2 (control gate) and bit line B 1 (drain) of the memory element in which data is written in FIG. 2, respectively. Pole) and back gate, the source remains open. If the memory system is driven by a 3.3V power supply system and uses a voltage of GND and 3.3V ', the voltages of -9V and 6V must be generated by the controller 1. To supply these voltages, the controller 1 supplies a voltage reduced to -9V to the column decoder 3 via the power line 32 and a voltage boosted to 6 V to the row decoder 2 via the power line 2 1 to select The word and bit lines supply reduced and boosted voltages. On the other hand, 0 V is connected to the unselected word and bit lines, and the sources S 0 and S 1 remain open. If the memory element is in the erased state, that is, the threshold voltage V t m = 5 V, at the beginning of writing, there are -7 f c electrons in the floating gate 47. The capacitance ratio of these electrons to a 0.7 causes the floating gate 47 to withstand a potential of 8 V. The above-mentioned "capacitance ratio M" represents the capacitance ratio between the floating gate 47 and the control gate 49 when all the parasitic capacitances added to the floating gate 47 are set to 1. As a result, the drain 45 and the floating gate 47 are generated. The potential difference of 14 V is shown in Fig. 10 (A), which leads to the FN channel phenomenon. Then the electrons are drawn out through the gate oxide film 46 into the potential difference of 45 ° to 14V, which causes the surface of the drain 45 to be in energy. Extremely empty. In addition, due to the high concentration of impurities on the drain surface, the width of the forbidden band is narrowed to several angstroms. Therefore, the electrons in the valence band generate electrons and holes through the channels of the conductive band, as shown in Figure 10 (B ) The state in the vicinity of the pole junction is enlarged. At this time, the current flowing from the pole 45 to the P well 43 through the inter-band channel is as small as about 100 ηA per memory element, providing the key to power saving. Since P Well 4 5

Page 13 5. The impurity concentration in the description of the invention (ίο) is high, 2 * 1 017 / cm3, and the breakdown voltage of the junction of the drain electrode is 9 V. When the potential difference between the P well and the drain is 6 V, which is 3 V lower than the 9 V burst withstand voltage, the maximum electric field at the drain junction is 5 * 1 05 / c in3 or less, and the width of the junction empty layer Narrow to about 0.2 μm. In this case, the impurity concentration of the source electrode and the drain electrode is about 1 * 10 2 cm 3 in the shallow part and about 1 * 10 n / cm 3 in the deep part. Therefore, the carrier generated in the inter-band channel is less likely to be heated due to the movement in the empty region, and high reliability cannot be obtained. In addition, a small width of the joint empty area is advantageous for miniaturization. In this embodiment, the source remains open. However, since the writing is almost based on the F N current, even if the source is set to 0 V, the writing time and writing current characteristics do not change. If the electrons are thus extracted, the threshold voltage V t in is reduced to 1 V in about 50 0 y s. In this state, the floating gates 4 and 7 are almost non-powered. Writing is thus completed. As mentioned above, when the large potential difference between the control gate 49 and the drain 45 is maintained, the potential difference between the electrodes 45 and the P well 43 is reduced by reducing the potential of the control gate 49 and the electrons drawn from the drain 45. The voltage is reduced so that the generation of hot carriers at the drain junction is reduced. In addition, since the voltage applied to the drain 45 is reduced, the impurity concentration in the P-well 43 can be increased without lowering the reliability and reducing the punch-through phenomenon. When erasing data, in the memory element in the erasing unit block, a voltage of 1 1 V is applied to each of the word lines W0 to Wn, and a voltage of -4 V is applied to each of the power lines S0 and S1 and the back gate BG ( Well), the bit lines B0 to Bn (drain) remain open, as shown in FIG. 3. The controller 1 then generates voltages of 1 1 V and 4 V to supply a voltage of 1 1 V to the column decoder 3 through the power supply line 3 2 and supplies power to the column decoder 3 through the power supply.

Page 14 V. Description of the invention (11) The application line 1 3 supplies a voltage of -4 V to the source S, and the power supply line 14 supplies a voltage of -4 V to the back gate BG to supply the word line and power supply. Line and backgate voltage. In the initial state of erasing data, there is a memory element in a write state, that is, a threshold voltage V t ι = 1 V, and a memory element in a non-write state, that is, a threshold voltage V t m = 5 V. Because the threshold voltage of the selected state during erasing is 5 V, the state of the memory element with the threshold voltage of 5 V will not change. Therefore, the memory element under the threshold voltage V 1; in = 1 V will be described below. In a memory element with a threshold voltage V t m = 1 V, the floating gate 47 is almost electrically neutral, as described in the previous data. This state and the capacitance ratio of 0.7 cause the floating gate 47 to withstand a potential of 6.5 V. Therefore, the potential difference between the 'floating gate 47 and the back gate B G and the floating gate 47 and the power supply lines S 0 and S 1 is 10.5 V. As a result, a FN channel phenomenon is generated, allowing electrons to be injected into the floating gate from the back gate BG and the source 44 to increase the threshold voltage of the transistor, as shown in FIG. 7. In this embodiment, the threshold voltage Vtm is raised to 5V (Vtm = 5V) within 50ms. At this time, the surface of the P well 43 is inverted into an N-type to form a source and drain channel. However, since the drains connected to the bit lines B 0 to B η are open, the channel current between the source and the drain does not flow. It should be noted that the current between the band channels does not flow, and about 1 η A / F N current of the memory element flows, resulting in the content of the memory element in a unit block being erased by a very low power source. It is worth noting that since the voltage applied to the control gate can be reduced by reducing the voltage of the P-well 43 and the source electrode 44 during electron injection, the withstand voltage of components including peripheral circuits such as transistors can be reduced. This makes it possible to miniaturize peripheral circuits.

Page 15 424327 V. Description of the invention (12) In addition, since the drain 45 is open during electron injection, the channel current between the source 44 and the drain 45 does not flow, which can reduce the power demand during electron injection. . In this way, power consumption can be reduced. When reading data, the address sent to the controller 1 will supply a voltage of 1 V to the bit line selected by the row address sent to the row decoder 2, and the voltage of 3.3 V = V dd to The word line selected by the column address sent to the column decoder 3. The presence or absence of written data in the selected memory element can be known by checking the current flowing through the memory element. This embodiment uses the condition of a single memory element_block to simplify the description. However, needless to say, the present invention can be technically applied to a semiconductor memory device including a plurality of memory element blocks. As described above, in the present invention, the generation of hot carriers can be avoided when the electrons are extracted, and the reliability of the memory element can be improved. In addition, since the punch-through phenomenon can be avoided, the memory element can be miniaturized. In addition, by reducing the voltage of the control gate, the withstand voltage of peripheral circuits can be reduced, and the power consumption during electron injection can be reduced. Although the preferred embodiment of the present invention has been described in detail, it should be understood that various modifications, substitutions and changes can be implemented without departing from the spirit and scope of the patent application scope of the present invention.

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Claims (1)

42432? 6. Patent application scope 1. A semiconductor memory device comprising: a memory element having: a semiconductor substrate; a well of a first conductivity type is formed in the semiconductor substrate; a first sum of a second conductivity type A second region is formed in the well; a channel region is formed between the first and second regions; a floating gate is formed on the channel region; a first insulating film is placed therebetween to accumulate carriers; a control gate is formed A second insulating film is placed between the floating gate; and a control circuit, when a carrier is withdrawn from the floating gate, the circuit applies a first voltage of a first polarity to the control gate, and The second voltage of the opposite polarity and the second voltage is in the first region. 2. For example, a semiconductor memory device in the scope of the patent application, wherein: when the carrier is withdrawn from the floating gate, the control circuit applies a reference voltage to the well, the magnitude of which is between the first voltage and the second voltage. Voltage. 3. The semiconductor memory device according to item 1 of the patent application scope, wherein: when the carrier is injected into the floating gate, a third voltage of the second polarity is applied to the control gate, and the second region is applied to the control gate A fourth voltage of the first polarity is applied, and a fifth voltage of the first polarity is applied to the well. 4. The semiconductor memory device according to item 1 of the patent application, wherein: the first voltage and the second voltage output by the control circuit when a carrier is extracted are high enough to allow a F N current to flow through the first insulation layer. Page 17 42432γ 6. Patent application scope 5. For example, the semiconductor memory device of patent application scope item 3, wherein: the third voltage, the fourth voltage, and the fifth voltage output by the control circuit when the carrier is injected are as high as An FN current is allowed to flow through the first insulating layer. 6. The semiconductor memory device as claimed in item 5 of the patent application, wherein: the fourth voltage and the fifth voltage have the same voltage level. 7. The semiconductor memory device as claimed in item 3 of the patent application, wherein: the first The area is electrically open. 8. A semiconductor device comprising:-a memory element having: a semiconductor substrate; a well of a first conductivity type is formed in the semiconductor substrate; first and second regions of a second conductivity type are formed in the In the well; a channel region formed between the first and second regions; a floating gate formed on the channel region; a first insulating film placed between the floating gate and the channel to accumulate carriers; a control gate Formed on the floating gate; a second insulating film provided between the control gate and the floating gate; and a controller for applying a third voltage of the second polarity to the control gate during carrier injection A first voltage of the first polarity is in the second region, and a second voltage of the first polarity is in the well. 9. The semiconductor memory device according to item 8 of the patent application, wherein: the first voltage and the second voltage are high enough to allow a F N current to flow through the first Page 18 4243 2 7 Page 19