CN1236485C - Manufacture of double mosaic wire copper wire inside low layer - Google Patents
Manufacture of double mosaic wire copper wire inside low layer Download PDFInfo
- Publication number
- CN1236485C CN1236485C CN 01109625 CN01109625A CN1236485C CN 1236485 C CN1236485 C CN 1236485C CN 01109625 CN01109625 CN 01109625 CN 01109625 A CN01109625 A CN 01109625A CN 1236485 C CN1236485 C CN 1236485C
- Authority
- CN
- China
- Prior art keywords
- layer
- dielectric layer
- copper
- ditches
- irrigation canals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a double-embedding making method for the connection of a copper wire in a lower layer. The present invention is carried out on the premise that a copper wire and a dielectric layer on the lower layers are formed in a double-embedding pattern of a semiconductor basal plate. The surface of the dielectric layer is exposed from the dielectric layer of the interconnector of the lower layer, and an oxide layer is formed on the dielectric layer of the interconnector of the lower layer; a plurality of wire channels are formed in the oxide layer by using the procedures of microphotograph and etching, one wire channel enables the dielectric layer to be exposed, and a barrier layer is formed on the exposed outer surface; the barrier layer is etched in an anisotropic mode, so gap walls are formed on side walls of the wire channels; electric slurry bombardment is carried out by using inert gases so as to clean copper oxide on the copper wire of the dielectric layer; a conductor layer is formed to fill the wire channels and overflow; the conductor layer on the oxide layer is removed by CMP.
Description
Technical field
The invention relates to semi-conductive manufacturing, be meant especially in a kind of manufacturing of dual damascene that with the bottom of copper conductor at double-mosaic pattern, and the plain conductor on upper strata is not restricted to the manufacture method of copper conductor especially.
Background technology
Along with the progress of integrated circuit technique, it is not at all surprising that a large amount of transistors, electric capacity or other passive device form on the single wafer.The marked improvement of component size microminiaturization trend and multiple layer inner connection line interconnection technique is given the credit in the significantly lifting of element concentration class, major part.But, in multiple layer inner connection line interconnection technique, along with lead is intensive, hiding many problems to be overcome.For example, when lead was intensive, reduced in the gap of implying between lead, therefore, how to insert these conductor spacings at the intraconnections dielectric layer, do not produce and do not have the cavity, and be a problem to be overcome to guarantee reliability.Secondly, how at the manufacturing intermediary layer hole (via hole) that lead is inlayed and the aligning of lead, not producing alignment error (misalignment), is another problem to be overcome.
Recently, by No. 6087251 a kind of new dual damascene technology of report of United States Patent (USP) that Mr. Hsu obtained, it can solve and be generally problem and the complicated deposition step that forms double-mosaic pattern intermediary layer hole and lead irrigation canals and ditches alignment error, and the method for proposition is as follows:
Step 1, consult Fig. 1, deposited dielectric layer between the first metal layer (IMD) 201 on the semiconductor substrate 200, in order to be connected (figure does not show) with element under it, then silicon nitride layer 202 is formed on the dielectric layer between the first metal layer (IMD) 201, at silicon nitride layer 202 again via the manufacturing patterning of photoetching and etching etc., to form lead irrigation canals and ditches 204a, 204b and 204c.
Step 2, as shown in Figure 2, conductor layer is deposition then, to fill up above-mentioned irrigation canals and ditches 204a, 204b and 204C.The part that conductor layer surpasses silicon nitride layer 202 upper surfaces then removes with the method for chemistry or mechanical polishing.
Step 3 as shown in Figure 3, covers a lead 206b wherein with photoresist pattern 208 earlier, then, imposes the etch-back step again, reaches predetermined being left till the thickness of base conductor approximately to remove the first half of lead 206a and 206c, to be etched to.Therefore, after this step, time layer conductor 206a ', 206c ' and interlayer 206b have been formed.
Step 4 is consulted shown in Figure 4ly, and with silicon nitride layer 202 backfill irrigation canals and ditches 206a ' and 206c ', the processing procedure with chemistry or mechanical polishing removes the part silicon nitride layer again, till exposing conductor layer 206b.Afterwards, be deposited on the silicon nitride layer 202 with an oxide layer 210 again.Oxide layer 210 is as the second metal interlevel oxide layer (IMD2).
Step 5 is consulted Fig. 5, and oxide layer 210 imposes patterning again, to form the irrigation canals and ditches 212 of level, exposes up to the surface of interlayer 206b.Horizontal irrigation canals and ditches 212 are again with the conductor layer backfill.Conductor layer exceeds the part of oxide layer 210 upper surface layers, and the processing procedure with chemistry or mechanical polishing removes again.Conductor layer on the irrigation canals and ditches 212 of level is the lead as the upper strata.
Aforesaid prior art when definition lead and interlayer hole, is carried out simultaneously.Do not need to go definition with the photoresist pattern again.The problem of alignment error when therefore, not having the definition interlayer hole.Its major defect is:
In the above-mentioned processing procedure,, will produce some problems if when bottom lead 206a, 206c and interlayer 206b are copper metal layer.For example, in case copper interlayer 206b exposes the surface, the oxide layer that will form layer of copper in the above, thus, before forming topping wire and interlayer 206b is connected, just need earlier with plasma bombardment, to remove this layer of copper oxide layer, to reduce resistance between the two.Yet in the process of plasma bombardment, the copper of part also can be spilt and be deposited, and for example the sidewall of irrigation canals and ditches 212 promptly is most probable deposition position.Clearly, sidewall is as if no any barrier layer, and copper will diffuse in the oxide layer 210, and makes that the product qualitative change of oxide layer 210 is bad.
Summary of the invention
The object of the present invention is to provide the manufacture method of a kind of copper conductor dual damascene of line within lower floor, overcome the drawback of prior art, prevent in the processing procedure of dual damascene the copper interlayer because of removing the copper oxide layer, and produce sputter, reach the purpose that improves quality in the oxide layer of lead trench sidewall.
The object of the present invention is achieved like this: the manufacture method of a kind of copper conductor dual damascene of line within lower floor, it is characterized in that: it comprises the steps:
(1) provides the semiconductor substrate;
(2) on this semiconductor substrate, form first dielectric layer; This first dielectric layer of patterning is to form most first irrigation canals and ditches in wherein;
(3) form a bronze medal layer, with these first irrigation canals and ditches of backfill; Impose chemistry or mechanical polishing to remove copper layer, to form most copper conductors above this first dielectric layer top;
(4) form mask pattern to cover a copper conductor, this copper conductor is predetermined as interlayer; With this mask pattern is etching mask, with the first half of remaining copper conductor of etching, to a preset thickness, has formed the bottom lead, and this bottom lead top stays second irrigation canals and ditches;
(5) remove this mask pattern; These second irrigation canals and ditches of backfill are to be same as the dielectric layer of the first dielectric layer material; Impose chemistry or mechanical polishing, to remove first dielectric layer, in order to the upper surface of exposed this interlayer above this interlayer;
(6) on this first dielectric layer, form second dielectric layer; This second dielectric layer of patterning is to form the 3rd irrigation canals and ditches;
(7) on second dielectric layer behind this patterning, form a barrier layer; Impose an anisotropic etch method and on the sidewall of the 3rd irrigation canals and ditches, form clearance wall;
(8) with the upper surface of this interlayer of plasma bombardment, to remove the copper oxide layer;
(9) impose conductor layer backfill the 3rd irrigation canals and ditches; Impose chemistry or mechanical polishing, to remove the conductor layer of this second dielectric layer top, to form most upper conductor layer.
Described first dielectric layer comprises silicon nitride layer at least.Described second dielectric layer comprises silicon oxide layer at least.Described barrier layer be selected from TiN, SiN, TaN, WN, Ta, W or Ti one of them.Described conductor layer is to be selected from one of them of group that copper, tungsten or aluminium forms.
Major advantage of the present invention is to have solved the copper oxide layer to be returned the problem that is plated in oxide layer by plasma bombardment.
Further specify below in conjunction with preferred embodiment and accompanying drawing.
Description of drawings
Fig. 1 is that prior art forms the lead irrigation canals and ditches in the cross sectional representation of silicon nitride layer.
Fig. 2 is that prior art backfill conductor layer is in the cross sectional representation of lead irrigation canals and ditches.
Fig. 3 is that prior art forms the wherein cross sectional representation of a lead of a mask.
Fig. 4 is the cross sectional representation that prior art forms a bottom lead and an interlayer.
Fig. 5 is that prior art forms the cross sectional representation of horizontal irrigation canals and ditches in oxide layer.
Fig. 6 is the cross sectional representation that prior art forms topping wire.
Fig. 7 is that method of the present invention forms barrier layer in the cross sectional representation of the oxide layer of patterning.
Fig. 8 is that method of the present invention forms clearance wall in the cross sectional representation of lead trench sidewall.
Fig. 9 is the cross sectional representation of method of the present invention with inert gas plasma bombardment copper interlayer surface oxide layer.
Figure 10 is the cross sectional representation that method of the present invention forms topping wire.
Figure 11 is the cross sectional representation that method of the present invention forms a bottom lead and an interlayer.
Embodiment
Consult Fig. 7-Figure 11, The present invention be directed to the problem that prior art exists, the improvement technology of proposition, the manufacturing which kind of has now dual damascene regardless of all can stay some problems to be solved, for example the alignment error problem of lead irrigation canals and ditches and interlayer hole pattern formation.Aforesaid Mr.'s Hsu patented technology, though can solve the above problems, yet, if with copper during as the material of dual damascene bottom lead and interlayer, the conductor material that forms another non-copper is thereon the time, since must be earlier to exposed copper interlayer plasma bombardment removing surperficial copper oxide layer, but and this step can cause with the oxide layer pollution problem when being intraconnections interlayer material.
The present invention can prevent that above-mentioned problem from taking place.Among Fig. 5 as prior art, on semiconductor substrate, have an IMD layer 201, silicon nitride layer 202 and oxide layer 210 and deposit in succession and finish.In silicon nitride layer 202, have bottom lead 206a ' and 206c ', in order to be connected with an IMD layer 201 interior lead (not shown) under it, copper interlayer 206b will be in order to being connected to form in oxide layer 210 (i.e. the 2nd IMD layer 210), and illustrated horizontal irrigation canals and ditches 212 are by photoetching and etching and form.
Consult Fig. 7, the present invention at first deposits one deck barrier layer 220 on the bottom and sidewall of oxide layer 210, irrigation canals and ditches 212.Usually this barrier layer 220 is with PVD or CVD method deposition, and the selection of material can comprise following several one of them, for example TiN, SiN, TaN, WN, Ta, W or Ti.
Consult shown in Fig. 8,9, then implement an anisotropic etch method, in order to form clearance wall 220a on the sidewall of irrigation canals and ditches 212, this step is to make the upper surface of copper interlayer 206b expose.Then, with inert gas plasma, for example argon gas bombards the upper surface of copper interlayer 206b, to remove its lip-deep copper oxide layer, as shown in Figure 9.The copper of part is also etched in the lump together with the copper oxide layer in the etching process.Its result just as shown in Figure 9, the barrier layer on the sidewall of irrigation canals and ditches 212, serve as and stop that the copper atom that spills deposits the role who diffuses to oxide layer again this moment.
Consult Figure 10, a top conductor layer 230 (for example a bronze medal layer, aluminium lamination or tungsten metal level) then deposition gets on, and fills up lead irrigation canals and ditches 212 fully, and the method for inserting can be wherein a kind of of sputter or chemical vapour deposition technique.Afterwards, the conductor layer that surpasses the oxide layer upper surface removes with the autofrettage of chemistry or mechanical polishing again, is etch stop layer with oxide layer 210.After removing the copper oxide layer, the topping wire of formation promptly can have excellent electrical property to be connected with copper interlayer 206b.
In the prior art, copper is to be formed among the silicon nitride layer, and silicon nitride layer is the good barrier layer with respect layer of copper.Yet the dielectric constant of silicon nitride layer is more a lot of than oxidation floor height.Therefore the present invention, can allow to replace the ccontaining bottom copper conductor of silicon nitride layer with oxide layer owing to many one form the step of barrier layer clearance wall.When if silicon nitride layer 202 replaces with oxide layer, it is very similar implementing with method of the present invention.But barrier layer does not need to be etched into clearance wall.To prevent that copper from spreading out from the irrigation canals and ditches bottom.For example, as shown in figure 11, oxide layer 203 at first forms irrigation canals and ditches 204a, 204b and 204c with photoetching and etched processing procedure, forms barrier layer 221 again, then, and backfill copper metal again.Afterwards, remove the copper that exceeds of oxide layer 203 upper surfaces with the method for chemistry or mechanical polishing.Processing procedure with chemistry or mechanical polishing removes again, still form the photoresist pattern then as described above and cover a lead 206b with as interlayer, eat-back the copper of all the other irrigation canals and ditches again, then, again with the silicon nitride layer backfill, to fill up irrigation canals and ditches, but, if the top conductor layer also is a copper during as lead, just inappropriate, because, just have the problem of copper from the diffusion of irrigation canals and ditches bottom when if the barrier layer on upper strata is etched into clearance wall.
The above is preferred embodiment of the present invention only, is not in order to limiting protection scope of the present invention, does not allly break away from the equivalence of being finished under the disclosed spirit and changes or modify, and all should be included within protection scope of the present invention.
Claims (5)
1, the manufacture method of a kind of copper conductor dual damascene of line within lower floor, it is characterized in that: it comprises the steps:
(1) provides the semiconductor substrate;
(2) on this semiconductor substrate, form first dielectric layer; This first dielectric layer of patterning is to form most first irrigation canals and ditches in wherein;
(3) form a bronze medal layer, with these first irrigation canals and ditches of backfill; Impose chemistry or mechanical polishing to remove copper layer, to form most copper conductors above this first dielectric layer top;
(4) form mask pattern to cover a copper conductor, this copper conductor is predetermined as interlayer; With this mask pattern is etching mask, with the first half of remaining copper conductor of etching, to a preset thickness, has formed the bottom lead, and this bottom lead top stays second irrigation canals and ditches;
(5) remove this mask pattern; These second irrigation canals and ditches of backfill are to be same as the dielectric layer of the first dielectric layer material; Impose chemistry or mechanical polishing, to remove first dielectric layer, in order to the upper surface of exposed this interlayer above this interlayer;
(6) on this first dielectric layer, form second dielectric layer; This second dielectric layer of patterning to form the 3rd irrigation canals and ditches, exposes this interlayer and part bottom lead in the 3rd irrigation canals and ditches;
(7) on second dielectric layer behind this patterning, form a barrier layer; Impose an anisotropic etch method and on the sidewall of the 3rd irrigation canals and ditches, form clearance wall;
(8) with the upper surface of this interlayer of plasma bombardment, to remove the copper oxide layer;
(9) impose conductor layer backfill the 3rd irrigation canals and ditches; Impose chemistry or mechanical polishing, to remove the conductor layer of this second dielectric layer top, to form upper conductor layer.
2, the method for claim 1 is characterized in that: described first dielectric layer comprises silicon nitride layer at least.
3, the method for claim 1 is characterized in that: described second dielectric layer comprises silicon oxide layer at least.
4, the method for claim 1 is characterized in that: described barrier layer be selected from TiN, SiN, TaN, WN, Ta, W or Ti one of them.
5, the method for claim 1 is characterized in that: described conductor layer is to be selected from one of them of copper, tungsten or aluminium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01109625 CN1236485C (en) | 2001-03-13 | 2001-03-13 | Manufacture of double mosaic wire copper wire inside low layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01109625 CN1236485C (en) | 2001-03-13 | 2001-03-13 | Manufacture of double mosaic wire copper wire inside low layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1374690A CN1374690A (en) | 2002-10-16 |
| CN1236485C true CN1236485C (en) | 2006-01-11 |
Family
ID=4658040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 01109625 Expired - Lifetime CN1236485C (en) | 2001-03-13 | 2001-03-13 | Manufacture of double mosaic wire copper wire inside low layer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1236485C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1295776C (en) * | 2003-12-24 | 2007-01-17 | 上海宏力半导体制造有限公司 | Method for separately surface treatment to intermediate window and groove of double inlay |
| CN101661897B (en) * | 2008-08-27 | 2012-01-11 | 和舰科技(苏州)有限公司 | Interconnector structure and manufacturing method thereof |
| CN102569167A (en) * | 2010-12-16 | 2012-07-11 | 中芯国际集成电路制造(北京)有限公司 | Method for forming dual damascene structure |
-
2001
- 2001-03-13 CN CN 01109625 patent/CN1236485C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1374690A (en) | 2002-10-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1191623C (en) | Method for making double inlaying latch by using metal hard shielding layer | |
| US6380084B1 (en) | Method to form high performance copper damascene interconnects by de-coupling via and metal line filling | |
| CN1258216C (en) | Method for forming multi-layer conductive line | |
| US7417321B2 (en) | Via structure and process for forming the same | |
| CN1434509A (en) | Double embedded metal inner connection wire structure and making method thereof | |
| CN1947236A (en) | A method for depositing a metal layer on a semiconductor interconnect structure | |
| CN1192050A (en) | Semiconductor devices | |
| CN1477695A (en) | Method for making semiconductor device | |
| CN1286497A (en) | Conductive copper wire with redundant liner | |
| CN1707787A (en) | Semiconductor devices | |
| CN1708846A (en) | A method for depositing a metal layer on a semiconductor interconnect structure having a capping layer | |
| US8709906B2 (en) | MIM capacitor and associated production method | |
| KR20050015190A (en) | Metal Interconnection for avoiding void and method for fabricating the same | |
| CN1324677C (en) | Technqiue and structure for improveing adhesive capacity between layer of stopping etch and metl layer | |
| KR20010076659A (en) | Method for fabricating an interconnection layer for semiconductor device | |
| CN1873952A (en) | Method of manufacturing semiconductor device | |
| US7955971B2 (en) | Hybrid metallic wire and methods of fabricating same | |
| CN1236485C (en) | Manufacture of double mosaic wire copper wire inside low layer | |
| US8053359B2 (en) | Semiconductor device having a second level of metallization formed over a first level with minimal damage to the first level and method | |
| CN102054755B (en) | Interconnecting structure and formation method thereof | |
| CN101640184A (en) | Semiconductor device and method for manufacturing the same | |
| CN2793918Y (en) | Semiconductor device | |
| US20020127849A1 (en) | Method of manufacturing dual damascene structure | |
| CN1503344A (en) | Method for forming aluminium lead wire | |
| CN1207771C (en) | Double-insert process using oxidative wire layer as dielectric barrier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20060111 |