CN1207771C - Double-insert process using oxidative wire layer as dielectric barrier - Google Patents
Double-insert process using oxidative wire layer as dielectric barrier Download PDFInfo
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- CN1207771C CN1207771C CN 01144733 CN01144733A CN1207771C CN 1207771 C CN1207771 C CN 1207771C CN 01144733 CN01144733 CN 01144733 CN 01144733 A CN01144733 A CN 01144733A CN 1207771 C CN1207771 C CN 1207771C
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Abstract
The present invention relates to a double-insert process using oxidative wire layers as dielectric barrier layers. A double-insert opening is composed of a hole and a channel, wherein a metal conductor wire is exposed out of the hole which is surrounded by a first dielectric layer of low dielectric constants; the channel is positioned above the hole and surrounded by a second dielectric layer of low dielectric constants; an oxidative wire layer is formed to cover the first dielectric layer and the side walls of the second dielectric layer; then, a metal barrier layer is formed to cover the side walls and the bottom of the double-insert opening; subsequently, conducting layers are formed, and the double-insert opening is full of the conducting layers; finally, the conducting layers outside the area of the channel are removed, and the residual conducting layers in the double-insert opening become a double-insert structure. The present invention has the efficacy of increasing the adhesiveness between ILD layers and the metal barrier layer.
Description
Technical field
The invention relates to a kind of dual damascene (dual damascene) processing procedure, be particularly to a kind of double-insert process that uses oxidative wire layer as dielectric barrier layer, can increase inner layer dielectric layer (inter-leveldielectric, ILD) and the tack between the metal barrier layer.
Background technology
In manufacture of semiconductor, be contracted to the intraconnections demand of required increase below the 0.25 μ m for the live width design of matable assembly, metal level can be made into multilayer form, to be provided as multi-metal intra-connection, for example: (inter-level dielectric, ILD) interior edge buries the intraconnections that forms a kind of dual-damascene structure at inner layer dielectric layer.Traditional double-insert process has simple, critical dimension (the critical dimension of processing procedure, CD) advantage such as easy to control, and in order effectively to reduce material cost, the material of conductive layer/ILD layer has been improved as the combination of copper metal/low-k (low-K) material by the combination of aluminum metal/silica.But when carrying out copper wiring, copper atom is easy to diffuse in the adjacent low-k ILD layer, even can migrate in the silicon base, and then has influence on the electrical performance that is made in all component on the silicon base.In order to address this problem, current techniques is to make a metal barrier layer between copper metal and ILD layer, it can select Ta/TaN, Ti/TiN or W/WN material for use, in order to producing reciprocation between the ILD layer that prevents copper metal and low-k, and can increase tack between the ILD layer of copper metal and low-k.
Fig. 1-Fig. 3 is the generalized section that tradition is used the dual damascene technology of metal barrier layer.As shown in Figure 1, in semiconductor substrate 10 include a plain conductor 12, a dielectric separate layer 14, has an ILD layer 16 of low-k, the 2nd ILD layer 20, a hard mask layer 22 and the dual damascene opening 25 that an etching stopping layer 18, has low-k.Dual damascene opening 25 is communicated with by a hole 23 and a trench 24 to constitute, wherein hole 23 connects etching stopping layer 18, an ILD layer 16 and dielectric separate layer 14, so that the predetermined surface of plain conductor 12 exposes to the open air out, and trench 24 is positioned at hole 23 tops, and connects hard mask layer 22 and the 2nd ILD layer 20.
As shown in Figure 2, prior to deposition one even metal barrier layer 26 on the whole surface of substrate 10, with bottom and the sidewall that covers dual damascene opening 25, deposition one copper metal layer 28 on metal barrier layer 26 fills up dual damascene opening 25 to one predetermined altitudes until copper metal layer 28 again.
At last, as shown in Figure 3, utilize cmp (CMP) method, and stop layer as grinding with hard mask layer 22, copper metal layer 28 beyond trench 24 zones is removed, the metal barrier layer 26 that will expose to the open air is again removed, and the copper metal layer 28 that then remains in the dual damascene opening 25 becomes a dual-damascene structure.Its major defect is:
In conventional method, can't improve (outgassing) problem of giving vent to anger of an ILD layer 16 and an ILD layer 20, this not only can reduce the tack between ILD layer and the metal barrier layer 26, also can influence the reliability and the hardness of dual-damascene structure.
Summary of the invention
At above-mentioned defective, inventor's active research and practice create technical scheme of the present invention.
The purpose of this invention is to provide a kind of double-insert process that uses oxidative wire layer as dielectric barrier layer,, reach the purpose that increases the tack between ILD layer and the metal barrier layer by using oxidative wire layer as dielectric barrier layer.
The object of the present invention is achieved like this: a kind of double-insert process that uses oxidative wire layer as dielectric barrier layer is characterized in that: which comprises at least the following step:
(1) provides the semiconductor substrate, it includes at least one dual damascene opening, this dual damascene opening is made of a hole and a trench, this hole exposes a plain conductor to the open air and is surrounded by first dielectric layer of a low-k, and this trench is positioned at this hole top and is surrounded by second dielectric layer of a low-k;
(2) utilize oxidation process to form the sidewall that an oxidative wire layer covers this first dielectric layer and this second dielectric layer;
(3) form sidewall and the bottom that a metal barrier layer covers this dual damascene opening;
(4) form a conductive layer, to fill up this dual damascene opening;
(5) remove this trench zone conductive layer in addition, the conductive layer that then residues in this dual damascene opening becomes a dual-damascene structure.
This oxidative wire layer is arranged between this first dielectric layer and this metal barrier layer, and between this second dielectric layer and this metal barrier layer.This carries out after the oxidation process, and other includes a metallic reducing step, is formed at the line oxide layer on this plain conductor surface with removal.Before forming this metal barrier layer, other includes a deaeration step.The method of removing this conductive layer is the cmp processing procedure.It also includes another step: form a protective layer, to cover the top of this dual-damascene structure.This protective layer is SiN or SiC.Include a dielectric separate layer on the surface at this semiconductor-based end in addition, it is positioned at the bottom of this first dielectric layer.Include an etching stopping layer on the surface at this semiconductor-based end in addition, it is positioned at the top of this first dielectric layer.This etching stopping layer is to be selected from following any material to constitute: SiO
2, SiC, SiN, SRO or SiON.Include an antireflecting coating on the surface at this semiconductor-based end in addition, it is between this etching stopping layer and this second dielectric layer.Include a hard mask layer on the surface at this semiconductor-based end in addition, its definition is formed on the surface of this second dielectric layer.This hard mask layer is made of silicon nitride.This plain conductor is made of the copper metal.This first dielectric layer is made of the spin coating macromolecule.This first dielectric layer is made of chemical vapor deposition process.This first dielectric layer is made of the spin coating macromolecule.This second dielectric layer is made of chemical vapor deposition process.This metal barrier layer is selected from following any material and constitutes: Ti, Ta, TiN or TaN.This conductive layer is made of the copper metal.
Further specify below in conjunction with preferred embodiment and accompanying drawing.
Description of drawings
Fig. 1-Fig. 3 is the generalized section of traditional double damascene process.
Fig. 4-Figure 10 is the generalized section of double-insert process of the present invention.
Embodiment
Consult Fig. 4-shown in Figure 10, use oxidative wire layer of the present invention comprises the steps: as the double-insert process of dielectric barrier layer
As shown in Figure 4, semiconductor substrate 30 includes the 2nd ILD layer 362, a hard mask layer 42, a photoresist layer 44 and most dual damascene openings 50 that an ILD layer 361, an etching stopping layer 38, an antireflecting coating 40, that most plain conductors 32, dielectric separate layers 34, have low-k have low-k.Each dual damascene opening 50 is communicated with by a hole 46 and a trench 48 to constitute, and wherein hole 46 connects etching stopping layer 38, an ILD layer 361 and dielectric separate layer 34, so that the predetermined surface zone of plain conductor 32 exposes to the open air out; 48 of trench are positioned at hole 46 tops, connect hard mask layer 42, the 2nd ILD layer 362 and antireflecting coating 40.
In preferred embodiment, the material of the one ILD layer 361 can be the spin coating macromolecule of making via the spin coating processing procedure (SOP), as FLARE, SlLK, Parylene, PAE-11 or polyimides, or the advanced low-k materials of making via chemical vapor deposition process (CVD), as: black diamond, Coral, Aurora, GreenDot or other dielectric material.In the same manner, the material of an ILD layer 362 can be selected the advanced low-k materials that SOP or CVD make for use.
In addition, the manufacture method of dual damascene opening 50 belongs to design alternative, can reach via various feasible methods, does not just add detailed description at this.
As Fig. 5-shown in Figure 6, after photoresist layer 44 divested, carry out oxidation process, on the sidewall of an ILD layer 361 and an ILD layer 362, form an oxidative wire layer 52, carry out the wet-cleaned step again.Thus, oxidative wire layer 52 can be provided as a dielectric barrier layer, can increase the tack between the metal barrier layer of ILD layer and follow-up making.But, because oxidative wire layer 52 also can be formed on the exposed surface of plain conductor 32, with the contact resistance value that influences between the conductive layer of plain conductor 32 and follow-up making, therefore the copper reduction step must carried out additionally one, to get rid of plain conductor 32 lip-deep oxidative wire layers 52.
In addition, also to carry out one degasification (degas) step, the gas of being discharged of a removable ILD layer 361 and the 2nd ILD layer 362.
As shown in Figure 7, on the whole surface of substrate 30, deposit a metal barrier layer 54 equably, its material can be selected Ti, Ta, TiN, TaN or W/WN for use, one of its purpose is to be used for reciprocation between the conductive layer of isolated ILD layer and follow-up making, and two of its purpose is the tacks that are used for increasing between the conductive layer of ILD layer and follow-up making.
Then, as shown in Figure 8, can utilize the conductive layer 56 of PVD, CVD, plating or other deposition techniques one bronze medal metal, until filling up all dual damascene openings 50.
Then, as shown in Figure 9, utilize etching or grinding technique (as: CMP processing procedure) that conductive layer 56 beyond trench 48 zones and metal barrier layer 54 are removed, trim until the height that makes conductive layer 56 with hard mask layer 42.Thus, the conductive layer 56 that remains in the dual damascene opening 50 becomes a dual-damascene structure 56 '.
At last; as shown in figure 10; go up deposition one protective layer 58 in substrate 30 surfaces; its material can be selected SiN or SiC for use; to cover the top of dual-damascene structure 56 '; be used for preventing the oxidative phenomena of dual-damascene structure 56 ', and the atom/ions diffusion that prevents dual-damascene structure 56 ' is to the dielectric layer of follow-up making.In addition, need, can repeat above-mentioned double-insert process and make other dual-damascene structure according to processing procedure.
Compared to conventional art, method of the present invention provides oxidative wire layer 52 as dielectric barrier layer, can increase the tack between ILD layer 361,362 and the metal barrier layer 54, and the influence that phenomenon produced of giving vent to anger that can slow down ILD layer 361,362, can also promote the hot reliability and the hardness of dual-damascene structure 56 '.In addition, the making of oxidative wire layer 52 only need utilize general oxidation process, therefore has the effect of saving the processing procedure cost.
Though the present invention discloses as above with preferred embodiment, so it is not in order to limiting the present invention, anyly has the knack of this skill person, and without departing from the spirit and scope of the present invention, a little change and the retouching done all belongs within protection scope of the present invention.
Claims (20)
1, a kind of double-insert process that uses oxidative wire layer as dielectric barrier layer is characterized in that: which comprises at least the following step:
(1) provides the semiconductor substrate, it includes at least one dual damascene opening, this dual damascene opening is made of a hole and a trench, this hole exposes a plain conductor to the open air and is surrounded by first dielectric layer of a low-k, and this trench is positioned at this hole top and is surrounded by second dielectric layer of a low-k;
(2) utilize oxidation process to form the sidewall that an oxidative wire layer covers this first dielectric layer and this second dielectric layer;
(3) form sidewall and the bottom that a metal barrier layer covers this dual damascene opening;
(4) form a conductive layer, to fill up this dual damascene opening;
(5) remove this trench zone conductive layer in addition, the conductive layer that then residues in this dual damascene opening becomes a dual-damascene structure.
2, use oxidative wire layer according to claim 1 is as the double-insert process of dielectric barrier layer, it is characterized in that: the oxidative wire layer of this step (2) is arranged between this first dielectric layer and this metal barrier layer, and between this second dielectric layer and this metal barrier layer.
3, use oxidative wire layer according to claim 2 is characterized in that as the double-insert process of dielectric barrier layer: this step (2) is carried out after the oxidation process, and other includes a metallic reducing step, is formed at the line oxide layer on this plain conductor surface with removal.
4, use oxidative wire layer according to claim 1 is characterized in that as the double-insert process of dielectric barrier layer: this step (3) is before forming this metal barrier layer, and other includes a deaeration step.
5, use oxidative wire layer according to claim 1 is characterized in that as the double-insert process of dielectric barrier layer: the method that this step (5) is removed this conductive layer is the cmp processing procedure.
6, use oxidative wire layer according to claim 1 is characterized in that as the double-insert process of dielectric barrier layer: it also includes another step (6): form a protective layer, to cover the top of this dual-damascene structure.
7, use oxidative wire layer according to claim 6 is characterized in that as the double-insert process of dielectric barrier layer: this protective layer is SiN or SiC.
8, use oxidative wire layer according to claim 1 is characterized in that as the double-insert process of dielectric barrier layer: include a dielectric separate layer on the surface at the semiconductor-based end of this step (1) in addition, it is positioned at the bottom of this first dielectric layer.
9, use oxidative wire layer according to claim 1 is characterized in that as the double-insert process of dielectric barrier layer: include an etching stopping layer in addition on the surface at the semiconductor-based end of this step (1), it is positioned at the top of this first dielectric layer.
10, use oxidative wire layer according to claim 9 is characterized in that as the double-insert process of dielectric barrier layer: this etching stopping layer is to be selected from following any material to constitute: SiO
2, SiC, SiN, SRO or SiON.
11, use oxidative wire layer according to claim 9 is characterized in that as the double-insert process of dielectric barrier layer: include an antireflecting coating on the surface at this semiconductor-based end in addition, it is between this etching stopping layer and second dielectric layer.
12, use oxidative wire layer according to claim 1 is characterized in that as the double-insert process of dielectric barrier layer: include a hard mask layer in addition on the surface at the semiconductor-based end of this step (1), its definition is formed on the surface of this second dielectric layer.
13, use oxidative wire layer according to claim 12 is characterized in that as the double-insert process of dielectric barrier layer: this hard mask layer is made of silicon nitride.
14, use oxidative wire layer according to claim 1 is characterized in that as the double-insert process of dielectric barrier layer: this plain conductor is made of the copper metal.
15, use oxidative wire layer according to claim 1 is characterized in that as the double-insert process of dielectric barrier layer: this first dielectric layer is made of the spin coating macromolecule.
16, use oxidative wire layer according to claim 1 is characterized in that as the double-insert process of dielectric barrier layer: this first dielectric layer is made of chemical vapor deposition process.
17, use oxidative wire layer according to claim 1 is characterized in that as the double-insert process of dielectric barrier layer: this first dielectric layer is made of the spin coating macromolecule.
18, use oxidative wire layer according to claim 1 is characterized in that as the double-insert process of dielectric barrier layer: this second dielectric layer is made of chemical vapor deposition process.
19, use oxidative wire layer according to claim 1 is characterized in that as the double-insert process of dielectric barrier layer: this metal barrier layer is selected from following any material and constitutes: Ti, Ta, TiN or TaN.
20, use oxidative wire layer according to claim 1 is characterized in that as the double-insert process of dielectric barrier layer: this conductive layer is made of the copper metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01144733 CN1207771C (en) | 2001-12-24 | 2001-12-24 | Double-insert process using oxidative wire layer as dielectric barrier |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01144733 CN1207771C (en) | 2001-12-24 | 2001-12-24 | Double-insert process using oxidative wire layer as dielectric barrier |
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| Publication Number | Publication Date |
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| CN1428838A CN1428838A (en) | 2003-07-09 |
| CN1207771C true CN1207771C (en) | 2005-06-22 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 01144733 Expired - Lifetime CN1207771C (en) | 2001-12-24 | 2001-12-24 | Double-insert process using oxidative wire layer as dielectric barrier |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7057287B2 (en) * | 2003-08-21 | 2006-06-06 | International Business Machines Corporation | Dual damascene integration of ultra low dielectric constant porous materials |
| US20050064701A1 (en) * | 2003-09-19 | 2005-03-24 | International Business Machines Corporation | Formation of low resistance via contacts in interconnect structures |
| US7193327B2 (en) * | 2005-01-25 | 2007-03-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier structure for semiconductor devices |
| CN102569167A (en) * | 2010-12-16 | 2012-07-11 | 中芯国际集成电路制造(北京)有限公司 | Method for forming dual damascene structure |
| CN106531688A (en) * | 2016-11-30 | 2017-03-22 | 武汉新芯集成电路制造有限公司 | Preparation method for through silicon via |
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- 2001-12-24 CN CN 01144733 patent/CN1207771C/en not_active Expired - Lifetime
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Granted publication date: 20050622 |