CN1231972C

CN1231972C - Static charging seal ring for system static protection

Info

Publication number: CN1231972C
Application number: CN 02120109
Authority: CN
Inventors: 王泰和
Original assignee: Sunplus Technology Co Ltd
Current assignee: Sunplus Technology Co Ltd
Priority date: 2002-05-17
Filing date: 2002-05-17
Publication date: 2005-12-14
Anticipated expiration: 2022-05-17
Also published as: CN1458690A

Abstract

The present invention relates to an electrostatic charging seal ring for system electrostatic prevention. The present invention is arranged around the outer margin of a basal plate of an integrated circuit wafer. The present invention mainly comprises a lower metal layer and an upper metal layer, wherein the lower metal layer is arranged on the basal plate through a first insulation layer, and is electrically connected with the first electrode of a capacitor on the basal plate through a contact window. The upper metal layer is arranged on the lower metal layer through a second insulation layer, and is electrically connected with the second electrode of the capacitor. The upper metal layer is connected with a first system electric potential. The lower metal layer is connected with a second system electric potential. The basal plate is connected with the second system electric potential. Therefore, the present invention can maintain the voltage difference between a high system electric potential Vdd and a low system electric potential Vss at a constant value, can not make the integrated circuit wafer reset or locked, and can effectively prevent the integrated circuit wafer from being affected by static electricity.

Description

Static charging seal ring with system static protection

Technical field

The invention belongs to the technical field of the electrostatic defending of integrated circuit (IC) wafer, especially refer to a kind of static charging seal ring with system static protection.

Background technology

Press, integrated circuit (IC) wafer (IC Chip) is owing to include extremely many precision electronic elements, therefore, very easily be subjected to the influence of environment noise such as static for example and produce misoperation or can't work at all, for example, when system static protection test (ESD Test), when a large amount of static are beaten on the product of LCD (LCD) integrated circuit (IC) wafer, the picture of LCD can disappear, this phenomenon is tested through actual the measurement, learn it is because integrated circuit (IC) wafer can be via the mode of routing (Wire bonding) path or an induction (Field induce), very big noise is coupled to substrate, on high potential Vdd of system and the electronegative potential Vss of system, cause disabler or circuit to be fastened lock (Latch-up).

For aforesaid phenomenon is described, please refer to shown in the equivalent electric circuit of Fig. 1, when noise is coupled to integrated circuit (IC) wafer, this noise can enter into substrate via weld pad 11 (Pad), because therefore substrate connected system electronegative potential Vss causes Vss toward rising or past decline, but Vdd can't be coupled to noise immediately, thereby the pressure reduction of Vdd and Vss just changes thereupon, even causes Vdd lower than Vss, causes integrated circuit (IC) wafer to be reset or fastens pinning.By being as can be known, how to prevent effectively that integrated circuit (IC) wafer from avoiding being subjected to the influence of static, be a problem that needs to be resolved hurrily in fact.

Summary of the invention

The object of the present invention is to provide a kind of static charging seal ring, avoid being subjected to the influence of static effectively to prevent integrated circuit (IC) wafer with system static protection.

For achieving the above object, the static charging seal ring with system static protection provided by the invention around the substrate outer rim that is arranged on integrated circuit (IC) wafer, is formed with at least one electric capacity on this substrate, and this static charging seal ring mainly comprises:

One lower floor's metal level is arranged on this substrate by one first insulating barrier, and is electrically connected to first electrode of this at least one electric capacity;

One upper metal layers is arranged on this lower metal layer by one second insulating barrier, and is electrically connected to second electrode of this at least one electric capacity;

Wherein, this upper metal layers connects first system's current potential, and this lower metal layer connects second system's current potential, and this base is pulled and connected second system's current potential.

Wherein also comprise a switching metal level, be set up in parallel on the same plane of this lower metal layer, make this upper metal layers be electrically connected to this switching metal level earlier, be electrically connected to second electrode of this at least one electric capacity again.

This lower metal layer wherein is electrically connected to first electrode of this at least one electric capacity with contact hole.

Wherein this upper metal layers is electrically connected to this switching metal level with through hole.

Wherein this switching metal level is electrically connected to second electrode of this at least one electric capacity with contact hole.

Wherein this switching metal level connects first system's current potential.

Wherein be formed with doped region on this substrate with first electrode as this at least one electric capacity.

Wherein be formed with compound crystal silicon layer in this first insulating barrier with second electrode as this at least one electric capacity.

Wherein this substrate is a p type substrate, its connected system electronegative potential, and this second system current potential is the electronegative potential Vss of system, this first system current potential is the high potential Vdd of system.

Wherein this doped region is N ⁺Doped region.

Wherein this substrate is a n type substrate, its connected system high potential, and this second system current potential is the high potential Vdd of system, this first system current potential is the electronegative potential Vss of system.

For further understanding structure of the present invention, feature and purpose thereof, elaborate with accompanying drawing and preferred embodiment below.

Description of drawings

Fig. 1 goes into the connection equivalent circuit diagram of weld pad for the output of integrated circuit.

Fig. 2 is the integrated circuit (IC) wafer schematic layout pattern with static charging seal ring of system static protection of the present invention.

Fig. 3 is the enlarged drawing of overlooking of the static charging seal ring of system static protection of the present invention.

Fig. 4 is a profile of the static charging seal ring of system static protection of the present invention.

Fig. 5 is another profile of the static charging seal ring of system static protection of the present invention.

Fig. 6 is the connection equivalent circuit diagram that weld pad is gone in the output of integrated circuit with static charging seal ring of system static protection of the present invention.

Embodiment

A relevant preferred embodiment with static charging seal ring of system static protection of the present invention, the schematic layout pattern of the integrated circuit (IC) wafer that reference earlier is shown in Figure 2, wherein, be provided with weld pad 21 at Waffer edge, the wafer outer rim then is surrounded with a seal ring 22 (Seal ring).

This seal ring 22 is made of layer of metal at least, Fig. 3 show one have double layer of metal seal ring 22 overlook enlarged drawing, it is that a metal level M1 of lower floor and a upper metal layers M2 are set on substrate 31 in regular turn, on the same plane of this lower metal layer M1, be set up in parallel a switching metal level M2 ' in addition, for convenience of description, the substrate 31 of this preferred embodiment is a p type substrate, its connected system electronegative potential Vss, and this upper metal layers M2 connected system high potential Vdd, this lower metal layer M1 electronegative potential Vss of system, this switching metal level M2 ' connected system high potential Vdd.

For the structure of this seal ring 22 is described, please refer to the profile at 1-1 ' tangent line shown in Figure 4, wherein, on p type substrate 31, be formed with mix formed source/

drain area

45 and 46 by N+, then be formed with a compound crystal silicon layer in the insulating barrier 41 on the substrate 31 with as gate district 47, so constitute a capacitance structure, and the upper metal layers M2 of seal ring 22 is arranged on this lower metal layer M1 via an insulating barrier 42, this lower metal layer M1 also is arranged on the substrate 31 by this insulating barrier 41, and this lower metal layer M1 is electrically connected the source/

drain area

45 and 46 of substrate 31 with contact hole 43 (Contact).

Fig. 5 then is presented at the profile of 2-2 ' tangent line, wherein, the upper metal layers M2 of seal ring 22 is arranged on this switching metal level M2 ' via insulating barrier 42, and this upper metal layers M2 is electrically connected this switching metal level M2 ' with through hole 49 (Via), this switching metal level M2 ' is arranged on the substrate 31 by insulating barrier 41, and should be electrically connected this gate district 47 with contact hole 48 by switching metal level M2 '.

Structure with above-mentioned seal ring 22, the upper metal layers M2 of seal ring 22 is electrically connected gate district 47 as can be known, lower metal layer M1 then is electrically connected to source/

drain area

45 and 46, and because these gate districts 47 constitute an electric capacity with source/

drain area

45 and 46, wherein gate district 47 is an electrode of electric capacity, and source/

drain area

45 and 46 are another electrode of electric capacity.Upper metal layers M2 connects Vdd again, lower metal layer M1 then connects Vss, as shown in Figure 2, this seal ring 22 is equivalent to provide an electric capacity between Vdd and Vss, its equivalent electric circuit as shown in Figure 6, circuit according to this, when noise is coupled to integrated circuit (IC) wafer, noise enters into substrate via weld pad 21, cause past rising of the electronegative potential Vss of system or past decline, so owing to being connected with the electric capacity 23 that is provided by seal ring 22 between Vss and Vdd, so the high potential Vdd of system is also with past rising or past decline thereupon, therefore, though whole current potential can be toward rising or past decline, the pressure reduction of Vdd to Vss is to keep a fixed value, so, just can not cause integrated circuit (IC) wafer to be reset or to fasten pinning, and can prevent effectively that integrated circuit (IC) wafer from avoiding being subjected to the influence of static.

Above embodiment is that the seal ring 22 with double layer of metal is the example explanation, so in practical application, seal ring 22 can have two-layer more than, at this moment, only need the metal level of the superiors is connected Vdd, all the other metal levels connect Vss and get final product, the substrate 31 of the foregoing description is a p type substrate again, and be n type substrate as this substrate 31, substrate connected system high potential Vdd then, the upper metal layers M2 connected system electronegative potential Vss of this seal ring 22, this lower metal layer M1 high potential Vdd of system, this switching metal level M2 ' connected system electronegative potential Vss.

It should be noted that above-mentioned many embodiment give an example for convenience of explanation, the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.

Claims

1. the static charging seal ring with system static protection around the substrate outer rim that is arranged on integrated circuit (IC) wafer, is formed with at least one electric capacity on this substrate, and this static charging seal ring mainly comprises:

One switching metal level is set up in parallel on the same plane of this lower metal layer, makes this upper metal layers be electrically connected to this switching metal level earlier, is electrically connected to second electrode of this at least one electric capacity again;

2. static charging seal ring as claimed in claim 1, it is characterized in that, this lower metal layer is electrically connected to first electrode of this at least one electric capacity with contact hole.

3. static charging seal ring as claimed in claim 1 is characterized in that, this upper metal layers is electrically connected to this switching metal level with through hole.

4. static charging seal ring as claimed in claim 1 is characterized in that, this switching metal level is electrically connected to second electrode of this at least one electric capacity with contact hole.

5. static charging seal ring as claimed in claim 1 is characterized in that, this switching metal level connects first system's current potential.

6. static charging seal ring as claimed in claim 5 is characterized in that, is formed with doped region on this substrate with first electrode as this at least one electric capacity.

7. static charging seal ring as claimed in claim 6 is characterized in that, is formed with compound crystal silicon layer in this first insulating barrier with second electrode as this at least one electric capacity.

8. static charging seal ring as claimed in claim 1 is characterized in that, this substrate is a p type substrate, its connected system electronegative potential, and this second system current potential is the electronegative potential Vss of system, this first system current potential is the high potential Vdd of system.

9. static charging seal ring as claimed in claim 8 is characterized in that, this doped region is N ⁺Doped region.

10. static charging seal ring as claimed in claim 1 is characterized in that, this substrate is a n type substrate, its connected system high potential, and this second system current potential is the high potential Vdd of system, this first system current potential is the electronegative potential Vss of system.