CN1667827A - Protection device of semiconductor circuit with electrostatic discharge protecting circuit - Google Patents
Protection device of semiconductor circuit with electrostatic discharge protecting circuit Download PDFInfo
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- CN1667827A CN1667827A CN 200510009038 CN200510009038A CN1667827A CN 1667827 A CN1667827 A CN 1667827A CN 200510009038 CN200510009038 CN 200510009038 CN 200510009038 A CN200510009038 A CN 200510009038A CN 1667827 A CN1667827 A CN 1667827A
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
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Abstract
The invention relates to an electrostatic discharge (ESD) protection apparatus for a semiconductor circuit, which has at least an ESD protection assembly (SD1-SD4, RS) connected in between a substrate contacting zone (SK1) and a ground potential connection (VSS), and electrically connected to the substrate contacting zone (SK1). The ESD protection assembly is designed as an ESD protection diode (SD1-SD4) type or an ESD protection transistor (ST1, ST2) type; or a resistor (RS) or the ESD protection transistor (ST1) is connected between the substrate contacting zone (SK1) and the ground potential connection (VSS) as the ESD protection assembly, additionally, the ESD protection diode (SD2) type or the ESD protection transistor (ST2)is connected between the substrate contacting zone (SK1) and a supply voltage potential connection (VDD).
Description
Technical field
The present invention is the esd protection device of relevant semiconductor, particularly integrated circuit.
Background technology
Known integrated circuit (ICs) may be subjected to grievous injury or may be destroyed because of the Electrostatic Discharge incident.The electric charge relevant with discharge can be made in many ways, for example by lightning, and as the friction between the insulator of synthetic fibers clad can example, or by contacting with the automatic chip processing unit.What no matter when ESD voltage for example was coupled to that I/O connects (the signal input and the output of integrated circuit) or voltage connects is one or more, infringement or destroy the there all may take place or appear at.
Because as be connected to voltage difference during the esd discharge between the doped region of n well of different service voltages, the electronics flashover also can betide on these aspects.As long as the electric current in these situations keeps being restricted to being lower than the following value of certain threshold level, this processing is reversible and does not have the generation of destruction.This is guaranteed especially that in the high impedance flashover property it can observedly reach on the point of specific currents position standard in these.Yet if current density is higher during this flashover, Low ESR response meeting is because of the triggering of parasitic diode transistor produces, and causes the rapid rising of electric current and produces local the thawing and irreversible destruction.One of critical point place typical measurement system as these selects to guarantee that parasitic transistor can not penetrate (punchthrough) effect because of what is called or other breakdown effect collapses by suitably separating between the n well area.Yet this (destructiveness) low impedance state not only may be because of these mechanisms but also may be accurate by for example producing because of the potential distribution partial substrates current potential that causes change is increased when esd event takes place because of the driving of parasitic diode transistor position.Because general esd protection notion, for example because the operating voltage difference, so service voltage network (VDD network) can not be via back-to-back parallel diode or double linkage is directly protected each other.Therefore, esd pulse system is dissipated via the earth potential rail (VSS rail) that produces remarkable voltage drop.If substrate contacts is connected VSS network so far, it is accurate that then these voltage drops may cause above-mentioned driving position.
Therefore, must provide the device of the esd protection in semiconductor circuit or the integrated circuit, unlikelyly be subjected to this overvoltage and because of its infringement that produces and destruction to protect them.In the up-to-date integrated circuit, these circuit must have the voltage that reaches some Kv and reach the ESD resistance of the electric current on some amperes big or small rank.Therefore, must avoid between the voltage connection or the voltage drop on the Bus Wire, and keep the Bus Wire impedance very low.In this situation, Bus Wire represents also to mean the service voltage rail.
One known esd protection device is to be disclosed among early stage prospectus DE 199 44489 A1 of Germany; the fine jade explanation is used for the signal input of semiconductor device and the esd protection device of output; wherein semiconductor substrate system is connected to the substrate bus so that apply the grade slab current potential to this semiconductor substrate; and the zone of the semiconductor doping in this semiconductor substrate system is connected to power bus so that apply the ground power potential to this semiconductor doping zone, and a parasitic diode is formed between this power bus and this substrate bus.The service voltage current potential can be applied to the semiconductor device that is provided the I/O pad via supplying with bus.Moreover in the known esd protection device example, forward bias voltage drop avalanche diode system is connected between substrate bus and the power bus, and additional forward bias voltage drop ESD diode is to be connected between power bus and the supply bus.Known esd protection device provides and reaches on the power bus protection of the ESD infringement that load produces on the bus of two places just on the substrate bus.During the general operation, these total linear systems are in same potential.Early stage prospectus discloses I/O and supplies with in the network between bus, just the ESD notion of the protection of signal input and output only.Yet; known esd protection device and substrate contacts inapplicable and when also not being designed to provide reliably protecting to avoid esd event to take place; well contact or guard ring contact, the infringement of the doped region in the nucleus of its supply lines or semiconductor circuit or destruction.
Fig. 1 shows a further known esd protection device, and wherein p+ doped region (being used as substrate contacts) and two n well area system is formed among the substrate S.P+ substrate contacts system is electrically connected to earth potential VSS.The one n well area system does electronics with the first service voltage current potential VDDP and contacts, and the 2nd n well area is to do electronics with the second service voltage current potential VDD to contact.The first parasitic bus resistance R1 and comprise one first esd protection assembly ESD1 and a parasitic or clear and definite parallel circuits system that had both deposited diode D1 is series at that earth potential connects VSS and the first service voltage current potential connects between the VDDP.The second parasitic bus resistance R2 and comprise one second esd protection assembly ESD2 and a parallel circuits parasitic or that clearly be provided diode D2 is series at equally that earth potential connects VSS and the second service voltage current potential connects between the VDD.As above-mentioned; when one of this known esd protection device shortcoming system betided first service voltage current potential connection VDDP place when esd event, positive potential was manufactured in earth potential by the part and connects VSS with respect to reaching with respect to parasitic bus resistance R1 place because of the dissipation of electric current via esd protection assembly ESD1.This causes parasitic diode transistor to be driven.
In order to constrain or to suppress this drivings relevant issues, quite big isolation be formed on critical, between the parasitic diode transistor electrode with its gain factor of abundant reduction β.Decide on various service voltage VDD and VDDP, for example this abundant separation number is about 8 microns for 0.13 micron technology in abutting connection with the n well.This quite big required isolation quite limits the further miniaturization of semiconductor circuit or integrated circuit.
Avoid the opposing party's genealogy of law of driving to connect a coupling assembly between two service voltages connection VDD and VDDP.Yet these need quite big quantity space therefore to be only applicable to very limited degree, avoid on the other hand driving reaching how much that further minimize semiconductor circuit.In addition, these coupling assemblies are located and transmitted to how much quarantine domain than difficulty.
Therefore, one of the present invention purpose system provides a kind of being designed simply to reach the saving space and can guarantee when esd event takes place, the esd protection device of the esd protection improvement of infringement of the nucleus of semiconductor circuit or destruction.One of this example specific purpose system provides the substrate contacts of semiconductor circuit nucleus, the esd event protection of well contact or guard ring contact.
This purpose system reaches by the esd protection device that has according to claim 1 characteristic.
Summary of the invention
Esd protection device system according to the present invention is designed in the semiconductor circuit, particularly integrated circuit.Esd protection device and semiconductor circuit can be formed in substrate or the epitaxial loayer.One first doped region of semiconductor circuit tool and at least two second doped regions.First doped region is electrically connected at least one earth potential and connects, and second doped region is electrically connected to the connection of service voltage current potential.The present invention's one main concept system connects esd protection circuit between first doped region and earth potential connection.Because this esd protection circuit is connected between first doped region and earth potential connect at least, so this is effectively reached circuit not suffer damage when Safety Design protects semiconductor device to place esd event to take place or destroys.Especially but not only individually, when first doped region was placed in the semiconductor circuit nucleus, the present invention can avoid the infringement of this semiconductor circuit.Moreover one of the present invention major advantage is that the ESD load betides in the semiconductor circuit example between two service voltage buses, and the esd protection assembly system that is connected to semiconductor circuit according to the present invention can avoid the infringement in the esd event.In conjunction with the esd protection assembly (it can be provided) of Fig. 1, this can reach rather good esd protection.When esd event took place, the present invention can provide esd protection circuit to intercept or presents by increasing resistance when the positive voltage of earth potential junction increases, and therefore can avoid during the esd discharge connection because of parasitic transistor produced.Moreover, can simply reach according to the present invention's esd protection device and to save the space mode and make, even make its essence that the semiconductor circuit or the integrated circuit of accessible miniaturization are provided.
The special tool advantage of esd protection circuit is designed to make first doped region, and particularly the contact of one of first doped region electronics has the minimum value of these current potentials of connection of service voltage current potential and the appearance of earth potential junction.This can provide semiconductor circuit to the rather good protection because of destruction that esd event produces.
Found that the tool advantage is that esd protection circuit has an at least one esd protection diode or an esd protection transistor.These protection assemblies can effectively avoid driving parasitic transistor, and it can be saved the space mode and carries out.Moreover this facilitates suitable simple designs configuration.
In another preferred embodiment, can be used the esd protection diode anode and the negative electrode system thereof that contact with first doped region to be electrically connected to earth potential.Moreover the current path system of the esd protection transistor that can be used is connected between first doped region and the earth potential, and its grid connects and substrate connection system is electrically connected to first doped region.So circuit system makes that semiconductor circuit is effectively protected not to be subjected to the destruction that produces because of esd event.
One to have advantage embodiment characteristic be that esd protection circuit has and is connected to first doped region and the earth potential first esd protection assembly between connecting, and be connected to first doped region and the two service voltages second esd protection assembly between one of connecting.When critical esd event took place, the second esd protection assembly can be electrically connected to the two service voltage current potentials that present electronegative potential and one of connect.
Resistor, particularly non-reacted resistor, or esd protection transistor can be connected the first esd protection assembly of being used as between first doped region and earth potential connection.Also can provide an esd protection diode or esd protection transistor to be connected to first doped region and the first or second service voltage current potential second esd protection assembly between connecting.This is met the demands the esd protection circuit of can variable form manufacturing and can different component design.Therefore, for example first doped region system is connected isolation by resistor with earth potential.During the general operation, also can guarantee that electric current, particularly substrate current do not need any critical voltage to fall and flow away via resistor; in the esd event; drive current is lowered and the first doped region place, particularly substrate, and the voltage system of well or guard ring contact position is by the esd protection diode clamp.This embodiment can make safety and ball bearing made using, suffers damage in the time of can avoiding semiconductor device to place esd event to take place by it or destroys.The esd protection device is in fact quite simple and can be designed fast, and escapable cost is carried out.
First doped region can be provided is substrate form and be in contact with it with the contact of substrate contacts or guard ring at least.It is the well contact form that second doped region also can be provided.One of two second doped regions can be electrically connected to the first service voltage current potential and connect, and another of two second doped regions can be electrically connected to the second service voltage current potential and connect.
When esd event took place, the second esd protection assembly can preferablely be connected to the two service voltage current potentials that present electronegative potential and one of connect.Can provide semiconductor circuit best esd protection, wherein irreversible breaking only betides in the esd discharge incident in the load direction.
If semiconductor circuit has some first doped regions or some contact points with first doped region or doped region; then when esd event takes place, only be connected to first doped region of earth potential connection for being placed in each example in abutting connection with the parasitic transistor person via the esd protection assembly.This can guarantee only to be placed in the effective esd protection part of need according to the present invention's esd protection device.This requires the optimization esd protection to minimum space, and can quite save into original implementation semiconductor circuit or integrated circuit.
Can provide protectiveness to isolate and be formed between the contact of first doped region.Both having deposited contact may cause parasitic element to be driven.Moreover (its quilt is with same area is not relevant not to be placed on second doped region; In this example, territory system is regarded as having the zone of different service voltage current potentials) between be contacted with when isolating more near the border, territory and may cause equally driving than protectiveness.
Protectiveness isolation system comes control by the ESD resistance of parasitic diode transistor.When the distance between second doped region of territory boundary increased, ESD resistance system increased.For example, if the protection assembly that any esd pulse of the so high feasible generation of this distance or ESD resistance is provided via not needing parasitic element to be driven dissipates, then no longer need the esd protection assembly.The ESD resistance of parasitic element is also decided on implant and doping section.Be installed up to the geometry devices of no minimum protectiveness isolation by restriction additional ESD protection assembly, but the optimization requisite space ratio and the esd protection assembly that must be designed.Yet, should notice that the present invention does not expect that minimizing protectiveness isolates.Another major advantage system of the present invention can be used to other structure because of the relevant range, so this isolation is also quite big.In the esd event, especially with substrate, what well or guard ring contact position form were done contact both deposits first doped region, is to be without prejudice by the esd protection component protection of corresponded manner contact.
Another tool advantage embodiment characteristic based semiconductor circuit has some protected first doped regions that are not subjected to esd event.These first doped regions respectively are electrically connected to the earth potential bus.This earth potential bus is preferable via the esd protection assembly, and particularly esd protection diode or esd protection transistor are electrically connected at least one earth potential pad.
Can provide esd protection circuit to be electrically connected at least one service voltage current potential connects.This has advantage avoids the destroyed some proper circuit of semiconductor circuit by suitably using the esd protection assembly can make esd event and take place the time.
Description of drawings
The some embodiment of the present invention will be explained in more detail in hereinafter with reference to sketch map, wherein:
Fig. 1 shows the sketch map of known esd protection device;
Fig. 2 shows esd protection device first embodiment according to the present invention;
Fig. 3 shows esd protection device second embodiment according to the present invention;
Fig. 4 shows esd protection device the 3rd embodiment according to the present invention;
Fig. 5 shows esd protection device the 4th embodiment according to the present invention;
Fig. 6 shows esd protection device the 5th embodiment according to the present invention;
Fig. 7 shows the esd protection device details plane graph according to the present invention;
Fig. 8 shows esd protection device the 6th embodiment according to the present invention.
Among the figure, identical or functional same components is to be provided same reference numeral.
Embodiment
Fig. 2 shows esd protection device first embodiment according to the present invention.Simplified shows explains very important these semiconductor circuits or integrated circuit components to the present invention.The first well area W1 and second well area W2 system quilt row become second doped region in the p conductive substrate.Among the embodiment, well area W1 and W2 are the n conduction type.The one n well area W1 system is electrically connected to the first service voltage current potential and connects VDDP, and the 2nd n well area W2 system is electrically connected to second service voltage current potential connection VDD.Moreover first doped region system is formed the substrate S that is used as semiconductor circuit, and is in contact with it by substrate contacts SK1.Substrate contacts SK1 is the p+ area format in embodiment.First doped region also can be provided is the well form and/or contact by guard ring.Border, the territory system of semiconductor circuit settles in its mode of passing through substrate contacts SK1.According to the present invention, substrate contacts SK1 system is electrically connected to earth potential via esd protection circuit ESD_SS and connects VSS.Moreover the esd protection circuit ESD_SS system among the embodiment is electrically connected to first and second service voltage current potential respectively and connects VDDP and VDD.According to the present invention's substrate contacts SK1 and earth potential connect be situated between among the esd protection circuit ESD_SS between VSS connect system be provided in be placed in may the parasitic transistor centre near.Esd protection assembly ESD_SS system reduces the current potential of substrate contacts SK1 to connecting VDD, the potential minimum at VSS and VDDP place.This compression esd event pursues when taking place and increases the driving that the VSS current potential is produced, and avoids the breech lock during the general operation.
Fig. 3 shows esd protection device second embodiment according to the present invention.With respect to embodiment illustrated in fig. 2, n well area W1 system is electrically connected to the first service voltage current potential and connects VDD1, and the 2nd n well area W2 system is electrically connected to second service voltage current potential connection VDD2.Border, the territory system of semiconductor circuit is placed and makes it can pass through substrate contacts SK1.Another substrate contacts SK2 system is formed on has minimum protectiveness isolation D
ProtectionSubstrate S in.Should notice that at this this is the icon among the embodiment.The border, territory also can be placed on some other some place, and this contact can be transferred, and other contact also can be provided.First substrate contacts SK1 system is electrically connected to earth potential connection VSS via the esd protection diode SD1 that is connected between substrate contacts SK1 and earth potential connection VSS.The anode of esd protection diode SD1 is electrically connected to substrate contacts, and the negative electrode of esd protection diode SD1 is electrically connected to earth potential network VSS.Not having this esd protection diode is connected between the second substrate contacts SK2 and the earth potential connection VSS.
The method of connection esd protection diode between substrate contacts SK1 and earth potential connection VSS according to the present invention is to be implemented in to be placed in and may to know these substrate contacts places near the parasitic transistor centre.When esd event took place, connecting in abutting connection with these substrate contacts SK1 of parasitic element via the esd protection diode was that compression is by increasing the driving that the VSS current potential is produced to earth potential connection VSS.Compared to prior art, this feasible one-tenth more near n well area W1 and W2, therefore can save on the chip or quite a lot of space in the integrated circuit.The anode of esd protection diode SD1 connects system and is electrically connected to p+ substrate contacts SK1, and its negative electrode system is electrically connected to earth potential network VSS.During the general operation and when ESD takes place, during example during should be general operation, this is via along esd protection diode SD1 dissipation substrate current partially.When betiding esd event especially, the current potential of VSS network increases system and is intercepted.
When esd event took place, voltage system was resulted from the substrate node place that quite is lower than the VSS network.By foundation the present invention's esd protection device, current/voltage characteristic is the change of destructiveness suddenly, and the accurate rapid rising in the electric current position of specific voltage just is that the voltage up between the parasitic transistor electrode quite is higher than the prior art person just produces.Therefore, the destruction of the assembly in the semiconductor circuit can be by clamped the avoiding of appropriate voltage of suitable esd protection assembly.Have minimum protectiveness and isolate D
ProtectionSubstrate contacts SK1 and best arrangement of SK2 also can guarantee not wasting space by need supplementary protection diode, and the distance between well area does not need to be increased by non-essential.This facilitates the best esd protection with minimum space requirement.Yet with can provide substrate contacts SK1 and SK2 each other further away from.The present invention in fact also facilitates this, because free space can be used to the other structure of semiconductor circuit.
Esd protection device the 3rd embodiment system according to the present invention is shown in Fig. 4.This embodiment is specially adapted to irreversible breaking and only betides situation in the esd discharge direction incident of service voltage current potential between connecting.Among this embodiment, this situation system is depicted in esd event may betide first service voltage current potential connection VDDP person.In this esd protection device, non-reacted protective resistor RS is the esd protection assembly that is connected between substrate contacts SK1 and earth potential connection VSS.Moreover esd protection diode SD2 system is connected to substrate contacts SK1 and the second service voltage current potential connects between the VDD.The anode system of esd protection diode SD2 is connected to substrate contacts SK1, and its negative electrode is to be connected to the second service voltage current potential to connect VDD, so anode system quilt is along being partial to substrate contacts SK1 and VDD direction.Esd protection diode SD2 system is electrically connected to the service voltage current potential and connects VDD, and its no esd event and overvoltage may betide among this embodiment.In the present embodiment, for example can suppose that positive esd pulse is to be applied to the first service voltage current potential to connect VDDP.Therefore, earth potential connects VSS effectively to be interrupted, and second service voltage current potential connection VDD system is positioned at earth potential.Because esd pulse is via esd protection assembly ESD1, ESD2, D1, D2, additional ESD protection assembly RS, SD2 and bus resistance R1 and R2 are dissipated, and are positioned at and connect the current potential of VDD for height so connected VSS system by current potential effectively interruptedly.Esd protection diode SD2 can make parasitic element (parasitic transistor) not be subjected to drive and clamped substrate contacts SK1 to connecting VDD, the maximum potential that makes substrate contacts SK1 place has more than the diode threshold greater than service voltage current potential VDD.
When esd event betides the VDDP place, embodiment illustrated in fig. 4ly can parasitic transistor not driven by the esd protection resistor R S that carries out several ohm big or small rank and esd protection diode SD2.(do not have any esd event) during the general operation, substrate current system flows away via having the protective resistor RS that can ignore voltage drop.When esd event took place, drive current was lowered, and the voltage system at substrate or guard ring contact SK1 place is clamped by esd protection diode SD2.Esd protection diode SD2 ' shown in Figure 4 has nothing to do in quilt explanation situation and not involved.
Yet similar Fig. 4 explanation also can be used for the situation that esd event betides VDD.In this situation, resistor R S and simple sign esd protection diode SD2 ' are that parasitic transistor is not driven in the last esd event of the similar VDD of making.In this situation, esd protection diode SD2 is irrelevant and can be left in the basket.
Also can provide esd protection diode SD2 and esd protection diode SD2 ' be rendered in simultaneously embodiment illustrated in fig. 4 in, and combine with resistor R S parasitic transistor is not driven when esd event betides VDDP or VDD.
Fig. 5 shows esd protection device the 4th embodiment according to the present invention.Embodiment with respect to Fig. 4; act on the first esd protection assembly of esd protection circuit ESD_SS except resistor R S works as, the second esd protection transistor ST2 also is provided and replaces esd protection diode SD2 as the second esd protection assembly among the esd protection circuit ESD_SS.The current path system of passing through the second esd protection transistor ST2 is connected between substrate contacts SK1 and the service voltage current potential connection VDD.Moreover the grid of esd protection transistor ST2 connects system and is electrically connected to earth potential connection VSS and substrate contacts SK1 by the substrate that can be provided connects.
The 5th embodiment simply is depicted in Fig. 6.Among this embodiment, the first esd protection assembly among the esd protection circuit ESD_SS and the second esd protection assembly are esd protection transistor ST1 and ST2 form.The current path system of passing through the first esd protection transistor ST1 is connected to earth potential and connects between VSS and the substrate contacts SK1.Moreover the grid of the first esd protection transistor ST1 connects system and is electrically connected to service voltage current potential VDD and substrate contacts SK1 by the substrate connection that can be provided.Second esd protection transistor ST2 system is connected to the esd protection device in similar mode embodiment illustrated in fig. 5.
Fig. 7 shows the plane graph of the semiconductor circuit part details with some assemblies.This design drawing is simple show must protected each substrate contacts or guard ring contact be to be connected to earth potential respectively by the metallic region that is shown as square some contacts among the embodiment and is electrically connected to this contact via the esd protection diode.Protection diode system is shown in the p+/n well and connects the basifacial component.Connecting via metal is that specific isolation between the protection diode of the substrate contacts p+ of characterization top component and two n wells and bottom component is the fact that helps protective effect.
Fig. 8 shows another embodiment.The integrated circuit (IC) cording has not to be described but by a large amount of assemblies of doped region formation in the substrate.Sketch map shows well or substrate contacts SK, ceiling GS and guard ring GR.Substrate contacts SK, ceiling GS and guard ring GR system are electrically connected to earth potential bus VSSGR.This earth potential bus VSSGR is via esd protection diode SD1, SD2 in each example ", SD3 and SD4 are electrically connected to earth potential pad VSS pad, and wherein four systems are shown among the embodiment.Esd protection diode SD1 to SD4 is to being connected between earth potential bus VSSGR and the VSS pad with suitable folk prescription.As figure, the substrate contacts SK that all need protection, ceiling GS and guard ring GR all are electrically connected to earth potential bus VSSGR.So shown in the embodiment, the quantity of esd protection diode SD1 to SD4 is to decide on the VSS pad quantity that exists and contact with earth potential bus VSSGR in this example.No matter need protect the substrate contacts SK that is not subjected to the integrated circuit incident, why are ceiling GS and guard ring GR quantity, and esd protection diode SD1 to SD4 all must be involved.Therefore, also can contact SK quite in a large number by what quite a small amount of VSS pad and a small amount of esd protection diode provided that connection need protect, therefore GS and GR can make parasitic transistor do not driven to earth potential.Another advantage be the VSSGR bus potential mainly by the VSS pad very electronegative potential decide.For example, a lot of if the current potential on the VSS pad increases, the protection diode system that then connects the VSSGR bus of this pad becomes partially contrary.Yet, but other diode also fixed bus add the voltage drop of crossing over diode in other VSS pad than electronegative potential.
The present invention can simply reach the low-complexity mode by the substrate that connects semiconductor circuit, and the esd protection circuit between well or protection contact and earth potential connect is facilitated the assembly infringement that esd event is produced or destroyed effectively protection.Protective circuit can be esd protection diode or esd protection transistor form.In another alternative, the esd protection assembly can form by esd protection resistor and additional ESD protection diode.Yet esd protection circuit can also many modes be formed some assemblies of esd protection diode freely and/or esd protection transistor and/or resistor.All alternative all can save the space and the cost efficiency mode is effectively carried out.Particularly, but the present invention's protective substrate contact, and well contact and/or guard ring contact can be presented in its electronics supply line of semiconductor circuit nucleus and any parasitic structure and nucleus itself and be subjected to the infringement and the destruction that produce because of esd event.By this, the present invention also is specially adapted to the ESD load and betides during the general operation between two of different operating voltage is isolated between service voltages and can not directly be protected each other, and is just back-to-back and when connecting by collective or double link.Be to guarantee by the esd protection assembly that is integrated in the circuit mainly in the ESD load incident on these two service voltage buses to protecting of infringement.Yet earth potential VSS can cause new ESD infringement to the local positive potential of service voltage current potential VDD.Yet this infringement can be once more be placed in esd protection assembly in the semiconductor circuit by foundation the present invention, particularly avoids with substrate contacts and these esd protection assemblies of being grounded.
Claims (12)
- One kind be used in the semiconductor circuit, particularly integrated circuit static discharge (electrostatic discharge, ESD) protective device, this semiconductor circuit have one first doped region (SK; SK1; GS; GR) and at least two second doped regions (W1, W2), this first doped region (SK; SK1; GS; GR) be electrically connected to earth potential and connect (VSS), and this second doped region (W1, W2) being electrically connected to the service voltage current potential connects (VDD1; VDD2; VDD VDDP), is characterized in thatOne esd protection circuit (ESD_SS) is to be connected in this first doped region (SK; SK1; GS; GR) and this earth potential connect between (VSS).
- 2. esd protection device as claimed in claim 1 is characterized in thatThis esd protection circuit (ESD_SS) is designed, to such an extent as to this first doped region (SK; SK1; GS; GR), this first doped region (SK particularly; SK1; GS; GR) one on electrically contacts, and is in this service voltage current potential and connects (VDD1; VDD2; VDD, VDDP) and this earth potential connect the minimum value of these current potentials that (VSS) locate to occur.
- 3. esd protection device as claimed in claim 1 or 2 is characterized in thatThis esd protection circuit (ESD_SS) have at least one esd protection diode (SD1 to SD4) or an esd protection transistor (ST1, ST2).
- 4. esd protection device as claimed in claim 3 is characterized in that-can by with this first doped region (SK; SK1; GS; GK) anode of the esd protection diode (SD1 to SD4) of contact use is and this first doped region (SK; SK1; GS; GK) contact and negative electrode thereof are to be electrically connected to earth potential (VSS), or-can be used an esd protection transistor (ST1, ST2) grid connect and substrate to connect be to be electrically connected to this first doped region (SK; SK1; GS; GK).
- 5. esd protection device as claimed in claim 1 or 2 is characterized in thatThis esd protection circuit (ESD_SS) is to be electrically connected at least one service voltage current potential to connect (VDD, VDDP; VDD1, VDD2).
- 6. esd protection device as claimed in claim 5 is characterized in that-this esd protection circuit (ESD_SS) has and is connected to one first doped region (SK; SK1; GS; GK) and an earth potential connect one first esd protection assembly between (VSS), and-have and be connected to one first doped region (SK; SK1; GS; GK) and these two service voltages connect (VDD, one second esd protection assemblies between one VDDP).
- 7. esd protection device as claimed in claim 6 is characterized in thatThis second esd protection assembly is to be electrically connected to these two service voltage current potentials that will occur electronegative potential when critical esd event takes place to connect (VDD1, VDD2; VDD, one VDDP).
- 8. as claim 6 or 7 described esd protection devices, it is characterized in that-one resistor (RS), a particularly non-reacted resistor, an or esd protection transistor (ST1) are to be connected to be used as at this first doped region (SK; SK1; GS; GR) and this earth potential connect one first esd protection assembly between (VS S), and-one an esd protection diode (SD2, SD2 ') or an esd protection transistor (ST2) are to be connected to be used as this first doped region (SK; SK1; GS; GR) and the one first or second service voltage current potential connect (VDD1, VDD2; VDD, VDDP) the one second esd protection assembly between.
- 9. as the arbitrary described esd protection device of claim, it is characterized in that(W1 W2) is the well contact form to this second doped region, and one (W1) of these two second doped regions is electrically connected to one first service voltage current potential to connect (VD1; VDDP), another of these two second doped regions (W2) then is electrically connected to one second service voltage current potential connection (VD2; VDD).
- 10. as the arbitrary described esd protection device of claim, it is characterized in thatThis semiconductor circuit has some first doped region (SK; SK1; GS; GR), and in each example by an esd protection circuit (SD1 to SD4; ST1 ST2) is connected to these first doped regions (SK that earth potential connects (VSS); SK1; GS; GR) be when an esd event takes place, to be placed in abutting connection with being sent in transistor person in all one's life.
- 11. esd protection device as claimed in claim 10 is characterized in thatThis semiconductor circuit has protected and can keep out some first doped regions (SK of esd event; SK1; GS; GR), these first doped regions (SK; SK1; GS; GR) respectively be electrically connected to earth potential bus (VSSGR), and this earth potential bus (VSSGR) is via an esd protection assembly, particularly an esd protection diode or an esd protection transistor (SD1; SD2 ', SD3, SD4; ST1 ST2) is electrically connected at least one earth potential pad (VSS pad).
- 12., it is characterized in that as the arbitrary described esd protection device of claimThis first doped region (SK; SK1; GS; GR) can be a substrate (S) form, and at least one substrate contacts (SK1) or guard ring contact (GS; GR) be to be in contact with it.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE200410007655 DE102004007655B8 (en) | 2004-02-17 | 2004-02-17 | Semiconductor circuits with ESD protection device with an ESD protection circuit contacted with a substrate or guard ring contact |
| DE102004007655.3 | 2004-02-17 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1667827A true CN1667827A (en) | 2005-09-14 |
| CN100416830C CN100416830C (en) | 2008-09-03 |
Family
ID=34832716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100090386A Expired - Fee Related CN100416830C (en) | 2004-02-17 | 2005-02-16 | Protection device of semiconductor circuit with electrostatic discharge protecting circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN100416830C (en) |
| DE (1) | DE102004007655B8 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101038616B (en) * | 2006-03-17 | 2010-05-12 | 上海华虹集成电路有限责任公司 | Limiting amplitude protection circuit used in non-contact IC card and radio frequency identification label |
| CN103733336A (en) * | 2011-08-23 | 2014-04-16 | 美光科技公司 | Combination ESD protection circuits and methods |
| US9490631B2 (en) | 2011-08-30 | 2016-11-08 | Micron Technology, Inc. | Over-limit electrical condition protection circuits and methods |
| US9705318B2 (en) | 2009-01-08 | 2017-07-11 | Micron Techology, Inc. | Over-limit electrical condition protection circuits for integrated circuits |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2693032B1 (en) * | 1992-06-25 | 1994-09-30 | Sgs Thomson Microelectronics | Structure of stud protection diodes. |
| JP3210147B2 (en) * | 1993-08-09 | 2001-09-17 | 株式会社東芝 | Semiconductor device |
| US5754381A (en) * | 1997-02-04 | 1998-05-19 | Industrial Technology Research Institute | Output ESD protection with high-current-triggered lateral SCR |
| DE19936636A1 (en) * | 1999-08-04 | 2001-02-15 | Siemens Ag | Protective structure for an integrated semiconductor circuit to protect against electrostatic discharge |
| DE19944489A1 (en) * | 1999-09-16 | 2001-04-19 | Infineon Technologies Ag | ESD protection arrangement for signal inputs and outputs in semiconductor devices with substrate separation |
| DE19944487B4 (en) * | 1999-09-16 | 2005-04-28 | Infineon Technologies Ag | ESD protection arrangement for a semiconductor device |
| JP2001094050A (en) * | 1999-09-21 | 2001-04-06 | Mitsubishi Electric Corp | Semiconductor device |
| US6674129B1 (en) * | 1999-12-17 | 2004-01-06 | Koninklijke Phillips Electronics N.V. | ESD diode structure |
| DE10002241C2 (en) * | 2000-01-20 | 2002-05-08 | Atmel Germany Gmbh | Integrated bipolar transistor structure to limit overvoltage |
| US6385021B1 (en) * | 2000-04-10 | 2002-05-07 | Motorola, Inc. | Electrostatic discharge (ESD) protection circuit |
| JP2002270766A (en) * | 2001-03-06 | 2002-09-20 | Ricoh Co Ltd | Esd protecting circuit |
-
2004
- 2004-02-17 DE DE200410007655 patent/DE102004007655B8/en not_active Expired - Fee Related
-
2005
- 2005-02-16 CN CNB2005100090386A patent/CN100416830C/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101038616B (en) * | 2006-03-17 | 2010-05-12 | 上海华虹集成电路有限责任公司 | Limiting amplitude protection circuit used in non-contact IC card and radio frequency identification label |
| US9705318B2 (en) | 2009-01-08 | 2017-07-11 | Micron Techology, Inc. | Over-limit electrical condition protection circuits for integrated circuits |
| CN103733336A (en) * | 2011-08-23 | 2014-04-16 | 美光科技公司 | Combination ESD protection circuits and methods |
| CN103733336B (en) * | 2011-08-23 | 2017-02-15 | 美光科技公司 | Combination ESD protection circuits and methods |
| US9490631B2 (en) | 2011-08-30 | 2016-11-08 | Micron Technology, Inc. | Over-limit electrical condition protection circuits and methods |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102004007655B8 (en) | 2013-10-10 |
| DE102004007655B4 (en) | 2013-03-28 |
| CN100416830C (en) | 2008-09-03 |
| DE102004007655A1 (en) | 2005-09-08 |
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