CN1229270A - Semiconductor apparatus and method for manufacturing same - Google Patents
Semiconductor apparatus and method for manufacturing same Download PDFInfo
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- CN1229270A CN1229270A CN99102893A CN99102893A CN1229270A CN 1229270 A CN1229270 A CN 1229270A CN 99102893 A CN99102893 A CN 99102893A CN 99102893 A CN99102893 A CN 99102893A CN 1229270 A CN1229270 A CN 1229270A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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Abstract
A semiconductor device and a manufacturing method for the semiconductor device in which there is no defect such as deteriorated switching characteristics of a MOS transistor or long-term reliability of a gate oxide film, increased leakage current between a gate electrode and a silicon substrate or the deteriorated gate withstand voltage, otherwise produced due to excessive etching of a silicon oxide film in an outer trench rim neighboring to a device area to form a recess to expose the shoulder of a device area. In order to prevent this from occurring, a silicon oxide film spacer is provided on a sidewall section of an opening on a silicon substrate after an opening is formed in the silicon nitride film, in order to form a trench smaller in dismeter than the diameter of the opening in the silicon nitride film.
Description
The present invention relates to a kind ofly has one to be used for isolating semiconductor device and manufacture method thereof with the trench isolation structures of electric insulation with being formed on active zone on the semiconductor chip.
In a LSI (large scale integrated circuit) device separation, used a kind of trench isolation structures, provide a raceway groove between the device region that this structure is to form on the surface of semiconductor chip, and fill this raceway groove to realize isolation and insulation with dielectric film.In this manufacture method that is used for trench isolation structures, not making the performance of device or reliability deterioration is one of key factor.
Yet the channel isolation that forms with conventional art is such moulding: at the silicon oxide film of the trivial shoulder of raceway groove top next-door neighbour's device by over etching to form district's shoulder that a groove exposes device region.In this channel isolation, deterioration with the long-term reliability of transistorized switch performance of MOS (metal-oxide semiconductor (MOS)) that forms subsequently or gate oxidation films has appearred, pass the increase of the leakage current of gate electrode and silicon chip, or the relevant problem of the reduction of gate withstand voltage.
In order to address these problems, disclose a kind of usefulness step subsequently at present and filled the method for the groove of raceway groove shoulder, as announcing among the open JP-A-07-193083 of Japan Patent, and a kind of middle district and shoulder district at device region changes and plants the sub-concentration of stream to alleviate the method in the electric field strength in shoulder district, as disclosed among the Japan Patent JP-A-09-321134.
Up to the present the technology that is adopted can obtain explaining that these figure are classical production process generalized sections progressively of semiconductor device to Fig. 6 g to Fig. 5 d and Fig. 6 e with reference to Fig. 5 a.
At first, forms one first silicon oxide film 22 with thermal oxidation process on silicon chip 21, thickness is 5 to 20nm, and usefulness chemical vapor deposition (CVD) method is formed thereon with one deck silicon nitride film 23, and thickness is 100 to 300nm, shown in Fig. 5 a.Then, with the optical graving platemaking technology one photoresist Figure 24 is formed in the presumptive area as device region.Then, use dry etching technology, this silicon nitride film 23 and first silicon oxide film 22 are got rid of with anisotropic etching in this order.
Then, with this silicon nitride film 23 as etching mask, silicon chip 21 by anisotropic etching to form raceway groove 25, shown in Fig. 5 b.If use CF
4Carry out anisotropic dry etch with the mist of HBr, just obtain magnitude and be approximately 10 selection ratio the silicon of silicon nitride or silicon oxide film, etching finish make raceway groove 25 deeply will be for 150 to 500nm.
Then, use thermal oxidation process, on the inwall of this raceway groove 25, form one second silicon oxide film 26, shown in Fig. 5 c.The purpose of this thermal oxidation is to remove owing to dry ecthing is created in damage on the inner wall surface of raceway groove.Like this, for example, forming thickness on the surface is the oxide-film of 10nm to the 30nm scope.So silicon nitride film 23 becomes a kind of oxidation-resistant film, make that silicon chip 21 lip-deep device regions are not oxidized.
Then, use the CVD method, the 3rd silicon oxide film 27 is formed at whole surface, shown in Fig. 5 d.The thickness of the film that forms depends on the degree of depth of raceway groove 25, the thickness of first silicon oxide film 22 and the thickness of silicon nitride film 23, and for the thickness of the 3rd silicon oxide film 27 that will be determined, roughly the summation with above-mentioned thickness is suitable should to make the thickness of the 3rd silicon oxide film 27.The inside of raceway groove 25 is all filled by the 3rd silicon oxide film 27.
Then, the 3rd silicon oxide film 27 is used cmp method (CMP), shown in Fig. 6 e.Just finish on the surface that three silicon oxide film 27 of this polishing on silicon nitride film 23 all removed until exposing silicon nitride film 23.And polishing time is adjustable, makes silicon nitride film 23 unlikely quilts all get rid of.At this moment, the opening that is formed on the silicon nitride film 23 has a width x3 narrower than the A/F y3 of raceway groove 25, and this is because this second silicon oxide film 26 that forms on the inwall of raceway groove with thermal oxidation process has the width identical with the A/F of nitride film 23.
In the thermal oxidation of silicon face, silicon face indentation one is equivalent to half distance of this oxide-film thickness.If in this structure, the thickness of this second silicon oxide film 26 is 26 to 30nm, compares with the A/F x3 of silicon nitride film 23, on one side channel width has increased 15nm, the channel width both sides have increased 30nm.
Then, use phosphoric acid solution, be heated to about 150 ℃, silicon nitride film 23 is selectively removed, shown in Fig. 6 f.The inside of raceway groove 25 is filled by second silicon oxide film 26 and the 3rd silicon oxide film 27, makes and has only the 3rd silicon oxide film 27 to protrude in the surface of silicon chip 21.Only remaining the 3rd silicon oxide film 27 on the surface of silicon chip 21.Protrude in the 3rd silicon oxide film 27 on the silicon chip 21 on one side than the narrow z3 of the width of raceway groove 25.
Then, first silicon oxide film 22 is etched away with hydrofluoric acid solution, shown in Fig. 6 g.Then silicon chip 21 lip-deep device regions quilts are at the depth bounds internal heating oxidation from 10nm to 30nm, and so the heat oxide film that forms is then etched away with hydrofluoric acid solution.In wet etching operation process, the 3rd silicon oxide film 27 that protrudes in silicon chip 21 surfaces is etched equally, makes that the height of the 3rd silicon oxide film 27 is low to the level near silicon chip 21 surfaces.
In further investigation process of the present invention, observe the following phenomenon that displays.
When the ledge by this wet etching operation etching the 3rd silicon oxide film 27, the sidewall of raceway groove and the separated z3 of being equal to distance a bit between do not have ledge.Like this, if wet etching is done under this situation, the top that is filled in second silicon oxide film 26 of raceway groove inboard is also followed etched immediately after the 3rd silicon oxide film 27 that protrudes in silicon chip 21 surfaces is etched to a preset height, up to final formed one the depression 28, shown in Fig. 6 g.The result is that the device region on raceway groove 25 both sides forms shoulder district 29.
Electric field is tending towards concentrated in the shoulder district 29 of the semiconductor device that forms with conventional method, 28 is formed in the raceway groove 25 if cave in like this, and the switch performance of the MOS transistor that will occur forming subsequently worsens or the problem of the long-term reliability deterioration of gate oxidation films.In addition, the leakage current that passes gate electrode and silicon chip is tending towards increasing, or gate withstand voltage is tending towards variation.
In view of above mentioned problem, one of purpose of the present invention provides a kind of semiconductor device and manufacture method thereof, wherein, it can avoid forming depression on the surface of the silicon oxide film that buries channel surface, or the variation of the switch performance of the MOS transistor that forms subsequently.Another purpose is to avoid the deterioration of gate oxidation films long-term reliability and pass grid and the increase of the leakage current of silicon chip, or the variation of gate withstand voltage.
Other purpose of the present invention will display in whole description.
For achieving the above object, the invention provides a kind of device, wherein by on semiconductor chip, forming one first dielectric film (as silicon nitride film 3 among Fig. 1 c), on the inwall of this first dielectric film, form one second dielectric film (as the silicon oxide film dividing plate 5 among Fig. 1 c) then, then the opening that provides with first and second dielectric films forms a raceway groove as mask, or only use the opening of first dielectric film (as the silicon nitride film among Fig. 3 c 13) to form a raceway groove as mask, form an epitaxial loayer (as the silicon epitaxy layer among Fig. 3 c 16) then on the inwall of raceway groove, the diameter of the raceway groove opening interior than first dielectric film is little.Specifically, the present invention has following characteristics:
First aspect, the invention provides a kind of method that is manufactured on the semiconductor device that raceway groove is arranged in the substrate, be included on the silicon chip and form first dielectric film that default opening arranged, settle one second dielectric film on the inwall of the first dielectric film split shed, and the opening that provides with first dielectric film and second dielectric film form a raceway groove as mask.
Second aspect, the invention provides a kind of method that is manufactured on the semiconductor device that raceway groove is arranged in the substrate, be included on the silicon chip and form first dielectric film that default opening arranged, form a raceway groove with the opening on first dielectric film as mask,, reach and on the inwall of epitaxial loayer, settle one second dielectric film to form epitaxial loayer by deposition on the inwall of raceway groove.
The present invention also provides a kind of method of making semiconductor device, comprises step: a) form one first silicon oxide film 2 and silicon nitride film 3 on silicon chip continuously; B) in above-mentioned first silicon oxide film 2 and silicon nitride film 3, form an opening by photolithography steps; C) on the sidewall of above-mentioned silicon nitride film 3 split sheds, settle silicon monoxide film dividing plate 5; D) form a raceway groove 6 with above-mentioned silicon nitride film 3 and silicon oxide film dividing plate 5 as mask; E) on the inwall of above-mentioned raceway groove 6, form one the 3rd silicon oxide film 7; F) imbed one the 4th silicon oxide film 8 in the inside of above-mentioned raceway groove 6; G) remove above-mentioned silicon nitride film 3; And h) removes the 3rd silicon oxide film 7 and the 4th silica 8 that protrude in above-mentioned substrate.
Fig. 1 a is the profile of consecutive steps of method that shows the formation raceway groove of first embodiment according to the invention to 1d.
Fig. 2 e is to show that the sequential chart 1a of consecutive steps of method of formation raceway groove of first embodiment according to the invention is to the profile of Fig. 1 d to 2h.
Fig. 3 a is the profile of demonstration according to the consecutive steps of the method for the formation raceway groove of second embodiment of the present invention to 3d.
Fig. 4 e to 4h be show according to the consecutive steps of the method for the formation raceway groove of second embodiment of the present invention continuously in the profile of Fig. 3 a to Fig. 3 d.
Fig. 5 a is the profile that shows the method for traditional formation raceway groove to Fig. 5 d.
Fig. 6 e to 6g be show traditional formation raceway groove method continuously in the profile of Fig. 5 a to Fig. 5 d.
Example below with reference to most preferred embodiment and enforcement most preferred embodiment is explained the present invention.
Have default opening a usefulness, be formed at silicon nitride film on the silicon chip (Fig. 1 c 3) as in the most preferred embodiment of etching mask with the method, semi-conductor device manufacturing method of the present invention that forms raceway groove, silicon dioxide film dividing plate (Fig. 1 c 5) is positioned on the inwall of this silicon nitride film opening.
And, having formed a raceway groove (Fig. 3 c 15) with the silicon nitride film that has default opening, be formed on the silicon chip as etching mask (Fig. 3 c 13), a silicon epitaxy layer (Fig. 3 c 16) is formed on the inner surface of raceway groove afterwards.
Need the above-described embodiment of the present invention referring to figs. 1 through Fig. 4 for further explaining, it illustrates examples more of the present invention by production process.Example 1
Fig. 1 a is the profile that shows the consecutive steps of implementing first example of the present invention to Fig. 2 h to Fig. 1 d and Fig. 2 e.Show that for convenient Fig. 1 and Fig. 2 are separated simultaneously.
At first, one first silicon oxide film 2 is formed on the silicon chip 1 by thermal oxidation process, and thickness reaches 5 to 20nm (nanometer), and a silicon nitride film 3 is formed thereon by chemical vapor deposition (CVD) method, and thickness reaches 100 to 300nm, as shown in Figure 1a.
Then, use lithography technique, a photoresist Fig. 4 is formed at one will be as the presumptive area of device region.Then, use dry etching technology, this silicon nitride film 3 and this first silicon oxide film 2 are pressed this anisotropically etching of order.
This photoresist Fig. 4 is changed into ash by oxygen plasma then and is got rid of, shown in Fig. 1 b.This second silicon oxide film is formed at whole surface then.This second silicon oxide film is carried out anisotropic etching makes silicon monoxide film dividing plate 5 be placed on the sidewall of opening of silicon nitride film 3.
Thickness that it should be noted that this second silicon oxide film will be set to the opening thickness that needn't be enough to all bury silicon nitride film 3.Promptly the thickness of this silicon oxide film is than the width of the narrowest part of these silicon nitride film 3 opening scopes half be also thin.
For example, if the width of narrow opening is 0.2 μ m (micron), i.e. 200nm, the thickness of this second silicon oxide film is thinner than half the 100nm corresponding to A/F, and promptly the thickness of this second silicon oxide film is preferably 30 to 80nm.
This silicon chip 1 uses this silicon nitride film 3 and this silicon oxide film dividing plate 5 as the anisotropically etching of etching mask quilt then, shown in Fig. 1 c, for example produces a raceway groove 6., if use a kind of CF
4Carry out anisotropic dry etch with the mist of HBr, just obtain magnitude and be approximately 10 silicon to silicon nitride film or to the selection ratio of silicon oxide film.Etching this moment will be done, and make that raceway groove 6 will be dark to 500nm for 150nm.
Then, use thermal oxidation process, one the 3rd silicon oxide film 7 is formed on the surface of these raceway groove 6 inwalls, shown in Fig. 1 d.The purpose of this thermal oxidation is to remove by carry out the damage that dry ecthing brought on the inner wall surface of raceway groove.So far, a thin oxide-film has satisfied requirement.For example, the thickness of oxide-film is met in 10 to 30nm magnitudes.Even it is thicker, the thickness of this oxide-film is also thin such as the twice of the second silicon oxide film thickness of last formation.Because silicon nitride film 3 is used as anti-oxidant surface, the device portions on the silicon chip 1 does not have oxidized.
Then, use the CVD method, one the 4th silicon oxide film 8 is formed on whole surface, shown in Fig. 2 e.The thickness of the film that forms depends on the degree of depth of raceway groove 6, the thickness of first silicon oxide film 2 and the thickness of silicon nitride film 3.The thickness of the 4th silicon oxide film 8 is set as that roughly the summation with above-mentioned thickness is suitable.All filled the inside of raceway groove 6 with the 4th silicon oxide film 8.
The 4th silicon oxide film 8 is polished with the CMP method then, shown in Fig. 2 f.Just finish on the surface that four silicon oxide film 8 of this polishing on silicon nitride film 3 all removed until exposing silicon nitride film 3.Polishing time is adjustable, makes nitride film 3 unlikely quilts all get rid of.
At this moment, the A/F x1 of silicon nitride film 3 is wideer than the width y1 of raceway groove 6, and this is because when forming raceway groove 6 by dry etching technology, silicon oxide film dividing plate 5 is formed on the inside of silicon nitride film 3 openings earlier.
Then, use phosphoric acid solution, be heated to about 150 ℃, silicon nitride film 3 selected removals are shown in Fig. 2 g.The inside of raceway groove 6 is filled by the 3rd silicon oxide film 7 and the 4th silicon oxide film 8, and silicon oxide film dividing plate 5 and the 4th silicon oxide film 8 protrude in the surface of silicon chip 1 like this.At remaining first silicon oxide film 2 in the surface of device region.First silicon oxide film 2 that protrudes in silicon chip 1 is with the device region that extends to of the distance z 1 of the width that exceeds raceway groove 6.
First silicon oxide film 2 is etched away with hydrofluoric acid solution then, shown in Fig. 2 h.The lip-deep device region of silicon chip 1 by at the depth bounds internal heating oxidation from 10nm to 30nm to form a heat oxide film that is etched away with hydrofluoric acid solution subsequently.In wet etch process, the silicon oxide film that protrudes in silicon chip 1 surface is etched equally, makes that its height is roughly suitable with the surface of silicon chip 1 now.
In example 1, protrude in the 4th silicon oxide film 8 of silicon chip 1 and this silicon oxide film dividing plate 5 and extend to device region with the distance z 1 of the width that exceeds raceway groove 6, therefore when outstanding part is etched by the wet etching operation, there is not the part etched risk early on the raceway groove inwall of being positioned at of having only the 3rd silicon oxide film 7, above raceway groove, do not form any groove, as in conventional art.Embodiment 2
Explain embodiments of the invention 2 now.Fig. 3 a is the profile that shows the consecutive steps of implementing second embodiment of the present invention to 4h to 3d and Fig. 4 e.Show for convenient simultaneously, Fig. 3 and Fig. 4 be divided into respectively Fig. 3 a to 3d and 4e to 4h.
In example 1, diameter is to form as mask by form silicon monoxide film dividing plate on the inwall of silicon nitride film opening less than the raceway groove of silicon nitride film split shed.In example 2, above-mentioned minor diameter raceway groove is that the epitaxial junction with the silicon of raceway groove inside is configured to.
With reference to Fig. 3 a, one first silicon oxide film 12 and a silicon nitride film 13 example 1 as described above are formed on the silicon chip 11 like that, then, by using well-known lithography technique and dry etching technology, opening is formed in this first silicon oxide film 12 and the silicon nitride film 13.
Changed into by oxygen plasma after ash gets rid of at photoresist figure 14, as etching mask, silicon chip 11 anisotropically is etched with forms a raceway groove 15 with silicon nitride film 13.If use the mist of a kind of CF4 and HBr to carry out anisotropic dry etch, obtain magnitude and be approximately 10 silicon selection ratio silicon nitride film or silicon oxide film.Etching this moment be done make raceway groove 15 deeply will for 150nm to 500nm.
Then, use a ultra high vacuum CVD equipment, by selective epitaxy growth, silicon growth on the inwall of raceway groove 15 to form a silicon epitaxy layer 16, shown in Fig. 3 c.Because adopt to select growing method in this operation, this silicon epitaxy layer only is grown in the part that silicon exposes, promptly in the inside of this raceway groove.The thickness of the silicon fiml that grows by epitaxial growth depends on the width of the opening of raceway groove 15.If the narrowest part of opening is 0.2 μ m, i.e. 200nm, the thickness of the silicon fiml that grows by epitaxial growth are preferably thin than half the 100nm corresponding to A/F, for example 30 to 80nm.
Then, use the CMP method in the example 1 as described above, one the 3rd silicon oxide film 18 is formed on whole surface, with the inside of the 3rd silicon oxide film 18 whole filling raceway grooves 15.
The 3rd silicon oxide film 18 is used the CMP method polishing in the example 1 as described above then, comes out up to the surface of silicon nitride film 13, shown in Fig. 4 f.
At this moment, the A/F x2 of silicon nitride film 13 is wideer than the width y2 of raceway groove 15, because the growth of this selection silicon epitaxy layer 16 causes the narrowed width of raceway groove 15.
Then, use phosphoric acid solution, be heated to about 150 ℃, as example 1, silicon nitride film 13 selected removals are shown in Fig. 4 g.The inside of raceway groove 15 is filled by second dielectric film 17 and the 3rd silicon oxide film 18, makes second insulating barrier 17 and the 3rd silicon oxide film 18 protrude in the surface of silicon chip 11.At remaining first silicon oxide film 12 in the surface of device region.This silicon oxide film that protrudes in silicon chip 11 extends to device region with the distance z 2 that exceeds raceway groove 15 width.
At last, first silicon oxide film 12 is used hydrofluoric acid solution and etches away, as example 1, shown in Fig. 4 h.The lip-deep device regions of silicon chip 11 by at 10nm to the depth bounds internal heating oxidation of 30nm to form a heat oxide film that is etched away with hydrofluoric acid solution subsequently.In wet etch process, the silicon oxide film that protrudes in the silicon chip surface is etched equally, makes that its height and the surface of silicon chip 11 are roughly suitable.
In example 2, as example 1, the 3rd silicon oxide film 18 and this second dielectric film 17 of protruding in silicon chip 11 extend out with the distance that exceeds raceway groove 15 width z2, shown in Fig. 4 g.Like this, when outstanding part is etched by the wet etching operation, do not exist this second dielectric film 17 that only is positioned on the raceway groove inwall early etched and above raceway groove, form the risk of groove, as taking place in the conventional art.
As mentioned above, the present invention has drawn following various remarkable result.
First remarkable result of the present invention is, owing to be formed on silicon sequentially by the photoetch operation Form an opening in on-chip heat oxide film and the nitride film, and the oxide-film dividing plate is formed on nitride film On the sidewall of split shed, subsequent is the subsequent step that forms raceway groove and fill oxide-film, the cuing open of device The face shape is shown in Fig. 2 f, and wherein the width of the aperture efficiency raceway groove in the silicon nitride film is wide.
The wide opening of width of the ratio raceway groove in the silicon nitride film is equivalent to protrude from silica-based from the inside of raceway groove The wide silicon oxide film of ratio raceway groove on the sheet, namely the silicon oxide film of raceway groove upper end covers device with overlap mode The part district. Like this, when the silicon oxide film that protrudes from silicon chip is removed with the wet etching operation subsequently, only The peripheral edge portion of the silicon oxide film of filling raceway groove is arranged by over etching, with the formation of avoiding caving in, avoid Outside the shoulder district of device region is exposed on.
By this channel isolation, can prevent the switch performance variation of the MOS transistor that forms subsequently. In addition, it can avoid the deterioration of the long-term reliability of gate oxidation films, and it can be avoided] gate electrode And the leakage current between the silicon chip, avoid simultaneously the decline of gate withstand voltage.
It is very clear to it should be noted that other purpose of the present invention becomes in whole description, and can Make amendment and do not break away from and reaching the relevant described aim of the present invention in place and scope here.
It should be noted that equally any description and/or claims in element and material and / or the order combination all drop within the above-mentioned modification.
Claims (8)
1. method that is manufactured on the semiconductor device that raceway groove is arranged in the substrate, comprising:
Formation one has first dielectric film of default opening on described substrate;
On the inwall of the opening of described first dielectric film, settle one second dielectric film; And
The opening that provides with described first dielectric film and second dielectric film forms a raceway groove as mask.
2. method that is manufactured on the semiconductor device that raceway groove is arranged in the substrate, comprising:
Formation one has first dielectric film of default opening on described substrate;
Form a raceway groove with the opening in described first dielectric film as mask;
Form an epitaxial loayer by the deposition on the inwall of described raceway groove; And
On the inwall of described epitaxial loayer, settle one second dielectric film.
3. the method for manufacturing semiconductor device as claimed in claim 1, wherein said first dielectric film
It is silicon nitride film;
Described second dielectric film is a silicon oxide film.
4, the method for manufacturing semiconductor device as claimed in claim 2, wherein,
Described first dielectric film is a kind of silicon nitride film;
Described second dielectric film is a kind of silicon oxide film; And wherein
Described epitaxial loayer is made of silicon.
5, a kind of method of making semiconductor device is comprising step: a) form one first silicon oxide film (2) and silicon nitride film (3) sequentially on silicon chip; B) in described first silicon oxide film (2) and described silicon nitride film (3), form an opening by photolithography steps; C) on the sidewall of described silicon nitride film (3) split shed, settle silicon monoxide film dividing plate (5); D) form a raceway groove (6) with described silicon nitride film (3) and silicon oxide film dividing plate (5) as mask; E) on the inwall of described raceway groove (6), form one the 3rd silicon oxide film (7); F) imbed one the 4th silicon oxide film (8) in the inside of described raceway groove (6); G) remove described silicon nitride film (3); And h) removes the 3rd silicon oxide film (7) and the 4th silicon oxide film (8) that all protrude in described substrate.
6. method of making semiconductor device is comprising step: a) form one first silicon oxide film (12) and silicon nitride film (13) sequentially on silicon chip; B) in described first silicon oxide film (12) and described silicon nitride film (13), form an opening by photolithography steps; C) form a raceway groove (15) with described first silicon oxide film (12) and silicon nitride film (13) as mask; D) form a silicon epitaxy layer (16) by deposition on the inwall of described raceway groove; E) on the inwall of described silicon epitaxy layer (16), settle one second dielectric film (17); F) imbed one the 3rd silicon oxide film (18) in the inside of described raceway groove (15); G) remove described silicon nitride film (13); And h) removes second silicon oxide film (17) and the 3rd silica (18) that all protrude in described substrate.
7. the semiconductor device that raceway groove is arranged on the substrate, wherein
The on-chip silicon nitride film that one usefulness is formed at default opening is provided and has been placed in described silicon nitride
Inwall on the raceway groove that forms as mask of silicon oxide film dividing plate;
The silicon monoxide film is filled in the inside of described raceway groove; And wherein
In the surface of the silicon oxide film of filling described raceway groove, there is not groove.
8, a kind of semiconductor device that comprises the raceway groove that forms as mask with the on-chip silicon nitride film that is formed at default opening, wherein
One silicon epitaxy layer is set on the inwall of described raceway groove;
The silicon monoxide film is filled in the inside of described raceway groove, and wherein
In the surface of the silicon oxide film of filling described raceway groove, there is not groove.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP082543/98 | 1998-03-13 | ||
| JP10082543A JPH11260906A (en) | 1998-03-13 | 1998-03-13 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1229270A true CN1229270A (en) | 1999-09-22 |
Family
ID=13777430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99102893A Pending CN1229270A (en) | 1998-03-13 | 1999-03-12 | Semiconductor apparatus and method for manufacturing same |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPH11260906A (en) |
| KR (1) | KR19990077847A (en) |
| CN (1) | CN1229270A (en) |
| TW (1) | TW413946B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853803A (en) * | 2010-01-28 | 2010-10-06 | 上海宏力半导体制造有限公司 | Method for reducing shallow channel isolating divot |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010038753A (en) * | 1999-10-27 | 2001-05-15 | 박종섭 | Manufacturing method for isolation in semiconductor device |
| JP2003017595A (en) | 2001-06-29 | 2003-01-17 | Toshiba Corp | Semiconductor device |
| JP4672197B2 (en) * | 2001-07-04 | 2011-04-20 | 株式会社東芝 | Manufacturing method of semiconductor memory device |
| KR100400254B1 (en) * | 2001-12-18 | 2003-10-01 | 주식회사 하이닉스반도체 | Method for forming the semiconductor device |
| JP2004039734A (en) | 2002-07-01 | 2004-02-05 | Fujitsu Ltd | Method of forming element separating film |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63246869A (en) * | 1987-04-02 | 1988-10-13 | Seiko Instr & Electronics Ltd | Semiconductor light receiving device |
| JPH01315160A (en) * | 1988-06-15 | 1989-12-20 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0637178A (en) * | 1992-07-17 | 1994-02-10 | Toshiba Corp | Manufacture of semiconductor device |
| JPH0729971A (en) * | 1993-06-25 | 1995-01-31 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1998
- 1998-03-13 JP JP10082543A patent/JPH11260906A/en active Pending
-
1999
- 1999-03-12 KR KR1019990008420A patent/KR19990077847A/en not_active Application Discontinuation
- 1999-03-12 TW TW088103918A patent/TW413946B/en not_active IP Right Cessation
- 1999-03-12 CN CN99102893A patent/CN1229270A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101853803A (en) * | 2010-01-28 | 2010-10-06 | 上海宏力半导体制造有限公司 | Method for reducing shallow channel isolating divot |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11260906A (en) | 1999-09-24 |
| TW413946B (en) | 2000-12-01 |
| KR19990077847A (en) | 1999-10-25 |
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