CN1225713C - Design method for specific chip of intelligent electric appliance - Google Patents
Design method for specific chip of intelligent electric appliance Download PDFInfo
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- CN1225713C CN1225713C CN 03114428 CN03114428A CN1225713C CN 1225713 C CN1225713 C CN 1225713C CN 03114428 CN03114428 CN 03114428 CN 03114428 A CN03114428 A CN 03114428A CN 1225713 C CN1225713 C CN 1225713C
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Abstract
The present invention discloses a design method for a dedicated chip of an intellectualized electric appliance. A programmable ASIC technique is used for designing a chip by the method on the basis of a platform. The method comprises: FPGA is used for designing a system on an intellectualized electric appliance chip; IP modules of the intellectualized electric appliance are divided; IP cores are designed in a parametrization mode, the designed IP cores all support parameterization programming, and different functions can be realized by configuring different parameters under the condition that core contents of the modules are not modified; the IP cores are designed in a generalization mode; the dedicated chip is used as a discrete element and connected with other circuits in the form of a small printed circuit board. The method of the present invention is used for completing the dedicated chip of the intellectualized electric appliance; the chip uses two 100-thousand gate FPGA chips (EP1k100PQ208-3); the accuracy of the functions of the entire chip is verified through emulation and actual measurement; finally, various performance indexes of a line protective device designed on the basis of the chip pass correlative tests of the National Relay Quality Testing, Monitoring and Detecting Center.
Description
One, technical field
The invention belongs to computer application field, relate to the special chip that is used to protect electrical network and equipment thereof, a kind of especially Automation of Electric Systems intelligent electric appliance special chip with the programmable special-purpose chip technical design.
Two, background technology
The electric system Microcomputer Protection is used to protect electrical network and equipment thereof, and is most important to the operation of power system stability economy.Microcomputer protecting device integrates computer technology, network technology, microelectric technique, sensor technology; compare with conventional art; not only functions such as the metering that can make, protection, observing and controlling are more accurate, more reliable, and can realize functions such as emergency review, failure wave-recording, equipment work situation on-line monitoring.As far back as the initial stage seventies just the someone propose to utilize computing machine as the imagination of protecting electrical power system element and obtained realization; 30 years of development and practice have been passed through; from replacing electromagnetic type relay simply, have the progressively perfect intelligent electrical apparatus equipment of new theory new technology such as network communication function, neural network, fuzzy control, small echo based on the electric system protection device of microprocessor up till now.
China introduces microcomputer protective relay at the mid-80, and the end of the eighties, the microcomputer protective relay device of domestic-developed began to apply.Be Microcomputer Protection period with fastest developing speed the nineties, and not only product is many, and defencive function is also perfect gradually, and the device manufacture level also improves constantly.Up to the present, domestic have large quantities of professional and technical personnel that are engaged in Microcomputer Protection research, design, exploitation, test, make, and tens tame professional production factories are arranged, and also has a collection of scientific research institutions, universities and colleges to be engaged in correlative study.The Microcomputer Protection product has route protection, bus protection, generator protection, tranformer protection, fault oscillograph etc., and kind is many, model is complete.Along with the research of microcomputer protecting device, a lot of theoretical results have also been obtained at aspects such as Microcomputer Protection software algorithms.Compare with external same device, we are not a halfpenny the worse aspect protection philosophy.We can say, since the nineties China's Protection Technology entered epoch of Microcomputer Protection.
Up to the present, the internal microcomputer protective device all is to be core with the single-chip microcomputer basically, and the performance quality of microprocessor directly influences the function of system.The hardware of microcomputer protecting device is always towards high speed and the development of high reliability both direction.The speed that on the one hand is processor is more and more faster, and system hardware structure is from single 8 bit processors to 16 and even 32 bit processors, until the current multimicroprocessor and the mixed structure of multi-digital signal processor; Then taking many measures aspect the raising reliability on the other hand: do not go out socket from bus and do not go out chip to bus, and the application of hardware check and watchdog technique etc., make the reliability of hardware obtain raising to a certain degree really.
Should see that microcomputer protecting device itself has some inherent defectives.For example, microprocessor and digital signal processor all adopt queuing type serial command executive mode, the raising of its operating rate and efficient also all is subject to this working method, aspect processing speed, the speed of digital signal processor and microprocessor still can not satisfy the new algorithm and the theoretical requirement of continuous appearance.In addition, microprocessor initially all must experience a reseting procedure in work, must satisfy certain level condition and time conditions, and when operation level had certain interference sudden change, it resets will become the key factor of the unreliable work of system.It is another shortcoming of microprocessor that program pointer is subject to disturb.Fact proved, no matter how outstanding microprocessor, no matter has how good interference protection measure, comprise the inside and outside hardware watchdog that any way is set, be subjected to strong jamming particularly under the strong electromagnetic situation, can't guaranteeing that all it still can operate as normal and do not enter irremediable " deadlock " state.Though watchdog technique can make most systems reset again, but still can't accomplish the recovery of instruction-level, thereby cause that the tripping of device or the possibility of malfunction exist.Especially when the interference of program pointer and the unreliable factor that resets were staggered, it is particularly complicated that situation will become.
Electric design automation is a new technology that develops rapidly in recent years.Application and Development based on the CPLD/FPGA of this technology can overcome above-mentioned essential defect.At first, the field programmable gate array product has adopted advanced in the system configuration programming mode more and more.Under the operate as normal level, can carry out in-system programming whole or in part to the programmable chip of working at any time.Next is that the clock delay of field programmable gate array can reach nanosecond at a high speed, in conjunction with its concurrent working mode, aspect ultra-high speed applications field and the observing and controlling in real time boundless application prospect is being arranged.Be example for example, under the 800MHz clock, need 7.7 μ s with the fastest industrial digital signal processor at present with 16 fast fourier transform of 1024, and with the Virtex-II of Xilinx company family chip at 140MHz clock less than of following operation use time 1 μ s; High reliability also is one of its advantage, microprocessor is peculiar to reset unreliable and program pointer easily the inherent shortcoming such as interference except not existing, the high reliability of field programmable gate array also shows almost and can will be stated under the total system in the same chip, thereby dwindled the volume of printed circuit board (PCB) greatly, be easy to management and shielding.In addition, developing instrument and design language standardization, construction cycle weak point are its another advantages.Utilize them can realize the design of almost any type of digital circuit or digital display circuit.How this technology being applied to the Microcomputer Protection field, is main contents of the present invention.
At present, along with the development of microelectric technique, SOC (system on a chip) all has advantage clearly at speed, reliability and aspects such as confidentiality and price, be the focus of studying in recent years.Advantages such as field programmable gate array is easy to develop and need not once to invest with it, make increasing chip design personnel turn to programmable way to realize, field programmable gate array is also development with surprising rapidity in recent years, its integrated level develops into current several ten million from several years ago several ten thousand, but integrated microprocessor, storer and communication interface etc. in the sheet, and the price end more and more.The feasible degree that really is tending towards practicability based on programmable SOC (system on a chip).This technology has obtained successful application in mobile phone, palm PC, TV set-top box, the hand-held consumer goods and fields such as the Internet, car engine controller and the network switch.
Aspect relay protection, the report that utilizes field programmable gate array to realize the overcurrent relay algorithm is abroad also arranged, but the function of the SOC (system on a chip) of not realizing ideal.
Three, summary of the invention
Purpose of the present invention is utilized special chip of FPGA Technology exploitation able to programme exactly, replaces single-chip microcomputer in the past to be used for the electric system Microcomputer Protection.The intelligent electrical apparatus special chip of the present invention design has been realized the function that software is in the past realized with hardware.Multiple functions such as protection, control, metering, supervision, constructing communication network that chip is integrated are in one.Adopted idea of modular, functional configuration, expansion are conveniently.
Realize that the technical scheme that intelligent electric appliance special chip of the present invention is taked is, utilizes FPGA Technology according to unitized method chip to be designed; May further comprise the steps:
1) utilizes field programmable gate array design intelligent electrical apparatus SOC (system on a chip)
Utilize the intelligent electrical apparatus special chip of field programmable gate array design, it has data acquisition function on the one hand, can monitor the parameters such as electric current, voltage of protected object simultaneously; It has the relay protection function on the other hand, in case acquisition parameter occurs should protecting action according to set protection algorithm unusually; Simultaneously, it also will have communication function, and it supports corresponding procotol to constitute electric substation automation system and distribution automation system.And utilize its programmable characteristics, under the structure of same chip, can develop a series of special chips that satisfy distinct device protection needs;
2) division of intelligent electrical apparatus chip internal functional module
Correctly take out the universal model of intelligent electrical apparatus, rationally divide interface definition between each functions of modules, each module of standard, design a series of general utility functions modules with the common hardware descriptive language; The various functional modules that will constitute chip in design process are divided into general and special-purpose two parts, and general module is used to construct the structure of chip, and private part is used to realize the application requirements of distinct device protection:
The general module part mainly comprises: data acquisition module, data processing module, communication module, internal task scheduler module, external memory interface module;
The special module part mainly refers to a series of protection algoritic modules, switching value input/output module;
3) parametrization of each functional module design
The equal support parameter programming of functional module of design; Under the situation of modified module core content not, only, different parameters just can realize different functions by being set;
4) General design of functional module
Adopt the general hardware descriptive language to design each functional module, so that be supported in exploitation under the different integrated circuit (IC) design platforms, each functional module is with independent component or claim the mode of virtual component to be connected with system bus and other functional module;
5) this special chip is connected with other circuit as an independent component with the form of a little printed circuit board (PCB).
Described data acquisition module, data processing module, communication module, internal task scheduler module, external memory interface, they are respectively:
Data acquisition module:
This module is finished special chip with the interface of outside mould/number conversion and relevant control, realizes the collection and the storage of 16 channel datas;
Data processing module:
Fast Flourier filtering algorithm, effective value that this module is finished 16 channel datas successively calculate; Finish power calculation; And fast Flourier result and other result of calculations are stored;
Communication module:
Be used for chip and external unit data communication interface, utilize the different communication protocol of programmable function design with serial mode;
External memory interface:
This module provides the control of external data memory being read and write in the mode of parallel or serial;
Data and task scheduling modules:
This module is the core of total system work, mainly comprises the scheduling of the scheduling of measured data, the scheduling of setting definite value, communication task, the scheduling of protection algorithm task etc., and it is equivalent to a simple real-time multi-task operating system; By parameter is set, control provides corresponding data to each protection algorithm; In case increase or delete a protection algoritic module, except will being provided with, also task scheduling modules to be set to the corresponding protection module, determine the priority of each task and guarantee corresponding task and this task need data message harmonious;
The annexation of above-mentioned intermodule is: the data output that data acquisition module obtains is as the data input of data processing module; The results of data processing is the data input of protection algorithm; Communication module then can be obtained data or provide data to other correlation module according to the requirement of communication protocol from disparate modules; All data are transmitted by internal bus; Total system is by the unified management of data dispatch module.
Described accommodation function module refers to a series of protection algoritic modules, comprising: fast tripping protection, quick-break in limited time, overcurrent protection, low-frequency load reduction, reclosing, zero-sequence current protection, zero-sequence voltage protection, differential protection, inverse time-lag protection etc.
The parametrization design of described each functional module comprises: data acquisition module can be selected different sampling rates by parameter setting; Data processing module also can select to import the length of counting of data and each point; Each protection module allow to select input data from which passage, get the first-harmonic data or get the higher hamonic wave data, which definite value is given definite value be, protect enable signal from where waiting; Data and task scheduling modules then will be specified the corresponding data channel of each protection algorithm by parameter is set; Communication module is provided with different baud rates and stipulations etc.
Described unitized function module design comprises: adopt the general hardware descriptive language to design each functional module, so that be supported in exploitation under the different designs platform; Each functional module links to each other with system bus and other functional module in the mode of independent virtual component.
Described special chip appears in the hardware of system with the form of an independent component, in case the definition of clear and definite its external interface also just is equivalent to determine the pin of element, the function of special chip realizes the programming decision by field programmable gate array chip.
Described field programmable gate array chip can be the product of different company, and the programming technology of chip both can be based on random access memory also can be based on flash memory or anti-fuse structures.
The quantity of described programmable gate array chip can be that a slice also can be two or multi-disc.
Described special chip is reserved with the part pin as outside measuring point, arbitrary signal in the chip can be assigned to these measuring points in exploitation and debug phase, by the correctness that oscillograph, logic analyser etc. are tested and checking designs, in case design is finished, and can reassign these functions of pins by program.
Four, description of drawings
Fig. 1 is the typical hardware configuration block diagram of the Microcomputer Protection in the background technology;
Fig. 2 is the special chip structured flowchart that is used for relay protection that adopts the present invention's design;
Fig. 3 is a data acquisition module interface block diagram;
Fig. 4 carries out overcurrent protection algoritic module figure;
Fig. 5 is a low-frequency load reduction protection module structured flowchart;
Fig. 6 is a special chip platelet structure figure;
Fig. 7 is the definition of special chip external pin;
The photo in kind of the route protection special chip that Fig. 8 design is finished;
Fig. 9 is the first programmable gate array external cabling schematic diagram that constitutes special chip;
Figure 10 is the external cabling schematic diagram that constitutes second programmable gate array of special chip;
Figure 11 is to the jtag interface of special chip programming and the elementary diagram of outside ROM (read-only memory).
Five, embodiment
For a more clear understanding of the present invention, comply with the embodiment that technical scheme of the present invention is finished below in conjunction with accompanying drawing and inventor, the present invention is described in further detail.
Referring to accompanying drawing 3～8; Fig. 3 is a data acquisition module interface block diagram; This module provides with the interface of the commonly used modulus conversion chip MAX125 of present Microcomputer Protection, has finished the storage of controlling of sampling and corresponding data.Two groups of each four tunnel input channels that MAX125 is integrated, the analog to digital conversion time of 14 bit resolutions and 3 μ s, 14 double port memories and with the parallel interface of most of microprocessor compatibilities.Cooperate traffic pilot, this module has been finished the collection of 16 analog channels and the storage of data.Module produces all signals and the sequential that the analog to digital conversion interface needs, and reads transformation result during EOC and stores in the chip internal storer.
Fig. 4 is overcurrent protection algoritic module figure;
This module is made up of a comparer and a timer, comparer has the data Data1 and the Data2 of two input ends, Data1 is from the output result of dedicated tunnel data processing module, and Data2 is from predefined definite value, and the parameter of timer is also given by definite value.In the content stores of the definite value storer externally, set by panel in advance or revise wherein content by telecommunication, its content is read in the storer of chip internal during system initialization, by the input of scheduler module control as Data2 among the figure.As real time data Data1 during greater than definite value Data2, the output signal of comparer starts timer work by low uprising.The timer timing is used to drive relay and finishes the tripping operation action to the trigger pulse of then exporting specified width, which width.Producing the corresponding order event information simultaneously is used for teletransmission and records nonvolatile memory.In case the situation of Data1 less than Data2 occur at the timer duration of work, the output of comparer will be resetted to timer by high step-down.Whether enable signal is used to select this defencive function of locking, and it can move back selection from the throwing of this defencive function, also can be from the output of other protection modules.This typical protection module except can finishing simple protection such as syllogic overcurrent protection, superpotential, zero sequence, can also be realized the algorithm of more complicated by combination.
Fig. 5 is a low-frequency load reduction protection module structured flowchart;
Low-frequency load reduction module and overcurrent protection difference are that the former is real time data comparer upset during greater than definite value, and the latter is then opposite, and should have functions such as slippage and low-voltage dead lock.The judgement of low pressure gets final product with identical module, but the input of slippage can not directly come self-metering frequency, and need carry out the calculating of df/dt.Here consider simplified design, with double this differential value of difference on the frequency approximate representation that records.Consider that again voltage transformer disconnection wants the locking low-voltage module.
Fig. 6 is a special chip platelet structure figure; Symbolic representation is among the figure, the 1-programmable gate array chip; The 2-JTAG interface; The 3-DIP switch; The outside ROM (read-only memory) of 4-configurating programmable gate array; The fixed interface that 5-is connected with mainboard; The active crystal oscillator of 6-; The 7-measuring point; 8-core voltage and input and output voltage indication.
This module appears in the hardware of system with the form of an independent component, and the definition of having fixed interface 5 also just is equivalent to determine the pin of element.The function that realizes as for element is then determined by the programming of programmable gate array chip.In this design, that programmable gate array chip 1 adopts is the EP1K100-3 of ALTERA company, can change the product of other (as: Xilinx, Actel etc.) companies in fact into.The programming technology of chip also both can be based on program storage also can be based on flash memory or anti-fuse structures.
The 2nd, the jtag interface of standard supports that directly connecting the downloaded program reconfigures chip.
The 3rd, DIP switch is used for selecting programmable gate array chip still to be powered on by the jtag interface configuration and is just loaded by outside ROM (read-only memory).
The 4th, deposit the outside ROM (read-only memory) of programmable gate array loading procedure.
The 7th, the outside measuring point of connection programmable gate array chip pin can be assigned to the arbitrary signal in the chip on these pins in exploitation and debug phase, by the correctness that oscillograph, logic analyser etc. are tested and checking designs.In case design is finished, and can reassign these functions of pins.For example, as the expansion interface of external unit, as general I/O etc.
Fig. 7 is the pinout that special chip is connected with mainboard.Main signal comprises: the core power supply; The I/O power supply; Systematically; With 14 data lines of analog to digital converter interface, 8 control lines; The input of frequency measurement signal; 8 LED indications; 8/16 relay control output; 16/24 switching value input; Article 14, totally 200 pins such as interface of microprocessor.60 pins have also been drawn in addition as test point.
The photo in kind of the route protection special chip that Fig. 8 design is finished.
Fig. 9, Figure 10 are the external cabling schematic diagrams that constitutes two programmable gate arrays of special chip.
Figure 11 is the jtag interface of special chip programming and the elementary diagram of outside ROM (read-only memory).
Programmable gate array chip in this design is the EP1K100PQ208-3 that has used two altera corps, and first collection pre-service of finishing data finished various protection algorithms, PERCOM peripheral communication, control output etc. for second.The actual protection algorithm of finishing has: fast tripping protection, prescribe a time limit fast tripping protection, overcurrent protection, overload alarm and protection, low-frequency load reduction, zero-sequence current, zero-sequence voltage protection, reclosing (band after-acceleration) etc.
In fact these functions also can be transplanted in the chip of Related product of other companies such as monolithic ACTEL APA300 of company or Xilinx.
Below be the embodiment that the inventor finishes.
5.1 the structure of chip
Intelligent electrical apparatus is as the primary element of Automation of Electric Systems.It must monitor the parameters such as electric current, voltage of protected object, in case that parameter occurs is unusual, device should be protected action according to set protection algorithm.It mainly comprises main contents such as data acquisition, data processing, protection algorithm, communication module and man-machine interface from function.Therefore, correctly take out the universal model of intelligent electrical apparatus, rationally divide interface definition between each functions of modules, each module of standard, design the key that a series of general functional modules just become the design of intelligent electrical apparatus special chip.Traditional method for designing is to be designed to the basis with function, and the system-on-chip designs method is then to design multiplexing or function is assembled into the basis.Promptly build the system of a complexity on chip with several large-scale macroblocks, these macroblocks of having developed are exactly general intellecture property functional module.Reusing complexity that can alleviate our design to a great extent and the time that designing institute needs of these functional module products.
Design this special chip and be used for the electric current, voltage, temperature etc. of monitor protection object and can reach 16 road analog signalses, can finish the frequency etc. of storage, metrical pulse electric degree and the AC signal of fast fourier transform and data as required to each analog quantity at chip internal.Computing function mainly includes the calculating of the calculating of effect value, active power and reactive power and power factor etc.Can handle nearly 48 way switch amount signals.Communication function can provide 232/485 interface of standard and the interface of fieldbus, by connecting and composing comprehensive automation system of transformer substation with host computer.The structure of chip as shown in Figure 2.
5.2 intelligent electric appliance special chip function module design
A. data acquisition
Voltage to frequency converter, serial analog to digital converter and parallel A/D converter etc. are adopted in existing microcomputer protecting device data acquisition usually, and each scheme can be designed to corresponding functional modules.Though someone designs in the mode of application-specific rather than in the mode of a general utility functions module.Here introduce a kind of parallel analog to digital conversion acquisition control module that we have succeeded in developing and have obtained to use.This module provides with the interface of the modulus conversion chip MAX125 that Microcomputer Protection is commonly used at present, has finished the storage of controlling of sampling and corresponding data.Two groups of each four tunnel input channels (four sampling holders) that MAX125 is integrated, the analog to digital conversion time of 14 bit resolutions and 3 μ s, 14 double port memories and with the parallel interface of most of microprocessor compatibilities.Cooperate traffic pilot, this module has been finished the collection of 16 analog channels and the storage of data.Module produces all signals and the sequential that the analog to digital conversion interface needs, and reads transformation result and stores in the chip internal storer, and its structural drawing is seen Fig. 3.
To the measurement of mains frequency here usefulness be to survey week to ask down method.At first to the input AC signal carry out shaping, then to its weekly high level part high-frequency count obtain period T.
By:
Order: T=T
0+ Δ T then works as T
0During＞＞Δ T, launch and get preceding two and can get by Taylor's radix:
F is an actual frequency in the following formula, T
0Be nominal period, T is an actual cycle, and Δ T is an actual error.Through such conversion as can be seen, division arithmetic is turned to the multiplying of subtraction and constant and variable.Simplified program design, the resource of saving chip has been played very big effect.
B. data processing
Data processing is one of main contents of intelligent electrical apparatus, generally includes effective value calculating, power calculation, frequency measurement and to fast fourier transform of AC sampling data etc.On filtering algorithm, except that the fast fourier transform of routine, wavelet transformation theory had also obtained successful application in the relay protection field in recent years, the report that also has programmable gate array to realize aspect electric energy quality monitoring.Because have the advantage of speed, the functional module that designs general wavelet transformation is only the key that related algorithm is achieved.
In the design of general Fourier transform module, the input data allow can establish by parameter from 16 o'clock by 1024 o'clock.It needs two memory blocks in design process, is respectively applied for intermediate result and the twiddle factor parameter of depositing computing, and the user can freely be provided with the position of memory block when configuration fast fourier transform module.The base 2 butterfly algorithms that adopt take one take advantage of again with two be added with device.The output result is the real part and the imaginary values of 16 Fourier transforms.Changeover control signal can be controlled this module and what data to carry out the calculating of a Fourier every, thereby adapts to the requirement of friction speed and precision.
C. protect algoritic module
In electric system, different object of protections has different protection algorithms, even same object of protection also often needs the combination of kinds of protect algorithm.For example, route protection uses syllogic current protection, zero-sequenceprotection, distance protection, longitudinal difference protection etc. usually; Therefore, need design series protection algoritic module to use for system configuration.Usually the input data of each protection algoritic module all comprise the definite value of one or several real time data and some.The corresponding relation of each data is realized by the data dispatch module of system.
For example, protection of three-phase current syllogic and the protection of zero-sequence current syllogic etc. all are most widely used protection algorithms in the relay protection, and in fact, these modules are except the definite value difference, and the structure of module is identical.Its typical case's protection algorithm as shown in Figure 4.This module is made up of a comparer and a timer, comparer has the data Data1 and the Data2 of two input ends, Data1 is from the output result of dedicated tunnel data processing module, and Data2 is from predefined definite value, and the parameter of timer is also given by definite value.In the content stores of the definite value storer externally, set by panel in advance or revise wherein content by telecommunication, its content is read in the storer of chip internal during system initialization, by the input of scheduler module control as Data2 among the figure.As real time data Data1 during greater than definite value Data2, the output signal of comparer starts timer work by low uprising.The timer timing is used to drive relay and finishes the tripping operation action to the trigger pulse of then exporting specified width, which width.Producing the corresponding order event information simultaneously is used for teletransmission and records nonvolatile memory.In case the situation of Data1 less than Data2 occur at the timer duration of work, the output of comparer will be resetted to timer by high step-down.Whether enable signal is used to select this defencive function of locking, and it can move back selection from the throwing of this defencive function, also can be from the output of other protection modules.This typical protection module except can finishing simple protection such as syllogic overcurrent protection, superpotential, zero sequence, can also be realized the algorithm of more complicated by combination.
Low-frequency load reduction module and above module class seemingly, difference is that the former is real time data comparer upset during greater than definite value, the latter is then opposite, and should have functions such as slippage and low-voltage dead lock.The judgement of low pressure gets final product with identical module, but the input of slippage can not directly come self-metering frequency, and need carry out the calculating of df/dt.Here consider simplified design, with double this differential value of difference on the frequency approximate representation that records.Consider that again voltage transformer disconnection wants the locking low-voltage module, then the The general frame of low-frequency load reduction module is seen Fig. 5.
D. peripheral control unit and memory interface
The interface of peripheral control unit mainly is can constitute complicated more system with ppu for chip.For example, in order to save the resource of chip, a series of different communication interfaces and different communication protocols can be realized with a general microprocessor, by be connected " four the is distant " function that can realize the electric system requirement, sending order logout etc. with host computer.The communication module of System on Chip/SoC only needs design chips just passable with interface between the peripheral control unit and communication protocol like this.Certainly, also the coprocessor of chip as another controller can be used as required, for example,, realize the control of protection tripping operation and other systemic-function with microprocessor with the collection and the wavelet transformation of programmable gate array realization data.The interface of realizing storer is a capacity limit of considering on-chip memory, and for example the failure wave-recording module all is rational selection to common hundreds of K of the demand of storer even tens M bytes no matter use external memory storage this moment technically or economically.So just can constitute a higher level hardware platform.
E. the scheduling of data and task
This module mainly comprises the scheduling of the scheduling of measured data, the scheduling of setting definite value, communication task, the parts such as scheduling of protection task.It is equivalent to a simple real-time multi-task operating system, also is the core of total system work.The fast fourier transform computing of different passages is finished successively in total system, and promptly the conversion start signal of each passage is from the EOC signal of a last passage.The data that obtain are kept in the on-chip memory successively, and the data dispatch module by system provides corresponding data for different protection algorithms.Definite value in each protection module is to be provided by the scheduling of setting definite value.
5.3 design example
According to above method, the applicant has designed the special chip of having finished route protection.The analog quantity of main monitoring comprises protective current IA, IB, IC; Metering current Ia, Ib, Ic, I
0Voltage U ab, Ucb, U
0The function of finishing mainly contains:
A. function of measuring: accurate measurement three-phase current, three-phase voltage (0.2 grade), supply frequency (+parameter such as 0.02Hz).16 times that can measure dedicated tunnel with interior harmonic value (1 grade).
B. defencive function: defencive function has quick-break, quick-break in limited time, excess current, overload, low-frequency load reduction, reclosing (the band after-acceleration is jumped), zero-sequence current, residual voltage etc.
C. communication function: can finish " four is distant " function with standard 232/485 or Lonworks fieldbus and upper machine communication.
D. control function: can finish by panel isolating switch branch, closing operation and systematic parameter function is set.
Can open or close teleswitch and divide closing operation by hardware lock in addition, or protect definite value to set, the analog quantity channel coefficient be adjusted, the setting that the defencive function throwing is moved back and system is provided with.This protected location can store and show 20 sequential affair records, real-time circuit analog value, the real-time status of current/voltage harmonic wave histogram and circuit definition switching value.
Its structure is seen Fig. 6, and Fig. 7 is the definition of its external pin.This module appears in the hardware of system with the form of an independent component, and the definition of having fixed interface 5 also just is equivalent to determine the pin of element.The function that realizes as for element is then determined by the programming of programmable gate array chip.In this design, that programmable gate array chip 1 adopts is the EP1K100-3 of ALTERA company, can change the product of other (as: Xilinx, Actel etc.) companies in fact into.The programming technology of chip also both can be based on data-carrier store also can be based on flash memory or anti-fuse structures.
Among Fig. 62 is jtag interfaces of standard, supports that directly connecting the downloaded program reconfigures chip; The 3rd, DIP switch is used for selecting programmable gate array chip still to be powered on by the jtag interface configuration and is just loaded by external program memory; The 4th, deposit the external memory storage of programmable gate array chip loading procedure; The 7th, the outside measuring point of connection programmable gate array chip pin can be assigned to the arbitrary signal in the chip on these pins in exploitation and debug phase, by the correctness that oscillograph, logic analyser etc. are tested and checking designs.In case design is finished, and can reassign these functions of pins.For example, as the expansion interface of external unit, as general IO interface etc.
This special chip partly adopts 2 100,000 programmable gate array chips (EP1k100-3), has wherein finished data acquisition and data processing for first, finishes protection algorithm, external communication, task scheduling etc. for second.The all functions module all adopts the standard hardware descriptive language to write, and the comprehensive exploitation environment uses the Maxplus II of altera corp.By logic analyser, simulating, verifying the correctness of entire chip function, finally passed through the dependence test of national relay quality inspection and supervision monitoring center based on every performance index of the line protective devices of this chip design.The photo in kind of special chip is seen shown in Figure 8.
Resources of chip utilizes situation such as table 4.1 and 4.2:
First chip occupation condition of table 4.1
| First | Take quantity | Quantity available | Occupation proportion |
| Logical block | 4253 | 4992 | 85％ |
| The embedded |
12 | 12 | 100％ |
Second chip occupation condition of table 4.2
| Second | Take quantity | Quantity available | Occupation proportion |
| Logical block | 3248 | 4992 | 65％ |
| The embedded | 2 | 12 | 17％ |
Claims (6)
1. intelligent electric appliance special chip, it is characterized in that, this chip is made of field programmable gate array, the function of chip is determined by a series of functional module combinations, these functional modules are divided into general module and special module two parts, general module partly is used to construct the structure of chip, and special module partly is used to realize the application requirements of different protection equipment; General module mainly comprises data acquisition module, data processing module, communication module, data and task scheduling modules, external memory interface module; Special module mainly refers to series protection algoritic module, switching value input/output module;
Data acquisition module is used to finish special chip with the interface of outside mould/number conversion and relevant control, realizes the collection and the storage of 16 channel datas;
Data processing module, the fast Flourier filtering algorithm, the effective value that are used for finishing successively 16 channel datas calculate; Power calculation; And result stored;
Communication module is used for chip and the external unit data communication interface with serial mode, utilizes the different communication protocol of programmable characteristics design;
The external memory interface module is used to provide the control of external memory storage being read and write in the mode of parallel or serial;
Data and task scheduling modules, this module are the cores of total system work, mainly comprise the scheduling of the scheduling of measured data, the scheduling of setting definite value, communication task, the parts such as scheduling of protection task, are equivalent to a simple real-time multi-task operating system; By being set, control provides corresponding data to each protection algorithm, in case increase or delete a protection algoritic module, except will being provided with to the corresponding protection module, also task scheduling modules to be set, determine that the priority of each task is harmonious with the data message that guarantees corresponding task and this task needs;
The annexation of above-mentioned intermodule is that the data output that data acquisition module obtains is as the data input of data processing module; The results of data processing is the data input of protection algorithm; Communication module then can be obtained data or provide data to other correlation module according to the requirement of communication protocol from disparate modules; All data are transmitted by internal bus; Total system is by data and task scheduling modules uniform dispatching and management.
2. intelligent electric appliance special chip as claimed in claim 1; it is characterized in that described series protection algoritic module comprises: fast tripping protection, prescribe a time limit fast tripping protection, overcurrent protection, low-frequency load reduction, reclosing, zero-sequence current protection, zero-sequence voltage protection, differential protection, inverse time-lag protection module.
3. intelligent electric appliance special chip as claimed in claim 1 is characterized in that, described data acquisition module is provided with by parameter and selects different sampling rates; Data processing module is selected the length of counting of input data and each point; Each protection module allow to select input data from which passage, which definite value gets the first-harmonic data or get higher hamonic wave data, given definite value be, protect enable signal from where; Data and task scheduling modules are specified the corresponding data channel of each protection algorithm then by parameter is set; Communication module is provided with different baud rates and communication protocol.
4. intelligent electric appliance special chip as claimed in claim 1 is characterized in that, the realization function of described intelligent electric appliance special chip is by the programming decision of field programmable gate array chip.
5. intelligent electric appliance special chip as claimed in claim 4, it is characterized in that, described field programmable gate array chip quantity is a slice or two or multi-disc, and this special chip is connected with other circuit as an independent component with the form of a little printed circuit board (PCB);
6. intelligent electric appliance special chip as claimed in claim 1, it is characterized in that, described intelligent electric appliance special chip is reserved with the part pin as outside measuring point, arbitrary signal in the chip can be assigned to these measuring points in exploitation and debug phase, by the correctness that oscillograph, logic analyser etc. are tested and checking designs, in case design is finished, and can reassign these functions of pins by program.
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| CN108021781A (en) * | 2018-01-31 | 2018-05-11 | 中国电子科技集团公司第五十四研究所 | The FFT IP core designs and optimization method of a kind of parameterisable |
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| CN111859827B (en) * | 2020-06-29 | 2022-06-17 | 山东云海国创云计算装备产业创新中心有限公司 | Chip IP integration method and device, electronic equipment and storage medium |
| CN112880657B (en) * | 2021-01-15 | 2023-02-07 | 清华大学 | System on chip for demodulating and controlling MEMS resonant gyroscope signal |
| CN113742280B (en) * | 2021-07-14 | 2023-07-28 | 江西昌河航空工业有限公司 | Dual ARM system capable of customizing communication protocol |
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