CN100464267C - Bus protocol analysis chip for servocontrol - Google Patents
Bus protocol analysis chip for servocontrol Download PDFInfo
- Publication number
- CN100464267C CN100464267C CNB2007100100550A CN200710010055A CN100464267C CN 100464267 C CN100464267 C CN 100464267C CN B2007100100550 A CNB2007100100550 A CN B2007100100550A CN 200710010055 A CN200710010055 A CN 200710010055A CN 100464267 C CN100464267 C CN 100464267C
- Authority
- CN
- China
- Prior art keywords
- module
- data
- protocol analysis
- bus protocol
- plc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Programmable Controllers (AREA)
Abstract
The invention discloses a bus protocol analysis chip for servo control, including: two bus protocol analysis modules, used for exchanging information with PC through the physical layer control module, according to the communication protocol to analyze information data; a parallel bus interface module, used for exchanging information with the servo driver control part outside the chip; a PLC module, used for completing the PLC control input and output; an encoder/grating foot processing module, used for processing the incremental encoder signals; a number of data register modules, used for data storage in order to transmit the data among the modules. The ASIC of the invention has the features of high single-chip integration, simplified circuit design, low debug complexity, and low cost.
Description
Technical field
The present invention relates to the chip that a kind of digital control system is used, more particularly, relate to a kind of in servo-driver the special chip of host computer and servo driver control part communication realization power drive.
Background technology
General number bus formula servo-drive system as shown in Figure 1, should comprise as the lower part: bus protocol analysis chip+servo driver control part+power drive part.During closed-loop control the encoder feedback processing section need be set.In digital control system, the point of a lot of switching values need be controlled by PLC, therefore also can dispose the PLC controller.Usually these parts all are to be realized by individual chips, finish on the plate by bus between the various piece and communicate by letter, and realize servocontrol.Problem is, the chip of multi-disc standalone feature, not only cost height, and debugging complexity.
Summary of the invention
At the problems referred to above, the invention provides a kind of in digital control system servo-driver private communication protocol interface chip, its purpose at the customization bus protocol, the multiple functional chip of prior art is integrated into a slice, to reduce cost convenient debugging, the stability of intensifier circuit.
To achieve these goals, the present invention has designed a kind of servo-controlled bus protocol analysis chip that is used for, comprise: 1, two bus protocol analysis modules are used for by a Physical layer control module and host computer interactive information, according to communications protocol resolving information data; 2, parallel bus interface module is used for the servo driver control part interactive information with chip exterior; 3, PLC module is used to finish input, the output of PLC control; 4, encoder processing module is used for incremental encoding or grating chi signal are handled; And data register module, be used for data storage so that the mutual forwarding of data between each module.Wherein, first bus protocol analysis module is by interaction data between data register and the parallel bus interface module; First bus protocol analysis module is also obtained the actual location data that the encoder processing module is deposited by the visit data register; Second bus protocol analysis module is by interaction data between data register and the PLC module; The encoder processing module is also by interaction data between data register and the parallel bus interface module.
The present invention is used for servo-controlled bus protocol analysis chip, and its further characteristics are that above-mentioned PLC module comprises the PLC I/O interface of 24 inputs, 16 outputs.And above-mentioned encoder processing module is incremental encoder/grating chi processing module.
By technique scheme, the present invention is used for servo-controlled bus protocol analysis chip and has following beneficial effect:
1, monolithic integrated level height, integrated 24 inputs, 16 output PLC in the chip, encoder feedback control, the function of parallel bus controller and bus protocol analysis circuit module.
2, simplify circuit design, do not need independent CPU control module to realize 24 inputs, 16 output PLC.
3, debug complexity, the integrated multiple function of chip has reduced the complexity of combined debugging between the chip.
4, low cost, the single-chip integrated level improves, and this function that needs the multi-disc special chip to realize is realized by monolithic.
Description of drawings
Fig. 1 is the functional block diagram of bus type servo-driver in the prior art;
Fig. 2 is a functional module structure synoptic diagram of selecting the bus type servo-driver of chip realization of the present invention for use;
Fig. 3 is the internal module block diagram of chip of the present invention.
Fig. 4 is to the regulation synoptic diagram of circulation sequential in a kind of communication protocol;
Fig. 5 be with same communication protocol shown in Figure 4 in the data structure of servocontrol driver;
Fig. 6 stipulates write section divided data institutional framework among Fig. 5;
Fig. 7 is to reading partial data institutional framework regulation among Fig. 5.
Embodiment
The structure of bus type servo-driver as shown in Figure 2, the functional module that chip wherein of the present invention need be finished is positioned at indicates the GDS06C frame, mainly comprises bus protocol analysis functional circuit, PLC interface circuit and incremental encoder and grating chi module.Usually, Zhuan Yong servo driver control part selects for use DSP servocontrol or FPGA servocontrol to realize.
In the module frame chart 3, GDS06C represents chip of the present invention, comprise two bus protocol analysis modules, a parallel bus interface module, a PLC module, an encoder processing module, an encoder processing module, and the data register module of a plurality of realization data forwarding.
1, bus protocol analysis module is mainly according to particular communication protocol analysis information data.Specifically, velocity location and the PLC control data that main control computer can be sent are resolved, send to the servocontrol module then and handle, the current encoder position of servo acquisition, the variation of PLC input point, the information such as state of servo-driver can be returned to main control computer and numerical control software by bus simultaneously.
For example shown in Fig. 4-7, in a kind of basic structure of making datagram in the agreement by oneself.
The circulation of an agreement is sent by 2 spaced data and forms as seen from Figure 4: the quick byte frame of the Frame of 962 bytes, 8 bytes.Wherein, the Frame function of 962 bytes comprises that host computer issues the order of servo controller and the data that slave unit returns.The function of the quick byte frame of 8 bytes comprises that order and data synchronization that host computer sends enable, i.e. the information of directive command execution.962 (962=2+40 * 24) byte data frames is with 16 system AA, and BB follows the tree certificate of 24 bus type servo-drivers afterwards as start byte, and each bus type servo-driver distributes 40 byte spaces.As Fig. 5, preceding 16 bytes are the data that write from host computer, and back 24 bytes are the data that will turn back to host computer.Write data division data organizational structure as shown in Figure 6, read the partial data institutional framework as shown in Figure 7.
The structure of above-mentioned agreement customizes as required, belongs to the intellection scope, and for example the meaning represented of byte length, each field has form separately in different agreement.But when adopting after standard agreement or custom protocol determine, the circuit of bus protocol analysis module is also just decided, therefore also can finish the analytical capabilities of data, for example finish the position data that host computer sends, the extraction of speed data, and the analysis of the status data of machine feedback.
2, parallel bus interface module is mainly used in the servo driver control part interactive information with chip exterior.Servocontrol is partly selected DSP or FPGA for use, carries out exchanges data by parallel bus.
3, PLC module, 24 inputs, 16 output PLC modules are fetched from the control data of host computer to output port from the plc data register read in interpolation cycle, finish all port scanning and oneself state and detect, and put the data of input port into the plc data register.
4, encoder processing module is finished the function of incremental encoder and grating chi feedback processing mechanism, can carry out frequency multiplication and counting processing to the incremental encoder or the grating chi signal of input, and data are returned to host computer by bus.
5, at chip internal, data are to realize mutual between each module by register and internal bus.
6, Physical layer control module is used for the transmitting-receiving control of Physical layer transmitting data.
The chip of embodiment among Fig. 3, its course of work are the servo data register district that superposed bus protocol analysis module will leave corresponding servo driving in from the position and the speed data of numerical control software among the figure; The servo driving part reads relevant data by the servo data register district of parallel bus interface module accesses internal bus, carries out s operation control; The servo driving part is delivered to servo data register district to control result and current state by the parallel bus interface module simultaneously, and host computer is taken data away in the corresponding operating cycle.
The actual location data of incremental encoder or grating chi is the part of servo-driver return data, realizes because frequency multiplication and counting are easier to design by the FPGA ratio, so the design of the control function of incremental encoder and grating chi is at chip internal.Absolute value encoder is relative complex because control is got up, and finishes corresponding reading and control function by servo driver control part.Data are sent to position data register 1 zone by parallel bus.The value of feedback of incremental encoder in functional planning/grating chi/absolute value encoder all is to belong to the servo driving part.Because different with supply servo driving partial data form, so data are provided for respectively two parts at 2 registers of inner setting with processing requirements to the bus feedback data.In incremental encoder and the grating chi module counted data is carried out being placed on location register 1 and location register 2 respectively after the different disposal.Wherein location register 1 is handled for bus protocol and is used; The part of location register 2 is used for the processing of servocontrol part, and the servocontrol part can be visited it by parallel bus.
The bus protocol analysis module that is positioned at the bottom among the figure is responsible for PLC from the PLC control data of host computer reception from bus, puts the plc data register corresponding to 24 inputs, 16 output PLC equipment into; Read that PLC input port data return to host computer in the PLC register.
The specific implementation method is used the emulation device FPGA, adopts special-purpose Hardware Description Language VHDL Programming with Pascal Language, guarantees to write the portability of code.Adopt method from bottom to top, divide module, write little functional module with VHDL language respectively according to function.The file of top layer adopts the map of VHDL language to be connected with the PORT mode, like this She Ji file portability, readable good.
The above; only be the preferable embodiment of the present invention; but protection scope of the present invention is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the present invention discloses; be equal to replacement or change according to technical scheme of the present invention and inventive concept thereof, all should be encompassed within protection scope of the present invention.
Claims (3)
1. one kind is used for servo-controlled bus protocol analysis chip, it is characterized in that, comprising:
Two bus protocol analysis modules are used for by a Physical layer control module and host computer interactive information, according to communications protocol resolving information data;
A parallel bus interface module is used for the servo driver control part interactive information with chip exterior;
A PLC module is used to finish input, the output of PLC control;
An encoder processing module is used for incremental encoding or grating chi signal are handled;
Data register module is used for data storage so that data mutual between each module;
Wherein,
First bus protocol analysis module is by interaction data between data register and the described parallel bus interface module;
First bus protocol analysis module is also obtained the actual location data that described encoder processing module is deposited by the visit data register;
Second bus protocol analysis module is by interaction data between data register and the described PLC module;
Described encoder processing module is by interaction data between data register and the described parallel bus interface module.
2. according to claim 1ly be used for servo-controlled bus protocol analysis chip, it is characterized in that described PLC module comprises the PLC I/O interfaces of 24 inputs, 16 outputs.
3. according to claim 1 and 2ly be used for servo-controlled bus protocol analysis chip, it is characterized in that described encoder processing module is incremental encoder/grating chi processing module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100100550A CN100464267C (en) | 2007-01-15 | 2007-01-15 | Bus protocol analysis chip for servocontrol |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100100550A CN100464267C (en) | 2007-01-15 | 2007-01-15 | Bus protocol analysis chip for servocontrol |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101013313A CN101013313A (en) | 2007-08-08 |
| CN100464267C true CN100464267C (en) | 2009-02-25 |
Family
ID=38700866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100100550A Active CN100464267C (en) | 2007-01-15 | 2007-01-15 | Bus protocol analysis chip for servocontrol |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100464267C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101226408B (en) * | 2008-01-24 | 2011-07-20 | 南京埃斯顿自动控制技术有限公司 | AC servo absolute value encoder position feedback pulse frequency dividing output method and circuit |
| WO2013033889A1 (en) * | 2011-09-06 | 2013-03-14 | 长沙中联重工科技发展股份有限公司 | Method for communicating with plc and upper computer |
| CN104914782B (en) * | 2014-03-10 | 2017-11-21 | 深圳市蓝海华腾技术股份有限公司 | A kind of data communication method and relevant device of the servo-driver of numerically-controlled machine tool |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1268831A (en) * | 1999-03-31 | 2000-10-04 | 中国科学院空间科学与应用研究中心 | Remote terminal of multichannel transmission data bus |
| CN2476390Y (en) * | 2001-04-26 | 2002-02-13 | 王玉琳 | Numerical control device used in numerical control machine |
| CN1438593A (en) * | 2003-01-15 | 2003-08-27 | 西安交通大学 | Design method for specific chip of intelligent electric appliance |
| CN2651848Y (en) * | 2003-11-06 | 2004-10-27 | 南京师范大学 | Field bus agreement conversion devices |
| US20050049727A1 (en) * | 1994-10-24 | 2005-03-03 | Fisher-Rosemount Systems, Inc. | Wireless communications within a process control system using a bus protocol |
| CN200997071Y (en) * | 2007-01-15 | 2007-12-26 | 大连光洋科技工程有限公司 | Bus protocol analytic chip for servo control |
-
2007
- 2007-01-15 CN CNB2007100100550A patent/CN100464267C/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050049727A1 (en) * | 1994-10-24 | 2005-03-03 | Fisher-Rosemount Systems, Inc. | Wireless communications within a process control system using a bus protocol |
| CN1268831A (en) * | 1999-03-31 | 2000-10-04 | 中国科学院空间科学与应用研究中心 | Remote terminal of multichannel transmission data bus |
| CN2476390Y (en) * | 2001-04-26 | 2002-02-13 | 王玉琳 | Numerical control device used in numerical control machine |
| CN1438593A (en) * | 2003-01-15 | 2003-08-27 | 西安交通大学 | Design method for specific chip of intelligent electric appliance |
| CN2651848Y (en) * | 2003-11-06 | 2004-10-27 | 南京师范大学 | Field bus agreement conversion devices |
| CN200997071Y (en) * | 2007-01-15 | 2007-12-26 | 大连光洋科技工程有限公司 | Bus protocol analytic chip for servo control |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101013313A (en) | 2007-08-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100568131C (en) | Multi-axis motion controller based on MPC5200 | |
| CN101546185B (en) | Programmable multi-axis controller based on IEEE-1394 serial bus | |
| CN103425106B (en) | The master/slave station control system of a kind of EtherCAT based on Linux and method | |
| CN101266482B (en) | Four-axis movement control card based on singlechip | |
| CN105242640B (en) | A kind of novel high-speed, high precision multiple-axis servo motion controller circuit | |
| CN105511502A (en) | VPX bus-based workpiece bench synchronous motion control system and method | |
| CN102591250B (en) | Dual-CPU (central processing unit) combined type motion controller | |
| CN103236217A (en) | Method and system for simulating multisystem synchronous numerical-control processing | |
| CN102722126A (en) | Four-roll plate bending machine control system based on advanced RISC machine (ARM) and Wince | |
| CN102122149A (en) | Embedded control system for carton proofing machine and control method thereof | |
| CN100464267C (en) | Bus protocol analysis chip for servocontrol | |
| CN103941650A (en) | Logic and movement integrated controller | |
| CN1936745A (en) | Inlaid numerical control system based on ARM and DSP | |
| CN201163363Y (en) | General multi-axis motion control system on numerical control machine | |
| CN103453933A (en) | Agricultural machine working parameter integrated monitoring platform and using method thereof | |
| CN101008842A (en) | Device for integrating manual pulse generator with bus type machine tools control panel | |
| CN200997071Y (en) | Bus protocol analytic chip for servo control | |
| CN104518716A (en) | Closed loop control system for miniature direct current motor and control method for system | |
| CN105955202A (en) | Network-based economical embedded five-axis numerical control system and control method thereof | |
| CN203376604U (en) | Full closed-loop numerical control system feedback circuit realized by AC servo drive | |
| CN201508489U (en) | Automatic centralized control system | |
| CN104238420A (en) | Servosystem high-speed data interactive communication unit based on USB | |
| CN103135495A (en) | Control system for numerical control cutting machine | |
| CN103075961A (en) | Position measuring and displaying device and method for supporting a plurality of grating rules based on single chip field programmable gate array (FPGA) | |
| CN102854376A (en) | Digital voltmeter and measuring method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: DALIAN KEDE CNC CO., LTD. Free format text: FORMER OWNER: DALIAN GUANGYANG TECHNOLOGY GROUP CO., LTD. Effective date: 20150731 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| C56 | Change in the name or address of the patentee |
Owner name: DALIAN GUANGYANG TECHNOLOGY GROUP CO., LTD. Free format text: FORMER NAME: DALIAN GUANGYANG SCI. + TECH. ENGINEERING CO., LTD. |
|
| CP03 | Change of name, title or address |
Address after: 116600 No. 6, Longquan street, Dalian economic and Technological Development Zone, Liaoning Patentee after: DALIAN GUANGYANG SCIENCE & TECHNOLOGY GROUP Co.,Ltd. Address before: 116600 Dalian economic and Technological Development Zone, Liaoning, No. 6 Longquan Street Patentee before: Dalian Guangyang Science & Technology Engineering Co.,Ltd. |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20150731 Address after: 116600 No. 8, the Yellow Sea street, Dalian economic and Technological Development Zone, Liaoning Patentee after: DALIAN KEDE NUMERICAL CONTROL Co.,Ltd. Address before: 116600 No. 6, Longquan street, Dalian economic and Technological Development Zone, Liaoning Patentee before: DALIAN GUANGYANG SCIENCE & TECHNOLOGY GROUP Co.,Ltd. |
|
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 116600 No. 8, the Yellow Sea street, Dalian economic and Technological Development Zone, Liaoning Patentee after: KEDE NUMERICAL CONTROL Co.,Ltd. Address before: 116600 No. 8, the Yellow Sea street, Dalian economic and Technological Development Zone, Liaoning Patentee before: DALIAN KEDE NUMERICAL CONTROL Co.,Ltd. |