CN104238420A - Servosystem high-speed data interactive communication unit based on USB - Google Patents

Abstract

The invention relates to a communication unit for high-speed data interaction of a USB-based servo system. Its technical scheme is: the COM end of described upper computer (1) is connected with the input and output end 2a of USB interface module (2); the data end of USB interface module (2) and control end 2b and the data end of FPGA (11) Connect with control end 11b, the data bus of FPGA (11) and the address bus are correspondingly connected with the data bus of DSP controller (8) and the address bus; The PWM input terminal is connected, and the two current feedback terminals of the permanent magnet synchronous motor (9) are correspondingly connected with the input terminals 8c and 8d of the DSP controller (8), and the position feedback terminal of the permanent magnet synchronous motor (9) is connected with the DSP controller ( 8) is connected to the input end 8b; the output end of the power drive module (10) is connected to the input end of the permanent magnet synchronous motor (9). The invention has the characteristics of simple structure, high transmission rate, stable transmission and convenient use.

Description

A Communication Unit for High Speed Data Interaction of Servo System Based on USB

technical field

The present invention belongs to the technical field of communication units for high-speed data interaction in servo systems. In particular, it relates to a communication unit for high-speed data interaction of a USB-based servo system.

Background technique

Servo systems aiming at high speed and high precision are widely used in high-tech fields such as laser processing, robots, and high-precision machine tools. As the control algorithm of the servo system becomes more and more complex, the servo control effect is largely determined by several related parameters of the algorithm. During the operation of the servo system, various state parameters, such as position, speed, error, etc., are obtained by modifying the algorithm parameters. basic basis. In the research and development process, in order to have a deeper and more convenient understanding of the operating status of the servo system, it is necessary to use a host computer to monitor and display the operating status of the servo system in real time. The motion state parameters of the servo system are complex and the amount of data transmission is large, so the data transmission rate is required to be high when the servo system and the host computer perform data interaction.

At present, the main methods of communication between the servo system and the host computer used in China are as follows: serial port communication, which has a simple structure, but the data transmission rate is low and the stability is poor, and the transmitted data is unreliable; optical fiber communication, the transmission rate is high And the transmission stability is good, but the cost is high, the structure is complicated, and it is not convenient to carry out data communication with conventional PC computers.

Contents of the invention

The present invention aims to overcome the defects of the prior art, and aims to provide a communication unit for high-speed data interaction of a servo system based on USB, which is convenient to use, stable in transmission and high in transmission rate.

In order to achieve the above object, the technical solution adopted in the present invention is: the communication unit includes: a host computer, a USB interface module, a keyboard and a display, an I/O interface, a field bus interface, a pulse input interface, an analog interface, and a DSP controller , FPGA, fault detection module, power drive module and permanent magnet synchronous motor.

The COM terminal of the host computer is connected to the input and output terminal 2a of the USB interface module. The data end of the USB interface module and the control end 2b are connected with the data end and the control end 11b of the FPGA, the input and output ends 3a of the keyboard and the display are connected with the control end 11c of the FPGA, and the input and output ends 4a of the I/O interface are connected with the control end of the FPGA. Terminal 11d is connected, the input and output terminal 5a of the fieldbus interface is connected with the control terminal 11e of FPGA, the input and output terminal 6a of the pulse input interface is connected with the control terminal 11f of FPGA, and the output terminal 12a of the fault detection module is connected with the input terminal 11a of FPGA , the data bus and the address bus of the FPGA are correspondingly connected to the data bus and the address bus of the DSP controller. The input and output terminals 7a of the analog interface are connected with the input and output ports 8a of the DSP controller, the PWM output terminals of the DSP controller are connected with the PWM input terminals of the power drive module, and the two current feedback terminals of the permanent magnet synchronous motor are connected with the DSP controller The input terminals 8c and 8d are connected correspondingly, the position feedback terminal of the permanent magnet synchronous motor is connected with the input terminal 8b of the DSP controller; the output terminal of the power drive module is connected with the input terminal of the permanent magnet synchronous motor.

The host computer is equipped with read-write USB interface software, FPGA is written with USB interface read-write logic timing control software, and FPGA is written with acquisition data framing operation software.

The USB interface module is composed of a USB interface and a USB control chip FT245RL, and the pins USBDM and USBDP of the USB control chip FT245RL are correspondingly connected with the pins UD- and UD+ of the USB interface.

The COM end of the host computer is connected to the input and output end 2a of the USB interface, the data signal pins D0-D7 of the USB control chip FT245RL, the write control signal input pin WR, the read control signal input pin RD, the full signal pin TXE and The empty signal pin RXF is correspondingly connected with the data input and output ports D0-D7 of the FPGA, the write control pin WR, the read control pin RD, the full signal input pin TXE and the empty signal input pin RXF in sequence.

The main process of the described read-write USB interface software is:

S-1. Obtain the port number of the USB interface;

S-2, enable the USB interface;

S-3. Judging whether to read data or write data, if it is read data, go to S-4, otherwise, go to S-7;

S-4. The host computer reads the data of the USB interface, and judges whether a frame of data has been read. If a frame of data is read, enter S-5. Otherwise, re-execute S-4;

S-5. After the upper computer receives a frame of data, it parses and caches the received data;

S-6. The upper computer judges whether all the data of the USB interface has been read, if all the data has been read, enter S-8, otherwise return to S-4;

S-7. The upper computer writes data to the USB interface, and judges whether the data writing operation is completed. If the writing data is completed, enter S-8, otherwise, execute S-7 again;

S-8. The data reading or writing is completed; the program ends.

The main flow of the read and write logic timing control software of the USB interface is:

S-1, FPGA judges whether to read data or write data, if it is read data, enter S-2, otherwise, enter S-5;

S-2, FPGA judges whether RXF is low level, if it is low level, enter S-3, otherwise, enter S-8;

S-3, RD set low level, execute data read operation, RD set high level;

S-4. The FPGA judges whether the data field is empty. If the data field is empty, set RXF to high level and enter S-8. Otherwise, return to S-3;

S-5, FPGA judges whether TXE is low level, if it is low level, enter S-6, otherwise, enter S-8;

S-6. Set WR to high level, execute data writing operation, and set WR to high level;

S-7. FPGA judges whether the data field is full, if the data field is full, TXE is set to high level, and enters S-8, otherwise, returns to S-6;

S-8. The program ends.

The main process of the described framing operation software for collecting data is:

S-1. FPGA integrates and frames the current data and position data collected by the DSP controller;

S-2. The FPGA adds a frame header to the integrated data.

Owing to adopting above-mentioned technical scheme, the present invention has following positive effect compared with prior art:

The invention utilizes the FPGA to control the read-write logic sequence of the USB control chip FT245RL, which ensures that the USB interface has the characteristics of high transmission rate and stable transmission. The USB control chip FT245RL has the function of mutual conversion between eight-bit parallel data and serial data, ensuring the accuracy of data interaction between the host computer and the servo system; the USB control chip FT245RL is easy to use, which makes the structure of the communication unit simple and shortens the development cycle. The host computer of the present invention performs high-speed data interaction with the servo system through the USB interface module, reads various state parameters of the servo system in real time, and displays the analysis results on the control interface of the host computer.

Therefore, the present invention has the characteristics of simple structure, convenient use, stable transmission and high transmission rate.

Description of drawings

Fig. 1 is a kind of structural representation of the present invention;

Fig. 2 is the structural representation of USB interface module 2 in Fig. 1;

Fig. 3 is the main flowchart of the read-write USB interface software of upper computer 1 among Fig. 1;

Fig. 4 is the main flowchart of the read and write logic sequence control software of the USB interface of FPGA11 in Fig. 1;

FIG. 5 is the main flow chart of the software for framing the collected data of FPGA11 in FIG. 1 .

Detailed ways

The present invention will be further described below in conjunction with accompanying drawing and specific embodiment, not limitation to protection scope:

A communication unit for high-speed data interaction of a USB-based servo system. As shown in Figure 1, the communication unit includes: host computer 1, USB interface module 2, keyboard and display 3, I/O interface 4, field bus interface 5, pulse input interface 6, analog quantity interface 7, DSP controller 8. FPGA 11 , fault detection module 12 , power drive module 10 and permanent magnet synchronous motor 9 .

The COM terminal of the host computer 1 is connected to the input and output terminal 2a of the USB interface module 2. The data end of USB interface module 2 and control end 2b are connected with the data end of FPGA11 and control end 11b, and the input and output end 3a of keyboard and display 3 is connected with the control end 11c of FPGA11, and the input and output end 4a of I/O interface 4 is connected with The control terminal 11d of FPGA11 is connected, and the input and output terminal 5a of fieldbus interface 5 is connected with the control terminal 11e of FPGA11, and the input and output terminal 6a of pulse input interface 6 is connected with the control terminal 11f of FPGA11, and the output terminal 12a of fault detection module 12 is connected with The input terminal 11 a of FPGA 11 is connected, and the data bus and address bus of FPGA 11 are correspondingly connected with the data bus and address bus of DSP controller 8 . The input and output terminals 7a of the analog quantity interface 7 are connected with the input and output ports 8a of the DSP controller 8, the PWM output terminals of the DSP controller 8 are connected with the PWM input terminals of the power drive module 10, and the two-way current feedback of the permanent magnet synchronous motor 9 end is connected with the input end 8c, 8d of DSP controller 8 correspondingly, the position feedback end of permanent magnet synchronous motor 9 is connected with the input end 8b of DSP controller 8; end connection.

The upper computer 1 is equipped with software for reading and writing the USB interface, the FPGA 11 is written with the reading and writing logic sequence control software for the USB interface, and the FPGA 11 is written with the software for framing the collected data.

As shown in Figure 2, described USB interface module 2 is made up of USB interface 2.1 and USB control chip FT245RL2.2, the pin USBDM of USB control chip FT245RL2.2, the pin USBDP and the pin UD- of USB interface 2.1 and Pin UD+ corresponds to the connection.

The COM end of the upper computer 1 is connected to the input and output end 2a of the USB interface 2.1, the data signal pins D0-D7 of the USB control chip FT245RL2.2, the write control signal input pin WR, the read control signal input pin RD, the full signal The pin TXE and the empty signal pin RXF are correspondingly connected with the data input and output ports D0-D7 of the FPGA11, the write control pin WR, the read control pin RD, the full signal input pin TXE and the empty signal input pin RXF in sequence.

As shown in Figure 3, the main process of the described read-write USB interface software is:

S-1. Obtain the port number of the USB interface 2.1;

S-2, USB interface 2.1 enable;

S-3. Judging whether to read data or write data, if it is read data, go to S-4, otherwise, go to S-7;

S-4. The upper computer 1 reads the data of the USB interface 2.1, and judges whether the reading of a frame of data is completed. If the reading of a frame of data is completed, enter S-5, otherwise, re-execute S-4;

S-5. After receiving a frame of data, the upper computer 1 parses and caches the received data;

S-6. The host computer 1 judges whether all the data of the USB interface 2.1 has been read, if all the data has been read, enter S-8, otherwise return to S-4;

S-7. The upper computer 1 writes data to the USB interface 2.1, and judges whether the data writing operation is completed. If the writing data is completed, enter S-8, otherwise, re-execute S-7;

S-8. The data reading or writing is completed; the program ends.

As shown in Figure 4, the main flow of the read and write logic timing control software of the USB interface is:

S-1, FPGA11 judges whether to read data or write data, if it is read data, enter S-2, otherwise, enter S-5;

S-2, FPGA11 judges whether RXF is low level, if it is low level, enter S-3, otherwise, enter S-8;

S-3, RD set low level, execute data read operation, RD set high level;

S-4, FPGA11 judges whether the data field is empty, if the data field is empty, RXF is set to high level, and enters S-8, otherwise, returns to execute S-3;

S-5, FPGA11 judges whether TXE is low level, if it is low level, enter S-6, otherwise, enter S-8;

S-6. Set WR to high level, execute data writing operation, and set WR to high level;

S-7, FPGA11 judges whether the data field is full, if the data field is full, TXE is set to high level, and enters S-8, otherwise, returns to S-6;

S-8. The program ends.

As shown in Figure 5, the main process of the described framing operation software for collecting data is:

S-1, FPGA11 integrates and frames the current data and position data collected by DSP controller 8;

S-2, FPGA11 adds a frame header to the integrated data.

Compared with the prior art, this specific embodiment has the following positive effects:

In this specific embodiment, the FPGA11 is used to control the read and write logic sequence of the USB control chip FT245RL2.2, which ensures that the USB interface has the characteristics of high transmission rate and stable transmission. The USB control chip FT245RL2.2 has the function of mutual conversion between eight-bit parallel data and serial data, ensuring the accuracy of data interaction between the host computer 1 and the servo system; the USB control chip FT245RL2.2 is easy to use, making the communication unit simple in structure and shortening Development cycle. The upper computer 1 of this specific embodiment performs high-speed data interaction with the servo system through the USB interface module 2, reads various state parameters of the servo system in real time, and displays the analysis results on the control interface of the upper computer 1 .

Therefore, this embodiment has the characteristics of simple structure, convenient use, stable transmission and high transmission rate.

Claims (5)

1. a communication unit based on USB servo system high-speed data interaction, characterized in that said communication unit includes: upper computer (1), USB interface module (2), keyboard and display (3), I/O interface ( 4), field bus interface (5), pulse input interface (6), analog quantity interface (7), DSP controller (8), FPGA (11), fault detection module (12), power drive module (10) and Permanent magnet synchronous motor (9); The COM end of the host computer (1) is connected with the input and output terminal 2a of the USB interface module (2); the data terminal and the control terminal 2b of the USB interface module (2) are connected with the data terminal and the control terminal 11b of the FPGA (11) , the input and output terminals 3a of the keyboard and display (3) are connected with the control terminal 11c of the FPGA (11), the input and output terminals 4a of the I/O interface (4) are connected with the control terminal 11d of the FPGA (11), and the field bus interface ( 5) the input and output terminal 5a is connected with the control terminal 11e of FPGA (11), the input and output terminal 6a of pulse input interface (6) is connected with the control terminal 11f of FPGA (11), the output terminal 12a of fault detection module (12) Be connected with the input terminal 11a of FPGA (11), the data bus of FPGA (11) and the address bus are correspondingly connected with the data bus and address bus of DSP controller (8); The input and output terminal 7a of analog interface (7) is connected with DSP The input and output port 8a of the controller (8) is connected, the PWM output end of the DSP controller (8) is connected with the PWM input end of the power drive module (10), and the two current feedback ends of the permanent magnet synchronous motor (9) are connected with the DSP The input terminals 8c and 8d of the controller (8) are correspondingly connected, and the position feedback terminal of the permanent magnet synchronous motor (9) is connected with the input terminal 8b of the DSP controller (8); the output terminal of the power drive module (10) is connected with the permanent magnet The input terminal of synchronous motor (9) is connected; The upper computer (1) is equipped with read-write USB interface software, the FPGA (11) is written with read-write logic timing control software for the USB interface, and the FPGA (11) is written with software for framing the collected data. 2. The communication unit based on USB servo system high-speed data interaction according to claim 1, characterized in that said USB interface module (2) is made up of USB interface (2.1) and USB control chip FT245RL (2.2), USB The pin USBDM and pin USBDP of the control chip FT245RL (2.2) are correspondingly connected with the pin UD- and pin UD+ of the USB interface (2.1); The COM end of the host computer (1) is connected to the input and output end 2a of the USB interface (2.1), and the data signal pins D0-D7, the write control signal input pin WR, and the read control signal input pin of the USB control chip FT245RL (2.2) Pin RD, full signal pin TXE and empty signal pin RXF are sequentially connected with data input and output ports D0-D7 of FPGA (11), write control pin WR, read control pin RD, full signal input pin TXE and empty signal The input pin RXF is connected accordingly. 3. the communication unit based on the servo system high-speed data interaction of USB according to claim 1, is characterized in that the main flow of described read-write USB interface software is: S-1, obtain the port number of the USB interface (2.1); S-2, USB interface (2.1) enable; S-3. Judging whether to read data or write data, if it is read data, go to S-4, otherwise, go to S-7; S-4, host computer (1) reads the data of USB interface (2.1), judges whether a frame of data has been read, if a frame of data has been read, enter S-5, otherwise, re-execute S-4; S-5. After the upper computer (1) receives a frame of data, it parses and caches the received data; S-6, host computer (1) judges whether all the data of USB interface (2.1) has been read, if all data has been read, enter S-8, otherwise return to S-4; S-7, upper computer (1) writes data to USB interface (2.1), judges whether write data operation is finished, if write data is finished, enter S-8, otherwise, re-execute S-7; S-8. The data reading or writing is completed; the program ends. 4. the communication unit based on USB servo system high-speed data interaction according to claim 1, characterized in that the main flow of the read-write logic sequence control software of the USB interface is: S-1, FPGA (11) judges read data or write data, if read data, enter S-2, otherwise, enter S-5; S-2, FPGA (11) judge whether RXF is low level, if it is low level, enter S-3, otherwise, enter S-8; S-3, RD set low level, execute data read operation, RD set high level; S-4. FPGA (11) judges whether the data domain is read empty, if the data domain is read empty, RXF is set high, and enters S-8, otherwise, returns to execute S-3; S-5, FPGA (11) judge whether TXE is low level, if it is low level, enter S-6, otherwise, enter S-8; S-6. Set WR to high level, execute data writing operation, and set WR to high level; S-7, FPGA (11) judge whether the data field is full, if the data field is full, TXE is set high, and enters S-8, otherwise, returns to S-6; S-8. The program ends. 5. the communication unit of the servo system high-speed data interaction based on USB according to claim 1, it is characterized in that the main process of the described framing operation software for collecting data is: S-1, FPGA (11) integrate and frame the current data and position data collected by DSP controller (8); S-2. The FPGA (11) adds a frame header to the integrated data.