CN1215378C - Process for making double lineage structure for preventing positioning error - Google Patents
Process for making double lineage structure for preventing positioning error Download PDFInfo
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- CN1215378C CN1215378C CN 02124883 CN02124883A CN1215378C CN 1215378 C CN1215378 C CN 1215378C CN 02124883 CN02124883 CN 02124883 CN 02124883 A CN02124883 A CN 02124883A CN 1215378 C CN1215378 C CN 1215378C
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- dielectric layer
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Abstract
The present invention provides a method for manufacturing a double-inlaying structure, which adopts a cryochemistry gaseous phase deposition technology which is called DiRECT, and the present invention can be used for depositing a low temperature fluorocarbon thin film on a photoresist layer which limits a double-inlaying structure. The fluorocarbon thin film is formed under the condition for the deposition of temperature of less than 100 DEG C, so the fluorocarbon thin film can not damage the photoresist layer, and the present invention can prevent the problem of the reliability of inner connection lines; the reliability of the inner connection lines is caused by positioning errors of photoresists.
Description
Technical field
The present invention relates to a kind of method for making of dual-damascene structure, particularly relate to a kind of process for making double lineage structure of avoiding positioning error (misalign).
Background technology
The dual damascene manufacture craft is a kind of method that can form the stacked on top structure of a plain conductor and a metal plug (plug) simultaneously in dielectric layer, dual-damascene structure mainly includes a upper strata groove (trench) and lower floor contact hole (via hole), be used for connecting the different elements and the lead of each interlayer in the semi-conductor chip, and utilize the core dielectric material (inter-layer dielectrics) around it isolated with other elements.Along with development of integrated circuits is accurate day by day and complicated, yield how to keep dual-damascene structure is one of important topic of semiconductor fabrication process.
Please refer to Fig. 1 to Fig. 3, Fig. 1 to Fig. 3 is the existing method synoptic diagram of making dual-damascene structure on semi-conductor chip.As shown in Figure 1, semiconductor chip 10 includes a substrate 11 and a conductive layer 12 is formed within the substrate 11.Then, deposit a protective seam 13, one first dielectric layer 14, an etch stop layer 15, one second dielectric layer 16 and one first photoresist layer 17 in regular turn on the surface of substrate 11 and conductive layer 12.And carry out one first gold-tinted manufacture craft, in the first photoresist layer 17, to form a plurality of first opening 17a.
Then as shown in Figure 2, carry out one first etching process, to remove second dielectric layer 16 that is not covered, in second layer dielectric layer 16, to form a plurality of grooves by the first photoresist layer 17.On second dielectric layer 16, apply one second photoresist layer 18 then and fill up a plurality of grooves, and and then carry out one second gold-tinted manufacture craft, in the second photoresist layer 18, form a plurality of second opening 18a.In the ideal case, the second opening 18a can drop in the groove in first dielectric layer 16 completely.Yet because manufacture craft technology limitation or other factors, produce positioning error when limiting the second opening 18a, make the second opening 18a of a part can drop on outside the groove in first dielectric layer 16 and cause.
As shown in Figure 3, remove etch stop layer 15, first dielectric layer 14 and protective seam 13 in regular turn, remove the second photoresist layer 18 then, form a dual-damascene structure along the second opening 18a.At last in the dual-damascene structure that completes, insert metal, and carry out a planarization program, to finish the making of plain conductor 19 and metal plug 19a by cmp (chemicalmechanical polishing) manufacture craft.
As previously mentioned, when in the second photoresist layer 18, making the second opening 18a, because manufacture craft factor, for example mask defect or photoresist uneven thickness, produce positioning error when limiting the second opening 18a and cause, make the second opening 18a of a part can drop on outside the groove in first dielectric layer 16.This situation can be dwindled the contact area of metal plug 19 and conductive layer 12, and then improves the resistance of metal plug 19.
Summary of the invention
The object of the present invention is to provide a kind of method for making of avoiding the dual-damascene structure of positioning error, to solve foregoing problems.
The object of the present invention is achieved like this; a kind of method of making a dual-damascene structure in the semiconductor chip surface promptly is provided; this semi-conductor chip includes a substrate; one conductive layer is located in this substrate top layer; one protective seam is covered on this substrate and this conductive layer; one dielectric layer is located on this protective seam, and a groove (trench) is formed in the top layer of this dielectric layer, and this method includes the following step:
Form a photoresist layer on this dielectric layer surface, and this photoresist layer fills up this groove;
In this photoresist layer, form one with the rough correspondence position of this groove opening, and expose the qualification opening of this dielectric layer;
Form a cover cap rock at this photoresist laminar surface, and this cover cap rock dwindles the bore of this qualification opening, and be positioned at the opening bore scope of this groove;
With this cover cap rock is shade, and this dielectric layer and this protective seam are carried out etching, up to exposing this conductive layer;
Remove this cover cap rock and this photoresist layer, and form a pair of embedding structure contact hole; And
In this pair embedding structure contact hole, insert the metal material, and form a dual-damascene structure.
The present invention also provides a kind of method of making a dual-damascene structure in the semiconductor chip surface, and this method includes the following step:
One substrate is provided, and be provided with a conductive layer in regular turn on the surface of this substrate, a protective seam and a dielectric layer;
Form one first photoresist layer in this dielectric layer surface;
Carry out one first photoetching making technology, in this first photoresist layer, form one first opening, to limit the position of a groove;
Carry out one first etching process, remove this dielectric layer of a predetermined depth,, remove this first photoresist layer subsequently in this dielectric layer, to form this groove via this first opening;
Apply one second photoresist layer in this dielectric layer surface, and fill up this groove;
Carry out one second photoetching making technology, in this second photoresist layer, form one with the rough correspondence position of opening of this groove, and expose one second opening of this dielectric layer;
Carry out a low temperature chemical vapor deposition manufacture craft, on this second photoresist layer with this second opening inwall on deposition one cover cap rock, and this cover cap rock dwindles the bore of this second opening, and is positioned at the opening bore scope of this groove;
Carry out one second etching process, via this this dielectric layer of second opening etching in regular turn and this protective seam, until this conductive layer surface;
Remove this cover cap rock and this second photoresist layer, and form a pair of embedding structure contact hole; And
In this pair embedding structure contact hole, insert a metal level, and form a dual-damascene structure.
In preferred embodiment of the present invention; the semiconductor chip includes a substrate, and a conductive layer is located in this substrate top layer, and a protective seam is covered on this substrate and this conductive layer; one dielectric layer is located on this protective seam, and a groove (trench) is formed in the top layer of this dielectric layer.At first, form a photoresist layer on this dielectric layer surface, and this photoresist layer fills up this groove.Then, in this photoresist layer, form one with the rough correspondence position of this groove opening, and expose the qualification opening of this dielectric layer.Then, form a cover cap rock, and this cover cap rock dwindles the bore of this qualification opening, and be positioned at the opening bore scope of this groove at this photoresist laminar surface.Afterwards, be shade with this cover cap rock, this dielectric layer and this protective seam are carried out etching, up to exposing this conductive layer.Subsequently, remove this cover cap rock and this photoresist layer, and form a pair of embedding structure contact hole.At last, in this pair embedding structure contact hole, insert the metal material, and form a dual-damascene structure.
Because the present invention is before forming the contact hole,, dwindling the opening bore of this opening, thereby reach the effect that positioning error takes place when avoiding limiting the contact hole earlier at deposition one low temperature CVD thin layer on this photoresist layer and on this opening inwall.
Description of drawings
Fig. 1 to Fig. 3 is the existing method synoptic diagram of making dual-damascene structure on semi-conductor chip;
Fig. 4 to Fig. 9 makes the method synoptic diagram of dual-damascene structure on semi-conductor chip for the present invention.
Embodiment
See also Fig. 4 to Fig. 9, Fig. 4 to Fig. 9 makes the method synoptic diagram of dual-damascene structure on semi-conductor chip for the present invention.As shown in Figure 4, semiconductor chip 20 includes a conductive layer substrate 22, a protective seam 24 is formed in the conductive layer substrate 22 and a dielectric layer 26 is formed on the protective seam 24.At first, apply one deck photoresist layer 28 on the surface of dielectric layer 26, and comprise exposure, the photoetching making technology of developing and cleaning supervisor via one, formation opening 28a in photoresist layer 28 is to limit the groove position in the dual-damascene structure.In preferred embodiment of the present invention, conductive layer substrate 22 is made of the copper metal, and dielectric layer 26 can be lower than 3 dielectric material (as SiLK by monox, fluorine silex glass (FSG) or specific inductive capacity
TM) constitute, protective seam 24 is to be made of silicon nitride.
As shown in Figure 5, then utilize photoresist layer 28, carry out an etching process,,, remove photoresist layer 28 subsequently in dielectric layer 26, to form groove 30 along the opening 28a etching dielectric layer 26 in the photoresist layer 28 as the etching shade.Then, as shown in Figure 6, on the surface of dielectric layer 26, apply one deck photoresist layer 32, and photoresist layer 32 is that groove 30 is filled up, carry out one subsequently and comprise exposure, the gold-tinted manufacture craft of developing and cleaning supervisor, with formation opening 32a in photoresist layer 32, and opening 32a is the position, contact hole that is used for limiting in the dual-damascene structure, and the size that the opening bore of opening 32a will be more required than manufacture craft at this moment is big a little.
And then, as shown in Figure 7, carry out a low temperature chemical vapor deposition manufacture craft,, be used for the opening bore of opening 32a is contracted to the required opening caliber size of manufacture craft to deposit a cover cap rock 34 at the inwall of photoresist layer 32 with opening 32a.In preferred embodiment of the present invention, cover cap rock 34 is one to comprise the macromolecule membrane of carbon and fluorine.
Contact hole 36 then as shown in Figure 8, utilizes cover cap rock 34, carries out an etching process, remove dielectric layer 26 and protective seam 24 in regular turn, so just can be formed in dielectric layer 26 and the protective seam 24 along opening 32a as the etching shade.Then, will overlap cap rock 34 and remove, so a dual-damascene structure is finished with photoresist layer 32.At last, as shown in Figure 9, in dual-damascene structure, insert a metal level 38, and carry out a comprehensive planarization program by a cmp manufacture craft, be positioned at dielectric layer 26 lip-deep metal levels 38 to remove fully, make that metal level 38 upper ends in the dual-damascene structure are rough to trim with dielectric layer 26 surfaces.
Wherein, aforesaid low temperature chemical vapor deposition manufacture craft is a DiRECT (DielectricResolution Enhancement Coating Technique) low temperature chemical vapor deposition method.And this low temperature chemical vapor deposition manufacture craft is to carry out in a high-density plasma etching machine, and its manufacture craft parameter comprises: the carbon fluorine of gas than (C/F) more than or equal to 0.25, to be lower than 100 ℃, pressure limit be that 1 to 100 milli-torr (mtorr), source power (source power) scope are that 500 to 2000 watts and substrate bias power (bias power) scope are 0 to 1200 watt to the manufacture craft temperature.And the available gas of this low temperature chemical vapor deposition manufacture craft comprises C
4F
8, CF
2H
2, C
3F
8, C
4F
6Or C
5F
8In addition, its employed gas include in addition carbonoxide (CO) and argon gas (argon, Ar).
Compared with prior art, the present invention utilizes a photoetching making technology to form the opening bore and is slightly larger than the opening 32a that manufacture craft needs, limit the position in the contact hole in the dual-damascene structure, and utilize a low temperature chemical vapor deposition manufacture craft, with deposit a cover cap rock 34 on the photoresist layer 32 with the inwall of opening 32a on, be contracted to the size that manufacture craft needs with opening bore with opening 32a.Promptly, finely tune the position of opening 32a by cover cap rock 34, opening 32a can fully be dropped in the groove 30 in the dielectric layer 26, in the time of therefore can avoiding limiting the contact hole positioning error takes place, and can increase the aligning enough and to spare (alignment margin) of photoetching making technology when limiting the contact hole.Moreover photoetching making technology can limit the contact hole by bigger exposure energy, produces scum silica frost (scumming) to reduce, and does not have the situation generation of positioning error.In addition, because the temperature of low temperature chemical vapor deposition manufacture craft is lower than 100 ℃, therefore can be on the photoresist layer 32 that limits back (patterned) deposit film, on semi-conductor chip, to make littler pattern (pattern), but can not destroy photoresist simultaneously.
The above only is preferred embodiment of the present invention, and all equalizations of doing by claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (17)
1. method of making a dual-damascene structure in the semiconductor chip surface; this semi-conductor chip includes a substrate; one conductive layer is located in this substrate top layer; one protective seam is covered on this substrate and this conductive layer; one dielectric layer is located on this protective seam; and one channel shaped be formed in the top layer of this dielectric layer, this method includes the following step:
Form a photoresist layer on this dielectric layer surface, and this photoresist layer fills up this groove;
In this photoresist layer, form one with the rough correspondence position of this groove opening, and expose the qualification opening of this dielectric layer;
Form a cover cap rock at this photoresist laminar surface, and this cover cap rock dwindles the bore of this qualification opening, and be positioned at the opening bore scope of this groove;
With this cover cap rock is shade, and this dielectric layer and this protective seam are carried out etching, up to exposing this conductive layer;
Remove this cover cap rock and this photoresist layer, and form a pair of embedding structure contact hole; And
In this pair embedding structure contact hole, insert the metal material, and form a dual-damascene structure.
2. the method for claim 1, the method that wherein forms this groove includes the following step:
This forms a photoresist layer in this dielectric layer surface;
Carry out a photoetching making technology, in this photoresist layer, form an opening, to limit the position of this groove;
Carry out an etching process, remove this dielectric layer of a predetermined depth, in this dielectric layer, to form this groove via this opening; And
Remove this photoresist layer.
3. the method for claim 1, wherein this protective seam is made of silicon nitride.
4. the method for claim 1, wherein this dielectric layer is made of monox.
5. the method for claim 1, wherein this dielectric layer is made of the fluorine silex glass.
6. the method for claim 1, wherein this dielectric layer is to be lower than 3 dielectric material by specific inductive capacity to be constituted.
7. the method for claim 1, this cover cap rock utilizes a low temperature chemical vapor deposition manufacture craft to form, and this low temperature chemical vapor deposition manufacture craft is carried out in a high-density plasma etching machine, and wherein the manufacture craft parameter comprises:
(1) the carbon fluorine of gas ratio is more than or equal to 0.25;
(2) the manufacture craft temperature is lower than 100 ℃;
(3) pressure limit is 1 to 100 milli-torr;
(4) the source power scope is 500 to 2000 watts; And
(5) the substrate bias power scope is 0 to 1200 watt.
8. method as claimed in claim 7, the available manufacture craft gas of this low temperature chemical vapor deposition manufacture craft comprises C
4F
8, CF
2H
2, C
3F
8, C
4F
6Or C
5F
8
9. method as claimed in claim 8, the employed manufacture craft gas of this low temperature chemical vapor deposition manufacture craft includes carbonoxide and argon gas in addition.
10. method of making a dual-damascene structure in the semiconductor chip surface, this method includes the following step:
One substrate is provided, and be provided with a conductive layer in regular turn on the surface of this substrate, a protective seam and a dielectric layer;
Form one first photoresist layer in this dielectric layer surface;
Carry out one first photoetching making technology, in this first photoresist layer, form one first opening, to limit the position of a groove;
Carry out one first etching process, remove this dielectric layer of a predetermined depth,, remove this first photoresist layer subsequently in this dielectric layer, to form this groove via this first opening;
Apply one second photoresist layer in this dielectric layer surface, and fill up this groove;
Carry out one second photoetching making technology, in this second photoresist layer, form one with the rough correspondence position of opening of this groove, and expose one second opening of this dielectric layer;
Carry out a low temperature chemical vapor deposition manufacture craft, on this second photoresist layer with this second opening inwall on deposition one cover cap rock, and this cover cap rock dwindles the bore of this second opening, and is positioned at the opening bore scope of this groove;
Carry out one second etching process, via this this dielectric layer of second opening etching in regular turn and this protective seam, until this conductive layer surface;
Remove this cover cap rock and this second photoresist layer, and form a pair of embedding structure contact hole; And
In this pair embedding structure contact hole, insert a metal level, and form a dual-damascene structure.
11. method as claimed in claim 10, wherein this protective seam is made of silicon nitride.
12. method as claimed in claim 10, wherein this dielectric layer is made of monox.
13. method as claimed in claim 10, wherein this dielectric layer is made of the fluorine silex glass.
14. method as claimed in claim 10, wherein this dielectric layer is to be lower than 3 dielectric material by specific inductive capacity to be constituted.
15. method as claimed in claim 10, this low temperature chemical vapor deposition manufacture craft are to carry out in a high-density plasma etching machine, wherein the manufacture craft parameter comprises:
(1) the carbon fluorine of gas ratio is more than or equal to 0.25;
(2) the manufacture craft temperature is lower than 100 ℃;
(3) pressure limit is 1 to 100 milli-torr;
(4) the source power scope is 500 to 2000 watts; And
(5) the substrate bias power scope is 0 to 1200 watt.
16. method as claimed in claim 15, the available manufacture craft gas of this low temperature chemical vapor deposition manufacture craft comprises C
4F
8, CF
2H
2, C
3F
8, C
4F
6Or C
5F
8
17. method as claimed in claim 16, the employed manufacture craft gas of this low temperature chemical vapor deposition manufacture craft includes carbonoxide and argon gas in addition.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02124883 CN1215378C (en) | 2002-06-21 | 2002-06-21 | Process for making double lineage structure for preventing positioning error |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02124883 CN1215378C (en) | 2002-06-21 | 2002-06-21 | Process for making double lineage structure for preventing positioning error |
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| Publication Number | Publication Date |
|---|---|
| CN1464342A CN1464342A (en) | 2003-12-31 |
| CN1215378C true CN1215378C (en) | 2005-08-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02124883 Expired - Fee Related CN1215378C (en) | 2002-06-21 | 2002-06-21 | Process for making double lineage structure for preventing positioning error |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7994046B2 (en) * | 2006-01-27 | 2011-08-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a dielectric layer with an air gap, and a structure including the dielectric layer with the air gap |
| JP2016206449A (en) * | 2015-04-23 | 2016-12-08 | 株式会社東芝 | Patten forming method |
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| CN1464342A (en) | 2003-12-31 |
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Granted publication date: 20050817 Termination date: 20190621 |