CN1203528C - Improved method and apparatus for chemical mechanical planarization (CMP) of semiconductor wafer - Google Patents

Improved method and apparatus for chemical mechanical planarization (CMP) of semiconductor wafer Download PDF

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Publication number
CN1203528C
CN1203528C CNB991020944A CN99102094A CN1203528C CN 1203528 C CN1203528 C CN 1203528C CN B991020944 A CNB991020944 A CN B991020944A CN 99102094 A CN99102094 A CN 99102094A CN 1203528 C CN1203528 C CN 1203528C
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China
Prior art keywords
wafer
chip carrier
lining form
temperature
semiconductor wafer
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Expired - Fee Related
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CNB991020944A
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Chinese (zh)
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CN1230014A (en
Inventor
M·L·维瑟
J·K·斯特芬斯
S·G·赫德格
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Siemens AG
International Business Machines Corp
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Siemens AG
International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/27—Work carriers
    • B24B37/30—Work carriers for single side lapping of plane surfaces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B49/00—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation
    • B24B49/14—Measuring or gauging equipment for controlling the feed movement of the grinding tool or work; Arrangements of indicating or measuring equipment, e.g. for indicating the start of the grinding operation taking regard of the temperature during grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]

Abstract

Areas of different temperatures are provided on a semiconductor wafer to improve uniformity in polishing rates during CMP.

Description

The method and apparatus of the chemical-mechanical planarization of semiconductor wafer
Technical field
The present invention relates to the semiconductor manufacturing, more particularly, relate to the method and apparatus that during the chemical-mechanical planarization of semiconductor wafer, semiconductor is adopted differential heating.
Background technology
In the manufacture process of integrated circuit, often need be to polishing such as the side of thin flat elements such as semiconductor material slices.Usually, can polish the surface that forms complanation so that eliminate profile or blemish to semiconductor wafer, for example, the particle such as dirt or dust of crystalline imperfection, scratch, coarse part or embedding.This glossing is commonly referred to mechanical planarization or chemical-mechanical planarization (" CMP "), and is used for improving quality of semiconductor devices and reliability.Usually, when on wafer, forming various devices and integrated circuit, carry out described CMP technology.
In general, chemical mechanical planarization process comprises that the flat semiconductor material slices that approaches by controlled downward pressure handle is pressed on the wet type burnishing surface of rotation.Solution such as aluminium oxide or silica can be as grinding mediator.Usually utilize rotary finishing head or chip carrier, wafer be pressed on the polishing platen of rotation by controlled pressure.Randomly between chip carrier and wafer, lining form is set.Usually, polishing platen is gathered the gasket material covering of the softer humidity of hydrogen carbamate such as porous.
The inhomogeneities of polishing speed can cause the undesirable scrambling of semiconductor wafer.Cause in the various factors of inhomogeneities of polishing speed in meeting, the uneven distribution of rubbing paste is arranged, lay polishing pad and exert pressure unevenly unevenly to polishing pad.
For example European patent EP 0 650 806A1 provide a kind of equipment of polishing of semiconductor wafers, and wherein a recess 22A at top board 22 contains a plurality of cells 33, and the cloth 34 that contains wafer is positioned at the back side of each cell 33, wafer 31 and described cloth 34 absorption.Each cell 33 has connected first and second pipelines, 35,38, the first pipelines 35 and has quoted and introduce liquid 36, the second pipelines 38 and quote discharge liquid and liquid is guided in first pipeline 35.In each first pipeline 35 thermostat 37 is arranged, described thermostat 37 is used for regulating according to the Temperature Distribution on the wafer temperature of the liquid 36 of each cell 33.The polishing speed of the various piece of wafer 31 is equated.
In this area the specific question that runs into is called " loading effect " in chemical mechanical planarization process.When wafer being pressed on the polishing pad softer on the polishing platen of chemical-mechanical planarization device, polishing pad may modification and enter zone between the structure to be removed, especially when the polishing speed of described structure is different from the polishing speed in the zone between the described structure.This may cause finished surface irregular or that rise and fall on wafer.In general, this phenomenon occurs on micron dimension, and the integrated circuit that forms on described wafer is had injurious effects, and is especially all the more so in the high-density applications occasion.
On being formed at on-chip transistor, when protection such as dielectric material of deposit such as boron-phosphorosilicate glass or insulating barrier, experience another example of described loading effect.The initial conformal deposition of described protective layer may produce the cusp that has directly over transistorized and the irregular surface of the recess between the transistor.As mentioned above, polishing pad may be out of shape and adapt to the irregular surface of protective layer or dielectric layer.The polished surface that obtains at last may occur with the fluctuating of micron dimension or the form of scrambling.
Described loading effect may work in order to remove the side that is present in the details on the wafer surface and other occasions of bottom surface during the chemical-mechanical planarization.In addition, may be partly on the entire wafer surface or occur loading effect fully.The periphery and the friction speed between the inside of the semiconductor wafer of rotation may form this problem.For example, the material of the big speed of inside experience that may relatively slowly move of the periphery of motion quickly of semiconductor wafer is removed.
Summary of the invention
In view of the foregoing, in the semiconductor manufacturing, need a kind of chemical mechanical planarization process that overcomes described loading effect.Therefore, the objective of the invention is to reduce or eliminate the inhomogeneities of polishing speed in the chemical mechanical planarization process.
Have been found that advantageously to utilize on wafer and form the problem that the different temperatures zone reduces or eliminate the inhomogeneous polishing speed that may run into when semiconductor wafer polished.Specifically, device described here comprises temperature-adjusting device, and the latter is used for improving the temperature with respect to the second portion of semiconductor wafer of the first of semiconductor wafer.Described temperature-adjusting device can be with the part cooling or the heating of the needs of semiconductor wafer, so that form the different temperatures zone on semiconductor wafer.Also described by on semiconductor wafer, forming the different temperatures zone and come method that semiconductor wafer is polished.
The invention provides a kind of method of uniform polish semiconductor wafer, it may further comprise the steps: wafer is fixed in the chip carrier, and described wafer has first and second portion; Between described wafer and described chip carrier, insert a lining form, described lining form has respectively first and corresponding first of second portion and the second portion with described wafer, and the thermal conduction rate of the first of described lining form is than the thermal conduction rate height of the second portion of described lining form; Heat the first of described chip carrier, make the first of described wafer be in the temperature of the second portion that is higher than described wafer; Described wafer is contacted with the polishing pad of a rotation; Temperature with regulating described chip carrier makes the surface of described wafer polished with uniform speed.
Described method can also comprise: heat the first of described chip carrier and cool off the second portion of described chip carrier simultaneously.
Wherein, the step of cooling off the second portion of described chip carrier comprises that the second portion that makes described chip carrier contacts with cooling fluid.
Wherein, the step of the first of the described chip carrier of described heating comprises the first of the described chip carrier of laser energy directive.
The first of described wafer is circular, and the second portion of described wafer is provided with around the outside of the first of described wafer.Perhaps, the second portion of described wafer is circular, and the first of described wafer is provided with around the outside of the second portion of described wafer.
The present invention also provides a kind of device of polishing of semiconductor wafers equably, and it comprises: be suitable for the chip carrier of clamping semiconductor wafer, described semiconductor wafer has first and second portion; Be inserted in a lining form between described wafer and the described chip carrier, described lining form has respectively first and corresponding first of second portion and the second portion with described wafer, and the first of described lining form is from the thermal conduction rate height of thermal conduction rate than the second portion of described lining form; Temperature regulation controller, be used for changing like this temperature of the part of chip carrier and described lining form, make first by the wafer of chip carrier clamping be in first temperature and be in second temperature that is lower than first temperature by the second portion of the wafer of chip carrier clamping; With the polishing pad of rotation, it be positioned in by the wafer position contacting of described chip carrier clamping.
Wherein said temperature regulation controller heats the first of described chip carrier.
Described temperature regulation controller comprises resistance heater.
Described temperature regulation controller cools off the second portion of described chip carrier.
The present invention also provides a kind of lining form that is used for the uniform polish semiconductor wafer, and it comprises: the first with first coefficient of heat conduction; With the second portion with second coefficient of heat conduction, described first coefficient of heat conduction is greater than described second coefficient of heat conduction.
Wherein, described at least second portion comprises the graininess filler.At least described first comprises hole.
The present invention also comprises the method according to the manufacturing integrated circuit of above-mentioned glossing.
Description of drawings
Fig. 1 shows the view according to the signal of burnishing device of the present invention.
Fig. 2 is presented at the view according to the signal at the back side of the embodiment of chip carrier useful in the chemical mechanical planarization process of the present invention.
The chip carrier of Fig. 3 displayed map 2 the cross-sectional view of signal.
Fig. 4 shows another embodiment according to burnishing device of the present invention.
Embodiment
The present invention relates to the manufacturing of integrated circuit (IC).For example, described ICs comprises the memory IC such as random access memory (RAM), dynamic random access memory (DRAM) or synchronous dram (SDRAM).Described IC can also comprise the circuit of other form, for example, and application-specific integrated circuit (ASIC), merger DRAM-logical circuit (embedded DRAM) or other logical circuit.
Usually, on wafer, form many IC concurrently.After finishing processing procedure, cut described wafer, so that described integrated circuit is divided into independent chip.With Chip Packaging, produce final products then, the latter for example is used for such as computer system, cellular telephone, personal digital assistant's (PDA) consumer products and other electronic product.
One embodiment of the present of invention described herein are included in the zone that forms different temperatures on the semiconductor wafer that stands chemical-mechanical planarization.The present invention is not only based on such discovery, promptly, the temperature of wafer will influence the speed of polishing, and based on such discovery, promptly, can realize variations in temperature in the wafer scope pari passu, this changes improving needed polishing speed to have practical value aspect the chemical-mechanical planarization uniformity.
As what see in Fig. 1, chemical mechanical polishing apparatus comprises and is used for the chip carrier 15 of holding chip 10.Motor 17 can be used to rotation vector 15.Can rotate the polishing platen 30 that carries polishing pad 35 by motor 37.Can be added to rubbing paste on the polishing pad 35 by conduit 40.Preferably wafer 10 is pressed on the polishing pad 35 with constant pressure.Employed rubbing paste composition, rotary speed and pressure size are all at those skilled in the art within sweep of the eye.
In order to realize new Ying's described here invention, utilize temperature controller that the each several part of chip carrier 15 is heated or cool off.In the time will heating, can use traditional heater of any kind, as long as the physical constraint that it can the accommodate wafer carrier and can carefully control the degree of heating to the each several part of chip carrier.Therefore, can carry out heating by the whole bag of tricks, for example, by resistance heater, induction heater or pharoid, perhaps can be down by being exposed to luminous energy (for example laser) or radio frequency, perhaps by making fluid, for example gas, the liquid after described carrier and the heating or both mixtures contacts and thermoelectricity heats.As shown in Figure 2, can on the back side 16 of carrier 15, add the endless belt 18,19 that comprises resistive heater, so that the heating of localization is provided.
As being clear that among Fig. 3, when starting heating tape 18,19, will conduct heats by chip carrier 15, so in wafer 10, experience differential heating.Therefore, for example, the part 10a of wafer 10 will be colder than the adjacent part 10b of the influence that is subjected to heating tape 19.Similarly, the part 10b of wafer 10 will be than not being subjected to any one adjacent part 10c heat that influences in the heating tape 18,19 basically.Because the influence of heating tape 18, part 10d will be maintained at than any one high temperature among part 10c and the 10e.
Obviously, the heating efficiency of element 18,19 needs not to be identical.On the contrary, can utilize heater that part 10b and 10d are heated to different temperature with different thermal outputs.Can further imagine: be not part heating, but temperature controller can be used to cool off the part of wafer the carrier of selecting 15.Can use cooling element according to the method identical,, thereby the each several part of chip 10 be cooled off so that the each several part of carrier is cooled off with above-mentioned heating element.Can adopt any traditional coolant mechanism, for example thermoelectric-cooled.But best coolant mechanism will be that the back side 16 of carrier 15 is contacted with cooling fluid, perhaps directly contact or contact in the scope of one or more conduit (not shown).In another embodiment, utilize temperature regulation controller, a part that makes wafer 10 is heated and another part is cooled off simultaneously.
On shown in Fig. 4 another among embodiment, to chip carrier 115 and can be clipped in wafer 110 and chip carrier 115 between the lining form with heat conduction gradient 120 carry out uniform heating or cooling.Suitable lining form will comprise that at least one is than higher heat conducting zone and at least one low heat conducting zone.By having the lining form of such heat conduction gradient, can obtain bigger polishing uniformity.Can give described lining form the heat conduction gradient with any several different methods.For example, when lining form is made by synthetic polymeric material, can change the polymer property (for example degree of crystallinity, density or the like) or the composition in the variant zone of lining form.Another kind method is can form different cell sizes by the different piece at lining form and obtain the heat conduction gradient.In another embodiment, can set up the heat conduction gradient in the different zones by being attached in the appointed area that many particle-filled things with high coefficient of heat conduction is attached to lining form and less this filler.
As discussed above, the inhomogeneities of polishing speed is produced by polishing tool and substrate.But the ability of the temperature of the zones of different of control wafer makes the user can regulate the polishing speed of zones of different, thereby causes the more uniform polishing speed on entire wafer.For example, those zones with lower polishing speed are heated to than higher temperature, so that raising polishing speed wherein.Usually, the edge of wafer has the polishing speed than the height of center of wafer.Therefore, will so that improve its polishing speed, make it equal the polishing speed of Waffer edge to the center heating of wafer.Another kind method is, aspect the more uniform polishing speed of formation, also is effective those zones with low polishing speed are heated and those the regional coolings with higher polishing speed are combined on entire wafer.
The temperature that adopts during the chemical-mechanical planarization depends on following some factors: the material that is comprised in the semiconductor wafer; The diameter of wafer and thickness; The character of the rubbing paste that is adopted and quantity; And the speed of rotation of chip carrier and polishing platen.But, can be heated to 30 to 80 ℃ of temperature in the scope to the part of wafer usually, perhaps be cooled to 20 to-20 ℃ of temperature in the scope.The temperature difference between the cold part of the part of wafer heat and wafer is preferably in 1 to 40 ℃ of scope.In addition, can on enough little scale, form the temperature difference, thereby so that suitably limit the polishing speed that wafer heat and cold portion boundary are controlled adjacent part closely.Like this, for the wafer of different configurations and/or composition, can realize uniform polishing speed with off-gauge method.
Though the present invention has been described with particularity to a certain degree,, after the description more than having read, many modifications and variations are possible and are conspicuous for the professional and technical personnel.For example, though the embodiments described herein is for example understood annular heating element 18,19,, can predict the configuration that adopts any geometry.Therefore, should be appreciated that can under the situation that does not break away from the spirit and scope of the present invention, use with here the diverse ways described particularly realize the present invention.

Claims (13)

1. the method for a uniform polish semiconductor wafer, it may further comprise the steps:
Wafer is fixed in the chip carrier, and described wafer has first and second portion,
Between described wafer and described chip carrier, insert a lining form, described lining form has respectively first and corresponding first of second portion and the second portion with described wafer, and the thermal conduction rate of the first of described lining form is than the thermal conduction rate height of the second portion of described lining form;
Heat the first of described chip carrier, make the first of described wafer be in the temperature of the second portion that is higher than described wafer;
Described wafer is contacted with the polishing pad of a rotation; With
Regulate the temperature of described chip carrier, make the surface of described wafer polished with uniform speed.
2. the method for claim 1 is characterized in that, described method also comprises:
Heat the first of described chip carrier and cool off the second portion of described chip carrier simultaneously.
3. the method for claim 2 is characterized in that, the step of cooling off the second portion of described chip carrier comprises that the second portion that makes described chip carrier contacts with cooling fluid.
4. the method for claim 1 is characterized in that, the step of the part of the described chip carrier of described heating comprises this part of the described chip carrier of laser energy directive.
5. the method for claim 1 is characterized in that, the first of described wafer is circular, and the second portion of described wafer is provided with around the outside of the first of described wafer.
6. the method for claim 1 is characterized in that, the second portion of described wafer is circular, and the first of described wafer is provided with around the outside of the second portion of described wafer.
7. device of polishing of semiconductor wafers equably, it comprises:
The chip carrier that is suitable for the clamping semiconductor wafer, described semiconductor wafer has first and second portion;
Be inserted in a lining form between described wafer and the described chip carrier, described lining form has respectively first and corresponding first of second portion and the second portion with described wafer, and the thermal conduction rate of the first of described lining form is than the thermal conduction rate height of the second portion of described lining form;
Temperature regulation controller, be used for changing like this temperature of the part of chip carrier and described lining form, make first by the wafer of chip carrier clamping be in first temperature and be in second temperature that is lower than first temperature by the second portion of the wafer of chip carrier clamping; With
The polishing pad of rotation, it be positioned in by the wafer position contacting of described chip carrier clamping.
8. the device of claim 7 is characterized in that, described temperature regulation controller heats the first of described chip carrier.
9. the device of claim 8 is characterized in that, described temperature regulation controller comprises resistance heater.
10. the device of claim 7 is characterized in that, described temperature regulation controller cools off the second portion of described chip carrier.
11. a lining form that is used for the uniform polish semiconductor wafer, it comprises:
First with first coefficient of heat conduction; With
Second portion with second coefficient of heat conduction,
Described first coefficient of heat conduction is greater than described second coefficient of heat conduction.
12. the lining form of claim 11 is characterized in that, described at least second portion comprises the graininess filler.
13. the lining form of claim 11 is characterized in that, described at least first comprises hole.
CNB991020944A 1998-03-06 1999-03-05 Improved method and apparatus for chemical mechanical planarization (CMP) of semiconductor wafer Expired - Fee Related CN1203528C (en)

Applications Claiming Priority (2)

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US09/036478 1998-03-06
US09/036,478 US6020262A (en) 1998-03-06 1998-03-06 Methods and apparatus for chemical mechanical planarization (CMP) of a semiconductor wafer

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CN1203528C true CN1203528C (en) 2005-05-25

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EP (1) EP0940222A3 (en)
JP (1) JPH11288906A (en)
KR (1) KR100604035B1 (en)
CN (1) CN1203528C (en)
TW (1) TW393376B (en)

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JPH11288906A (en) 1999-10-19
TW393376B (en) 2000-06-11
US6379222B2 (en) 2002-04-30
US20010046831A1 (en) 2001-11-29
US6020262A (en) 2000-02-01
EP0940222A2 (en) 1999-09-08
KR19990077604A (en) 1999-10-25
EP0940222A3 (en) 2001-08-08
CN1230014A (en) 1999-09-29
KR100604035B1 (en) 2006-07-24

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