CN1201384C - Wafer class probe card and its mfg. method - Google Patents
Wafer class probe card and its mfg. method Download PDFInfo
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- CN1201384C CN1201384C CN 02100980 CN02100980A CN1201384C CN 1201384 C CN1201384 C CN 1201384C CN 02100980 CN02100980 CN 02100980 CN 02100980 A CN02100980 A CN 02100980A CN 1201384 C CN1201384 C CN 1201384C
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- probe card
- wafer
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- probe
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Abstract
The present invention discloses a wafer level probe card and a manufacture method thereof. A testing motherboard comprises an inward recessed pit which is formed on the lower surface; a filled buffer in the pit is used for absorbing the external force of an object to be tested; a soft circuit substrate is arranged on the testing motherboard towards the object to be tested; a vertical probe is formed on a software circuit board. The vertical probe is fixed by insulating materials, the vertical probe is coated with hard conductive materials to enhance the hardness and the deformation resistance of the vertical probe, and therefore, the service life of the vertical probe is prolonged. The wafer level probe card of the present invention has the efficiency of easy manufacture and rapid testing of wafer type assemblies.
Description
Technical field
The present invention relates to the measuring technology of semiconductor subassembly, particularly a kind of wafer class probe card (WaferLevel probe card) and manufacture method thereof.
Background technology
Fast development along with semiconductor technology, electronic product is under the fast trend of compact and multi-functional speed, and the semi-conductive I/O number of IC is not only more and more, and density is also more and more higher, also make the number of pins of package assembling also increase, and the requirement of signal transmission speed is also more and more faster thereupon.Semiconductor chip individually is encapsulated within the packaging body of plastic cement or ceramic material usually.The pin structure of packaging body transfers matrix form to by peripheral arrangement mode and arranges.For the time of reduction chip testing is carried out test at a high speed with utilizing a large amount of different telecommunication functions.The utensil of chip functions test also needs to change thereupon.
Early stage encapsulation technology is utilized input and the output of the pin of peripheral arrangement mode as signal mainly based on the encapsulation technology of lead frame.And under the demand of high density input and output, the encapsulation of lead frame has not met described demand at present.At present, under described demand, encapsulation also need reduce volume, and meeting present trend, and ball arranged encapsulation (ballgrid array is also followed in the encapsulation of high density I/O; BGA encapsulation) development of technology and haveing breakthrough, therefore, the encapsulation of IC semiconductor carrying trends towards utilizing ball arranged encapsulation technology (BGA).The pin that it is characterized by I/O is spherical, is beneficial to promote the electrical transmission speed of package assembling, can meet at present and the demand of following numeral system speed.
Yet no matter be the described lead frame or the encapsulation of ball arranged encapsulation technology (BGA), being encapsulated as of the overwhelming majority is cut into individual the encapsulation more afterwards in advance.And wafer form is encapsulated as a kind of trend of semiconductor packages, and United States Patent (USP) has and discloses a kind of wafer form encapsulation, consult, USP N.5323051, denomination of invention is " Scmiconductor wafer level package ".Therefore, wafer form is encapsulated as a kind of trend of semiconductor packages.
Be encapsulated as a kind of trend of industry based on wafer form, so wafer sort, crystal round test approach and make test card and also must be developed, be beneficial to carry out the test of wafer form encapsulation.The test of previous lead frame or ball arranged encapsulation technology (BGA) encapsulation generally is cut into crystal grain after the monomer, is installed in the test bench (socket) and is tested.And each test bench can only carry out the test of a monomer, is difficult for carrying out a large amount of synchronous tests.And anti-its road of wafer form encapsulation technology and go before wafer cuts as yet, encapsulates a plurality of crystal grain and test.
Summary of the invention
The purpose of this invention is to provide a kind of wafer class probe card and manufacture method thereof, be formed at the lower surface of testing motherboard by comprising a depression, and inwardly concave; Fill cushion and be formed in the depression, absorb determinand external force; Flexible circuit base board is positioned at the test motherboard towards object plane to be measured; Vertrical probe is formed on the flexible circuit base board; The fixing described Vertrical probe of insulation material; Rigid conductive material coats Vertrical probe, strengthens its hardness and strengthens its anti deformational force, reaches the purpose that increases useful life, makes the test usefulness that the wafer form assembly is provided easily and fast.
The object of the present invention is achieved like this: a kind of wafer class probe card.It is characterized in that: it comprises the lower surface that a depression is formed at the test motherboard at least, and inwardly concaves; Fill cushion and be formed in the described depression, absorb determinand external force; Flexible circuit base board is positioned at described test motherboard towards object plane to be measured; Vertrical probe is formed on the described flexible circuit base board; The fixing described Vertrical probe of insulation material; Rigid conductive material coats this Vertrical probe, strengthens its hardness.
This cushion is a soft epoxy resin.This insulation material is an epoxy resin.This Vertrical probe is copper or copper alloy.This rigid conductive material is a metal.This flexible circuit base board includes printed circuit and conduction perforation, constitutes the signal bang path.This test motherboard includes contact terminal corresponding to the conduction perforation, is beneficial to signal is passed to this test motherboard.Adopt electroplating technology rigid conductive material to coat this Vertrical probe, carry out case hardness and handle.
The present invention also provides a kind of manufacture method of described wafer class probe card, it is characterized in that: it comprises following steps at least:
(1) form cushion in test motherboard depression, and expose portion should be tested motherboard;
(2) the software circuit substrate is placed the cushion of this test motherboard towards object plane to be measured;
(3) on the software circuit substrate, form Vertrical probe with the manufacture of semiconductor technology;
(4) on detecting probe surface, coat rigid conductive material, strengthen its hardness.
This cushion is a software epoxy resin.This Vertrical probe is the structure that comprises copper.The rigid conductive material that coats on this Vertrical probe surface comprises metal.This method is adapted to not encapsulate the direct practice that contacts of aluminium pad of wafer.
Describe in detail below in conjunction with preferred embodiment and accompanying drawing.
Description of drawings
Fig. 1 is an array type test overall architecture schematic diagram of the present invention.
Fig. 2 is the partial structurtes schematic diagram of wafer class probe card of the present invention.
Fig. 3 is the use schematic diagram of wafer class probe card of the present invention.
Fig. 4 is the main position composition diagram of wafer class probe card of the present invention.
Fig. 5 is the probe structure schematic diagram of wafer class probe card of the present invention.
Embodiment
The present invention discloses a kind of technology relevant for the wafer form encapsulation, in detail, the invention provides a kind of wafer class probe card, is beneficial to encapsulate the kenel test and uses.
Consult shown in Figure 1ly, be array type test overall architecture of the present invention.The making that provides a wafer 2 to finish integrated circuit or semiconductor element, its surface are also to form the conductive projection 4 as electric signal transmission or test usefulness.Utilize a vacuum absorption device 6 by the fixing wafer of pressure gap, be beneficial to test.Include probe (probe) 16 and test circuit on one test card, utilize conductive projection 4 on the probe 16 contact wafers to form measuring route.Described probe (probe) 16 comprises and utilizes film tip (membrane tip) to form to be beneficial to test.The load board of one tester table (load boad) 10 will be attached on the test motherboard (ProbeCard) 8, be beneficial to the test signal is passed on the tester table in addition analytical test result.
Figure 2 shows that the local essential structure of wafer class probe card of the present invention, Figure 3 shows that the use schematic diagram of wafer class probe card of the present invention, the conductive stud fast 4 of each encapsulation unit 12 on the wafer is touched at the film tip of described probe 16.Wherein, encapsulation unit 12 is the part signal on the wafer, and representative is positioned at still uncut encapsulation monomer on the wafer 2.Described each encapsulation monomer encapsulates before cutting in advance and tests.The present invention is mainly used in test phase.In addition, the application of wherein said method also comprises the practice of the direct contact of primary aluminum pad (probing pad orbonding pad) that does not encapsulate wafer.
Fig. 4 is the main position composition diagram of wafer class probe card of the present invention.It comprises test motherboard (ProbeCard) 8, is the main body that constitutes test card.Described test motherboard 8 comprises a depression and is formed at lower surface and inwardly concaves, and wherein fills cushion 14 to absorb the deformation power that probe 16 is passed back from the surface of contact measured wafer (determinand).Wherein this cushion 14 is soft epoxy resins.Insert a flexible circuit base board 20 with respect to cushion 14 towards wafer to be measured (determinand) face in test motherboard 8, and on flexible circuit base board 20, produce Vertrical probe 16 with the manufacture of semiconductor technology.Vertrical probe 16 is fixed with insulation material 22, to add embodiment, can use but be not limited to epoxy resin to constitute.In addition, on probe 16 surfaces, coat rigid conductive material 24 and strengthen its hardness, strengthening its anti deformational force, and then increase useful life.Flexible circuit base board 20 includes printed circuit 26 and conduction perforation (through hole) 28 is positioned at wherein, is beneficial to constitute the signal bang path.Described conduction perforation (through hole) 28 is beneficial to signal is passed to test motherboard 8 corresponding to the contact terminal (pogo pin) 30 on the test motherboard 8.
Figure 5 shows that the probe structure schematic diagram of wafer class probe card of the present invention.Probe 16 is to utilize copper or copper alloy to form to add embodiment, and the circuit 26 that is positioned on the flexible circuit base board 20 also utilizes copper or copper alloy to consist of preferable.By among Fig. 5 as can be known, probe 16 most advanced and sophisticated appearances coat the rigid conductive material 24 of one deck outward, with the protection probe.Wherein, can adopt electroplating technology to reach the purpose that case hardness is handled, wherein, this rigid conductive material 24 is high rigidity metals.
The wafer sort card advantage of made of the present invention is: make easily, can provide the test of wafer form assembly to use fast.
Manufacture method of the present invention comprises following steps at least:
1, form cushion in a test motherboard depression, and expose portion should be tested motherboard;
2, the software circuit substrate is placed the cushion of this test motherboard towards object plane to be measured;
3, on the software circuit substrate, form Vertrical probe with the manufacture of semiconductor technology;
4, on detecting probe surface, coat rigid conductive material, strengthen its hardness, strengthening its anti deformational force, and then increase useful life.
The present invention forms the probe step and comprises formation photoresistance pattern on the elasticity composition position of a substrate, and the expose portion substrate.Continue and form conductive material among this photoresistance pattern.Remove this photoresistance pattern again, form on the position in this substrate elasticity to form conductive projection.Coat described conductive projection with rigid conductive material again, add the anti deformational force of strengthening this projection, increase its useful life.
The present invention with preferred embodiment explanation as above and is familiar with this field skill person, and in not breaking away from spiritual scope of the present invention, institute does a little change and retouches, and all belongs within protection scope of the present invention.
Claims (14)
1, a kind of wafer class probe card is characterized in that: it comprises the lower surface that a depression is formed at the test motherboard at least, and inwardly concaves; Fill cushion in described depression, absorb determinand external force; Flexible circuit base board is positioned at described test motherboard towards object plane to be measured; Vertrical probe is formed on the described flexible circuit base board; The fixing described Vertrical probe of insulation material; Rigid conductive material coats this Vertrical probe, strengthens its hardness.
2, wafer class probe card according to claim 1 is characterized in that: this cushion is a soft epoxy resin.
3, wafer class probe card according to claim 1 is characterized in that: this insulation material is an epoxy resin.
4, wafer class probe card according to claim 1 is characterized in that: this Vertrical probe is copper.
5, wafer class probe card according to claim 1 is characterized in that: this Vertrical probe is a copper alloy.
6, wafer class probe card according to claim 1 is characterized in that: this rigid conductive material is a metal.
7, wafer class probe card according to claim 1 is characterized in that: this flexible circuit base board includes printed circuit and conduction perforation, constitutes the signal bang path.
8, wafer class probe card according to claim 1 is characterized in that: this test motherboard includes contact terminal corresponding to the conduction perforation, is beneficial to signal is passed to this test motherboard.
9, wafer class probe card according to claim 1 is characterized in that: adopt electroplating technology rigid conductive material to coat this Vertrical probe, carry out case hardness and handle.
10, the manufacture method of the described wafer class probe card of a kind of claim 1, it is characterized in that: it comprises following steps at least:
(1) form cushion in test motherboard depression, and expose portion should be tested motherboard;
(2) flexible circuit base board is placed the cushion of this test motherboard towards object plane to be measured;
(3) on flexible circuit base board, form Vertrical probe with the manufacture of semiconductor technology;
(4) on detecting probe surface, coat rigid conductive material, strengthen its hardness.
11, the manufacture method of wafer class probe card according to claim 10 is characterized in that: this cushion is a software epoxy resin.
12, the manufacture method of wafer class probe card according to claim 10 is characterized in that: this Vertrical probe is the structure that comprises copper.
13, the manufacture method of wafer class probe card according to claim 10 is characterized in that: the rigid conductive material that coats on this Vertrical probe surface comprises metal.
14, the manufacture method of wafer class probe card according to claim 10 is characterized in that: this method is adapted to not encapsulate the direct practice that contacts of aluminium pad of wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02100980 CN1201384C (en) | 2002-01-10 | 2002-01-10 | Wafer class probe card and its mfg. method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02100980 CN1201384C (en) | 2002-01-10 | 2002-01-10 | Wafer class probe card and its mfg. method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1431693A CN1431693A (en) | 2003-07-23 |
| CN1201384C true CN1201384C (en) | 2005-05-11 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02100980 Expired - Fee Related CN1201384C (en) | 2002-01-10 | 2002-01-10 | Wafer class probe card and its mfg. method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1201384C (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100416788C (en) * | 2004-03-02 | 2008-09-03 | 旺矽科技股份有限公司 | Multifunctional probe card |
| CN100343677C (en) * | 2005-03-16 | 2007-10-17 | 胜华科技股份有限公司 | Contact film probe and manufacturing method thereof |
| KR100741697B1 (en) * | 2005-10-28 | 2007-07-23 | 주식회사 파이컴 | Probe Card And Method Of Fabricating The Same |
| CN102455373B (en) * | 2010-10-19 | 2014-04-23 | 群成科技股份有限公司 | Probe card structure |
| TWI447414B (en) * | 2012-06-07 | 2014-08-01 | 矽品精密工業股份有限公司 | Test apparatus and test method |
| CN104280677B (en) * | 2014-10-30 | 2017-11-10 | 通富微电子股份有限公司 | Semiconductor test tool |
| CN109507457B (en) * | 2017-09-15 | 2020-10-16 | 中华精测科技股份有限公司 | Probe card device |
| CN114839410B (en) * | 2022-04-06 | 2024-07-09 | 强一半导体(苏州)股份有限公司 | Film probe card device |
-
2002
- 2002-01-10 CN CN 02100980 patent/CN1201384C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1431693A (en) | 2003-07-23 |
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Granted publication date: 20050511 Termination date: 20100210 |