CN2582166Y - Flip chip wafer measuring structure - Google Patents
Flip chip wafer measuring structure Download PDFInfo
- Publication number
- CN2582166Y CN2582166Y CN 02252389 CN02252389U CN2582166Y CN 2582166 Y CN2582166 Y CN 2582166Y CN 02252389 CN02252389 CN 02252389 CN 02252389 U CN02252389 U CN 02252389U CN 2582166 Y CN2582166 Y CN 2582166Y
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- chip
- substrate
- signal
- chip package
- fixing base
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- Expired - Lifetime
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Abstract
The utility model relates to a flip chip wafer measuring structure. The flip chip wafer measuring structure uses a flip chip wafer baseplate to replace a transforming plate of a traditional flip chip wafer probe card, the flip chip wafer baseplate is arranged previously without additional design and manufacture, the design and manufacture of the flip chip wafer baseplate is correspondingly matched with a chip, a traditional transforming plate needs to be designed and specially manufactured with high cost and time waste aiming at the chip needing to be measured, and thus the flip chip wafer baseplate can be used for replacing the traditional transforming plate to reduce cost and simplify the development process of a chip measuring card.
Description
Technical field
The utility model relates to a kind of chip package chip testing structure, particularly a kind of chip package chip testing structure with low cost.
Background technology
Flip chip assembly process (Flip Chip Packaging) is a kind of processing procedure that directly encapsulates at crystal column surface, and the chip on the wafer is fixedly welded on the base plate for packaging (Substrate) in the mode of chip package.For with chips welding on substrate, weld pad on the chip need form a soldering projection lower metal layer and a soldering projection (Solder Bump), then need prewelding (Pre-soldering) on the base plate for packaging, and composite packing structure is to utilize soldered ball (Solder Ball) to finish mechanicalness and electrical being connected with printed circuit board (PCB).Soldering projection is finished electrical being connected with the solder bond of prewelding, but structural aspect only is local the connection.For chip is connected with substrate comprehensively; usually can cover brilliant (Underfill) thing of filling with one and insert between chip and the substrate, and the interface between protection chip and substrate makes its influence that avoids being subjected to environment (for example moisture) with coefficient of thermal expansion differences and complete chip and the substrate of combining between balance chip and substrate.
Before crystal column surface directly carried out flip chip assembly process, the chip of wafer must be tested earlier.Test each chip one by one with chip package wafer sort card during test.Fig. 1 and Fig. 2 show two kinds of traditional chip package wafer sort cards respectively.As shown in Figure 1, this chip package wafer sort card comprises a test card printed circuit board (PCB) 102 and a keyset (Transformer) 104.This test card printed circuit board (PCB) 102 has the circuit that the test signal from keyset 104 is sent to a testing equipment (not icon).Keyset 104 is used as the signal distribution interface of test card printed circuit board (PCB) 102 and tested chip chamber.Keyset 104 1 sides have circuit and contact point, are sent to test card printed circuit board (PCB) 102 will test signal.Keyset 104 has in addition and is used for the probe 106 that contacts with tested chip output/input weld pad/projection.Keyset 104 must design and produce at various tested chips especially in order to test different chips.Fig. 2 shows another kind of traditional chip package wafer sort card.This chip package wafer sort card comprises a test card printed circuit board (PCB) 202 and a keyset 206.Keyset 206 will be tested signal by contact point 204 and be sent to test card printed circuit board (PCB) 202.Keyset 206 has and is used for the probe structure (Probe Frame) 208 that contacts with tested chip output/input weld pad/projection.
When using above-mentioned traditional chip package wafer sort card to test crystal covered chip, probe 106 or probe structure 208 can contact with chip output/input weld pad/projection.Probe 106 or probe structure 208 send test signal from chip to keyset 104 or 206, and the test signal that keyset 104 or 206 will receive again distributes to meet the requirement of test card printed circuit board (PCB).Keyset 104 or 206 then will be tested signal and be sent to the test card printed circuit board (PCB).
The used keyset of but above-mentioned chip package wafer sort card but has some shortcomings.Traditional keyset is formed by the ceramic material manufacturing, and the equipment that ceramic keyset itself and being used for is made ceramic keyset is all very expensive.In addition, each tested chip all must carry out additional designs consuming time and customized especially requirement very less and expensive keyset, therefore significantly increases the cost of chip testing.
Because the shortcoming of above-mentioned traditional chip package chip test card and flow process, therefore be necessary to develop and a kind of novel chip package chip testing structure that improves to overcome the shortcoming of traditional chip package chip test card.And the utility model just can meet such demand.
Summary of the invention
A purpose of the present utility model is for providing a kind of chip package chip testing structure that can effectively reduce the chip testing cost.
But another purpose of the present utility model is for providing a kind of facilitating chip test card development process and the chip package chip testing structure of saving the chip test card development time.
Another purpose of the present utility model is for providing a kind of chip package chip testing structure that the optimum test condition of tested chip is provided.
In order to reach above-mentioned purpose, the utility model provides a kind of chip package chip testing structure, this chip package chip testing structure comprises a substrate that is used for chip package, wherein this substrate and a tested chip mate mutually, and distribute from the test signal of this tested chip, and a fixing base and a signal communicating device, this fixing base and signal communicating device are used for fixing this substrate and send this test signal from this chip from this substrate to one testing equipment.
Description of drawings
Fig. 1 shows a kind of traditional chip package wafer sort card;
Fig. 2 shows a kind of traditional chip package wafer sort card;
Fig. 3 shows that one covers geode type array packaging structure;
Fig. 4 is presented at solder bond and covers brilliant chip and the substrate before of filling;
Fig. 5 shows that one has the chip package chip testing structure of crystal-coated packing substrate plate;
Fig. 6 shows that another kind has the chip package chip testing structure of crystal-coated packing substrate plate.
Symbol description among the figure
102 test card printed circuit board (PCB)s
104 keysets
106 probes
202 test card printed circuit board (PCB)s
204 contact points
206 keysets
208 probe structures
302 substrates
304 chips
306 projections
308 soldered balls
310 circuit trace
312 weld pads
500 chip package chip testing structures
502 fixing bases and signal communicating device
504 crystal-coated packing substrate plates
506 contact devices
508 contact devices
600 chip package chip testing structures
602 fixing bases and signal communicating device
604 crystal-coated packing substrate plates
606 contact devices
608 contact devices
Embodiment
In this mandatory declaration is that fabrication steps described below and structure do not comprise complete processing procedure and structure.The utility model can various processing procedures, software and hardware is implemented, and only mention at this and understand required processing procedure and the structure of the utility model.
Below will be described in detail, and please note that icon will be simple form and, and size all is beneficial to understand the utility model by exaggerative not according to scaling according to accompanying drawing of the present utility model.
With reference to shown in Figure 3, show that one covers geode type array packaging structure (Flip Chip Ball GridArray Package).This covers geode type array packaging structure and comprises a chip 304 and a substrate 302.Substrate 302 is as the chip microscope carrier and will be distributed to soldered ball 308 from the signal of chip 304, and the spacing of soldered ball 308 then meets the demand of printed circuit board (PCB).Chip 304 is connected with substrate 302 by projection 306 (Bump).Fig. 4 is presented at solder bond and covers brilliant preceding chip 304 and substrate 302 of filling (Underfill).Chip 304 combines with substrate 302 with the solder bond of 310 of circuit trace (CircuitTraces) by projection 306.For accurately combination, the projection 306 on the chip 304 must be aligned with each other with the circuit trace 310 of substrate 302.And projection 306 is formed on the weld pad 312, that is weld pad 312 also must be aligned with each other with circuit trace 310.Projection 306 comprises soldering projection (Solder Bump).Crystal-coated packing substrate plate have one with keyset 104 or 206 identical functions, for instance, substrate 302 also is that the signal from chip 304 is distributed to soldered ball 308 in composite packing structure, the spacing of soldered ball 308 then must meet the signal transmission of printed circuit board (PCB) and the demand of contact, therefore substrate 302 can be contacted this with soldered ball 308 and add that simultaneously suitable contact, probe or other contact device and chip package wafer sort clamping touch.And, therefore circuit trace 310 these one sides of substrate 302 can be added that suitable contact, probe or other contact device are used for contact chip 304 to test because the circuit trace 310 of substrate 302 is just aimed at coupling originally with the weld pad 312 on the chip 304.Originally just has multiple layer inner connection access node structure in the substrate 302, just as the circuit in keyset 104 or 206 being distributed to printed circuit board (PCB) from the signal of chip 304.Therefore in chip package chip testing structure, it is effective and feasible to replace traditional keyset with crystal-coated packing substrate plate.And crystal-coated packing substrate plate comprises organic material package substrate, and for example macromolecule membrane increases layer (Polymer Thin Film Build-Up) liquid crystal high polymer material (Liquid CrystalPolymer).
Traditionally when test chip 304, probe 106 or probe structure 208 aim at and contact chip 304 on projection 306.The substrate 302 that originally mainly is used as chip 304 microscope carriers then is used to replace keyset 104 or 206 now, because the circuit trace 310 of substrate 302 has just been aimed at coupling originally with the weld pad 312 on the chip 304, thus can on the circuit trace 310 of substrate 302, add the probe of similar probe 106 or probe structure 208 or other contact device with the projection on the contact chip 304 306 to test.Except probe, mechanical devices such as soldered ball or spring also can be formed on the circuit trace 310 of substrate 302 with the weld pad on the contact chip.In order to be used for packaged chip, substrate is produced in a large number, and keyset must carry out additional designs expensive and consuming time and customized especially to produce few quantity at tested chip, and it is not only feasible and very convenient favourable therefore to replace keyset with substrate.In addition, substrate is made by organic material with low cost, and traditional keyset is formed by the ceramic material manufacturing of costliness.Moreover, it is also very expensive to be used for making the equipment of ceramic keyset.
Fig. 5 shows that one has the chip package chip testing structure 500 of crystal-coated packing substrate plate 504.As shown in Figure 5, this chip package chip testing structure 500 comprises a fixing base and signal communicating device 502, contact device 506 and 508 simultaneously.Fixing base and signal communicating device 502 comprise circuit, and this circuit receives via contact device 506 and is sent to a testing equipment (not icon) from the signal of substrate 504 and with signal.Fixing base and signal communicating device 502 fixing bases 504 are to carry out chip testing.Substrate 504 comprises the multi-link structure of internal layer and receives from the signal of tested chip and will be distributed to the contact device 506 with big spacing from the signal of the contact device 508 with less spacing via contact device 508.The spacing of contact device 508 and tested chip pad spacing must be mated, and contact device 506 spacings then must be mated with the weld pad spacing of substrate 504, and the weld pad of this substrate 504 is former to be used for and a printed circuit board (PCB) or motherboard solder bond before this.Contact device 506 comprises for example spring of soldered ball or mechanical device.Contact device 508 comprises probe, pin (Pin) or spring.Fixing base and signal communicating device 502 comprise the printed circuit board (PCB) of a probe testing device.The weld pad and the signal of the tested chip of contact device 508 contacts are linked up tested chip and substrate 504.Contact device 506 signals are linked up fixing base and signal communicating device 502 and substrate 504.Fig. 6 shows that another kind has the chip package chip testing structure 600 of crystal-coated packing substrate plate 604, and this chip package chip testing structure 600 comprises a fixing base and signal communicating device 602, contact device 606 and 608 simultaneously.
The utility model provides a kind of chip package chip testing structure with crystal-coated packing substrate plate, and this chip package chip testing structure replaces traditional keyset with crystal-coated packing substrate plate.Because crystal-coated packing substrate plate is encapsulation procedure indispensability and a large amount of the manufacturing, so do not need to manufacture and design in addition, and the design of crystal-coated packing substrate plate is just mated with chip with manufacturing originally in correspondence with each other, and traditional keyset needs to carry out additional designs expensive and consuming time with customized especially at tested chip, and, replace with crystal-coated packing substrate plate therefore that traditional keyset can reduce cost and the facilitating chip test card is developed time-histories because traditional keyset be expensive ceramic material and need by expensive equipment tool manufacturing.
The detailed description of above-mentioned relevant utility model only is an example and unrestricted.Other equivalence that does not break away from spirit of the present utility model changes or modifies within the scope of the claims of the present utility model that all should be included in.
Claims (10)
1. a chip package chip testing structure is characterized in that, this chip package chip testing structure comprises:
One is used for the substrate of chip package, and wherein this substrate and a tested chip signal are linked up, and distribute from the test signal of this tested chip; And
One fixing base and signal communicating device, this fixing base and signal communicating device are used for fixing this substrate and send from this chip this test signal through distributing from this substrate to one testing equipment.
2. chip package chip testing structure as claimed in claim 1 is characterized in that this above-mentioned substrate comprises contact device, and this contact device contacts the weld pad and the signal of this chip and links up this chip and this substrate.
3. chip package chip testing structure as claimed in claim 1 is characterized in that this above-mentioned fixing base and signal communicating device comprise the printed circuit board (PCB) of a probe testing device.
4. chip package chip testing structure as claimed in claim 1 is characterized in that this above-mentioned substrate comprises the substrate that organic material is made.
5. chip package chip testing structure as claimed in claim 1 is characterized in that, above-mentioned this fixing base and signal communicating device comprise contact device, and this contact device signal is linked up this fixing base and signal communicating device and this substrate.
6. a chip package chip testing structure is characterized in that, this chip package chip testing structure comprises:
One is used for the substrate of chip package, and wherein this substrate and a tested chip signal are linked up, and distribute from the test signal of this tested chip;
One fixing base and signal communicating device, this fixing base and signal communicating device are used for fixing this substrate and send from this chip this test signal through distributing from this substrate to one testing equipment; And
First contact device, this first contact device contact the weld pad and the signal of this chip and link up this chip and this substrate.
7. chip package chip testing structure as claimed in claim 6 is characterized in that, above-mentioned this fixing base and signal communicating device comprise second contact device, and this second contact device signal is linked up this fixing base and signal communicating device and this substrate.
8. chip package chip testing structure as claimed in claim 6 is characterized in that this above-mentioned contact device comprises soldered ball.
9. chip package chip testing structure as claimed in claim 6 is characterized in that this above-mentioned substrate comprises the substrate that organic material is made.
10. a chip package chip testing structure is characterized in that, this chip package chip testing structure comprises:
One is used for the substrate of chip package, and wherein this substrate and a tested chip signal are linked up, and distribute from the test signal of this tested chip;
First contact device, this first contact device contact the weld pad and the signal of this chip and link up this chip and this substrate;
One fixing base and signal communicating device, this fixing base and signal communicating device are used for fixing this substrate and send from this chip this test signal through distributing from this substrate to one testing equipment; And
Second contact device, this second contact device signal is linked up this fixing base and signal communicating device and this substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02252389 CN2582166Y (en) | 2002-10-22 | 2002-10-22 | Flip chip wafer measuring structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02252389 CN2582166Y (en) | 2002-10-22 | 2002-10-22 | Flip chip wafer measuring structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2582166Y true CN2582166Y (en) | 2003-10-22 |
Family
ID=33721896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02252389 Expired - Lifetime CN2582166Y (en) | 2002-10-22 | 2002-10-22 | Flip chip wafer measuring structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2582166Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102012470B (en) * | 2009-09-04 | 2013-09-11 | 日月光半导体(上海)有限公司 | Electrical test adapter plate of sealing base plate and method thereof |
-
2002
- 2002-10-22 CN CN 02252389 patent/CN2582166Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102012470B (en) * | 2009-09-04 | 2013-09-11 | 日月光半导体(上海)有限公司 | Electrical test adapter plate of sealing base plate and method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20121022 Granted publication date: 20031022 |