CN1197953A - Apparatus and method for correcting DDC erron in display device - Google Patents

Abstract

A DDC error correcting circuit and method are provided, which precents DDC1 error generated when the initial state of microcomputer is low, in case that the clock signal line and data signal line are overlapped with the clock signal line and data signal line for DDC 1/2B of EEPROM according to automatic control of picture. The microcomputer finishes the initialization of its ports to start the normal operation, and then resets the EEPROM. The correction circuit is constructed in a manner that a switching element is added to the power supply of the EEPROM, and a control signal for driving the switching element is output from a specific port of the microcomputer.

Description

Apparatus and method at display device lieutenant colonel DDC erron

The present invention relates to a kind of display device, specifically, relate to its information to/circuit and the method for proofreading and correct the DDC error in the display device of DDC1 and DDC2B pattern are provided during from a computing machine transmission/reception, this circuit and method prevent bad DDC operation according to the original state of a microcomputer.

Generally speaking, display device is the output unit of a typical computing machine, and the signal that shows the conduct image that sends from a computing machine is so that a user can discern it.Below with reference to Fig. 1 the basic structure of an internal circuit of one regular display is described.With reference to figure 1, the internal circuit of this regular display comprises: a video card 10, and it is contained in the computing machine (not shown), the colour signal that is used to provide color format required (R, G, B) and horizontal/vertical synchronization signals (H_Sync/V_Sync); A microcomputer 20 is used for receiving described horizontal/vertical synchronization signals and producing the picture control signal that a monitor picture is controlled from video card 10; Vertical deflection circuit 30 and horizontal deflecting circuit 40, be used to receive described horizontal-drive signal (H_Sync) and vertical synchronizing signal (V_Sync), with the electron beam that produces by the deflection of a deflection coil executive level and vertical deflection so that by the electron gun of CRT80 continuously deflection begin to the bottom of its right side part from the top of the left part of CRT80, form an image that resembles a width of cloth picture thus; A high voltage circuit 50, the anode that utilizes a blanking pulse that produces from horizontal deflecting circuit 40 high voltage to be applied to CRT80 according to the principle and the High-Voltage Technology of on-off circuit; A video preamplifier 60 is used for that (R, G B) amplify, so that this signal maintains a specific voltage level to a low level picture intelligence being sent by low voltage amplifier from video card 10; With a video main amplifier 70, the signal that is used for being amplified to 40Vpp by video preamplifier 60 is amplified to 60Vpp, energy is applied to each pixel of display.

Have dual mode and will send to described display from the horizontal/vertical synchronization signals and the vision signal of computing machine or other data processing equipments.As shown in Fig. 2 A, one of method is that (video signal cable B) and synchronous signal line transmit by a cable picture intelligence for R, G.In this case, be sent to slightly different that signal of each lead-in wire of a connector may be with display manufacturer.As shown in Fig. 2 B, another kind of method is that (video signal cable B) and synchronous signal line transmit by cable separately described picture intelligence for R, G.Here, if carry out the operating system program that makes a computer operation, then use the D-Sub method, because of it has faint high frequency characteristics.BNC is the resolution that is used for improving at high frequency band, often uses BNC when one of execution is similar to the program of CAD.The function of utilizing described D-Sub method to change information in display and computer inter is known as DDC (DDC).The information that this means the various relevant monitors that used by the user is sent to computing machine, so that this computing machine can show the image that is suitable for this monitor most, even this user does not have information to show on this monitor.

Most computers user is to the degree of the resolution of its monitor and the very understanding of level of resolution that is suitable for software that they use.Therefore, even the user has high performance monitor, need the software (such as CAD or recreation) of high resolution pictures to be fully utilized.Because the user does not have the knowledge of resolution and does not have conversion of resolution to show the ability of described picture.Yet, if described DDC is to the monitor support, then monitor is to the information (EDID) of computing machine transmission about himself, and computing machine receives this information and automatically show best picture in the scope that this monitor is supported, and has nothing to do with the present employed software of user.This makes monitor be in to be suitable for state of user most.

The information (EDID) that sends to computing machine from monitor comprises the ID of the manufacturer that represents manufacturer, the product IDs of expression product type name, the data whether notice display power setting signaling (DPMS) function is supported, CRT performance and supporting regularly.The pattern that sends the information of relevant monitor to computing machine is divided into DDC1 and DDC 2B.With reference to figure 3A, the 12nd bar lead-in wire of DDC1 pattern by the D-Sub signal cable by bit from monitor to the computer sends the data, make these data synchronous from the vertical synchronizing signal (V_Sync) that computing machine sends with the 14th lead-in wire by the D-Sub signal cable.128 bits of EDID information are sent continuously, till this vertical synchronizing signal is transfused to.

With reference to figure 3B, DDC 2B pattern requires computing machine to send data by the 12nd lead-in wire (data) and the 15th lead-in wire (clock) of signal cable to monitor.Afterwards, monitor sends the EDID data by the 12nd lead-in wire of signal cable to computing machine.When computing machine transmits one when sending stop signal to monitor, in case judgment data by fully to its transmission, monitor will stop data and send.Most DDC monitors are supported this two kinds of patterns.For DDC1 and DDC 2B are supported, can use a microcomputer home block.Yet, as a rule, be to use the application-specific integrated circuit of DDC1/2B, as shown in Figure 4.Data-signal (SDA) and clock signal (SCL) send by the 12nd lead-in wire and the 15th lead-in wire of D-Sub cable respectively.When scl line (the 15th bar lead-in wire) when becoming low level state, carry out conversion from the DDC1 pattern to DDC 2B pattern.When in a single day pattern was switched to DDC 2B, it did not turn back to DDC1, unless monitor power is restarted.

Simultaneously, when picture data (by manufacturer self control) was stored among the EEPROM (electronics erasable programmable ROM) of an outer setting, the 12nd lead-in wire and the 15th lead-in wire by described signal cable utilized the clock cable (SCL) of microcomputer and data signal line (SDA) to store this data.Therefore, as shown in Figure 5, the data line of DDC1/2B and clock line are shared by the data line and the clock line of microcomputer.In this case, if all of the port of this microcomputer all is in a low level state when microcomputer is reclosed power supply, then the clock signal (SCL) with the EEPROM of the clock signal (SCL) of this microcomputer stack also is maintained at low level state.Like this, because the clock signal of EEPROM becomes low level state, its mode switch is to DDC 2B.Therefore, when monitor was switched on, the power supply of microcomputer restarted state and is confirmed as the ground level state, and this makes the operation of DDC1 become impossible.

Below with reference to Fig. 6 A and 6B the aforesaid operations program is explained in more detail.Fig. 6 A represents that the operating voltage of EEPROM is fixed on the power connection state, and Fig. 6 B represents that microcomputer does not finish the power connection reseting procedure and fixed operating voltage up to EEPROM.When microcomputer had been finished power connection and resetted in about time of 8 to 10ms, all of the port of this microcomputer was maintained at the about 12 μ s of low level state.Then, when the initialization of each port finished, microcomputer began normal running.Problem in this situation is that the EEPROM of beamhouse operation is according to the low state execution pattern conversion of keeping 12 μ s.In other words, the height of 12 μ s to low mode conversion has caused height to the low mode of clock cable (SCL) to be changed, thereby produces the DDC1 error.In other words, EEPROM 12 μ s mode switch at the reseting period of microcomputer initial operation that are in the DDC1 state are judged as and are transformed into DDC2B, thereby produce the DDC1 error.This be when all of the port that is in microcomputer power connection state be a kind of inevitable phenomenon that the data-signal (SDA) of low level state and this microcomputer and clock signal (SCL) are produced when being connected to each other.

Therefore, The present invention be directed to a kind of circuit and method of proofreading and correct the DDC error in display device, sort circuit and method have eliminated widely because the limitation of correlation technique and the variety of issue that defective causes.

An object of the present invention is to provide a kind of circuit and method of proofreading and correct the DDC error in display device, this circuit and method make an EEPROM force the power connection of microcomputer resets after to reset, thus correction DDC1 error.

In order to realize above-mentioned purpose of the present invention, construct a DDC1 error correction circuit in such a way, promptly, a switch block (Tr) is connected to the power end of an EEPROM, with the output signal of a microcomputer particular port is sent to this switch block so that after this microcomputer begins normal running by described this switch block of particular port switch once.

Being appreciated that above-mentioned general description and following going through are illustrative and illustrative, is for described invention provides further instruction according to claim.

Comprise and constitute this instructions part and together with the description that is used for the principle of the invention makes an explanation embodiments of the invention are described so that the accompanying drawing that the present invention is further understood to be provided.In described accompanying drawing:

Fig. 1 is the block scheme of the structure of expression common display device;

Fig. 2 is the synoptic diagram that expression connects the signal wire of a computer system and a display device;

Fig. 3 A and 3B are the synoptic diagram of DDC transfer mode between the expression computer system and display apparatus;

Fig. 4 is the synoptic diagram according to the method for attachment of an application-specific integrated circuit of DDC transfer mode;

Fig. 5 is the synoptic diagram of the structure of the data line of EEPROM of expression and microcomputer and clock line;

Fig. 6 A and 6B are the synoptic diagram of waveform of the operating voltage of expression described EEPROM and microcomputer;

Fig. 7 is the synoptic diagram of expression according to a DDC error correction circuit of the present invention;

Fig. 8 is the process flow diagram according to DDC error correction operation of the present invention.

To describe in detail to the preferred embodiments of the present invention below, example wherein is illustrated in the accompanying drawings.

Fig. 7 shows the structure of DDC error correction circuit according to an embodiment of the invention.With reference to figure 7, this DDC error correction circuit comprises a D-Sub signal cable 1, be used for from a computing machine receive colour signal (R, G, B) and synchronizing signal (H/V Sync) and utilize a specific lead-in wire execution information transmission/reception; An EEPROM 2 is used for receiving a data-signal (SDA) and a clock signal (SCL) respectively by the 12nd lead-in wire and the 15th lead-in wire of signal cable 1; A microcomputer 3, it is connected with the 15th lead-in wire with the described clock signal of transmission/reception and data-signal with to particular port transmission one control signal that EEPROM2 is resetted with the 12nd lead-in wire of signal cable 1; With a switch block (Tr), the described particular port that is used to receive by microcomputer 3 sends to the control signal of its base terminal and exports the EEPROM control signal by its collector terminal.

To the work of DDC error correction circuit of the present invention be described below.Along with applying of power supply, EEPROM2 keeps a normal working voltage 8 to 10ms.When power connection resets when finishing, microcomputer 3 makes its all of the port remain on low level state 12 μ s.Subsequently, EEPROM2 is switched to the DDC2B pattern.Reset finish after, microcomputer 3 is to control signal that is used to drive described switch block of the instantaneous output of a particular port.This control signal is sent to the base stage of switch block (Tr), this switch of momentary connection.Therefore, the power of power end that is applied to EEPROM2 is by insantaneous break, turns back to DDC1 state as original state so EEPROM2 is reset.

Fig. 8 is the process flow diagram according to DDC error correction operation of the present invention.At first, at step S1, the normal working voltage that the EEPROM maintenance is provided by power supply.At this moment, microcomputer 3 does not also finish the initial procedure of operate as normal.At step S2, microcomputer 3 finishes power connection and resets in 8 to 10ms, makes its all of the port be in the about 12 μ s of low level state then, makes their initialization.In view of the above, in step 3, EEPRM2 is switched to DDC2B from initial DDC1.At step S4, the microcomputer 3 beginning operate as normal of port initialization have been finished, by signal that is used to drive described switch of particular port output.At step S5, when making the moment conducting of this switch block according to the drive signal from microcomputer, the power that is applied to EEPROM2 is also by temporarily disconnected.Subsequently, the power that is applied to this switch block base stage is cut off.At step S6, when described switch block was cut off, power was applied to EEPROM2 once more, thereby at step S7, EEPROM2 is switched to the DDC1 pattern of original state.

Switch block is added to the power end of EEPROM2, under the control of microcomputer 3, makes its conducting/cut-out.In other words, after the normal public work of microcomputer 3 beginning, its power switch that offers EEPROM2 once so that this EEPROM resets, is kept normal DDC1 operation.When superposeing according to the data line (SDA) of the automatic control data line (SDA) of picture and clock line (SCL) and the DDC1/2B of EEPROM and clock line (SCL), EEPROM is reset after microcomputer begins operate as normal, makes EEPROM pattern (it has been converted into DDC 2B) turn back to the DDC1 state.At this moment keep operate as normal.

Those skilled in the art will be appreciated that, can make various improvement and variation to circuit and method of proofreading and correct the DDC error in display device of the present invention, and not break away from the spirit or scope of the present invention.Therefore, the present invention will cover various improvement and variation and their equivalent that hypothesis falls into this invention in the unexamined claim scope.

Claims (2)

1. a method of proofreading and correct the DDC error in computer system comprises the following steps:

According to providing of power supply a microcomputer is resetted;

All of the port initialization to this microcomputer; With

Switch is provided to the power supply of a memory device to change its DDC state.

2. DDC error correction circuit comprises:

A memory device is used to store the information of display device;

A switch block is connected to the power end of described memory device; With

A microcomputer, be used for after operate as normal begins, receiving a control signal from a computing machine, be applied to the power supply of described memory device with switch, control the switching manipulation of described switch block, described memory device is resetted to utilize a particular port.

Images