JPH1115457A - Display device and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To evade the occurrence of an error when a power source of a display device supporting a DDC(display data channel) standard is turned on. SOLUTION: This display device stores the specific information on the display device, and is provided with a storage 2 capable of transmitting the specific information to a computer main body, in at least two modes. At this time, a reset means TR forcedly resetting the storage 2 to an initial mode after a microcomputer 3 capable of controlling the storage 2 is power on reset is provided. By such a constitution, even when a high to low mode revision signal required for port initialization after the microcomputer 3 is power on reset is sent to the storage 2, and the mode of the storage 2 is revised by its mode revision signal, since the storage 2 is reset forcedly to the initial mode by the reset means TR, the occurrence of the error when the power source is turned on is evaded.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a monitor, and more particularly to a display device such as a DDC.
ata Channel, hereinafter simply referred to as DDC. )
The present invention relates to a display device having a DDC error correction circuit capable of preventing a DDC operation failure due to an initial state of a microcomputer in a display device supporting the standard and a control method thereof.

[0002]

2. Description of the Related Art A general display device is a typical output device of a computer system which displays a data signal transmitted from a computer main body as image information so that a user can recognize the data signal.

The internal circuit of a conventional display device will be briefly described with reference to FIG. As shown in the figure,
Color signals R, G, B required for image formation mounted in a computer (not shown) and horizontal / vertical synchronization signal H-SYN
C, V-SYNC, and a horizontal / vertical synchronization signal H transmitted from the video card 10.
A microcomputer 20 for generating a screen control signal for controlling a monitor screen based on -SYNC and V-SYNC, and a cathode ray tube (CRT: Cathode Ray Tu) based on the horizontal synchronizing signal H-SYNC and the vertical synchronizing signal V-SYNC.
be, hereinafter simply referred to as CRT. The electron beam generated from the electron gun 80 is changed by the deflection yoke DY to the CRT 80.
Vertical deflection circuit 30 and horizontal deflection circuit 40 for sequentially deflecting horizontally and vertically so as to form an image like a single picture, deflected in order from the upper left to the lower right, and a horizontal deflection circuit using switching and high voltage technology. A high voltage circuit 50 for supplying a high voltage to the anode terminal of the CRT 80 by a retrace pulse generated from an output terminal of the CRT 80 and a video card 1 with a low voltage amplifier
A video preamplifier 60 for amplifying the video signals R, G, and B transferred from 0 and holding the video signals R, G, and B at a constant voltage level, and further amplifies the signal amplified by the video preamplifier 60 to 40
It mainly comprises a video main amplifier 70 which amplifies the signal to 0 VPP and supplies it to each pixel as beam energy.

As a method of transferring such a horizontal / vertical synchronization signal and a video signal from a computer or other data processing device to a display device, Ds is used.
Two types, a ub pin connector system and a BNC connector system, are known.

FIG. 4A shows a D-sub 15-pin connector. For each numbered pin,
R, G, and B video signals and synchronization signals are assigned, and these signal lines are incorporated in one cable to transmit signals. Note that the signal transmitted to each pin of the D-sub 15-pin connector may vary slightly between display device manufacturers. Also, D
Since the Sub-pin connector system has a low high-frequency characteristic, it is used at a normal resolution such as a computer operation system (hereinafter referred to as OS) program.

FIG. 4B shows a BNC connector. As shown in the figure, the BNC connector has five terminals R, G, B, H, and V. R, G, B video signals and horizontal / vertical synchronization signals are assigned to each terminal, and each is separated. Is a method for performing data transfer via a cable. With such a configuration, the BNC connector can secure a high resolution in a high frequency band, and thus is mainly used when using a program requiring a high resolution such as a computer-aided design (hereinafter, referred to as CAD).

By the way, the standard for data transfer between a computer and a display device using the D-Sub pin connector system is a DDC standard, and VESA standard.
(Video Electronics Standa
rd Association). The DDC standard enables installation and setup on a computer system to be performed by a so-called plug and play system.

For example, the work of setting the resolution is very complicated, and a user who has little knowledge of the functions of the display device cannot fully utilize the monitor even if he has a high-resolution monitor. However, according to the DDC standard, a signal line and a procedure for exchanging data between the computer main body and the monitor are defined, and the performance of each monitor can be obtained by a simple operation. That is, if the monitor supports the DDC standard, an electrically erasable and writable read-only memory (Electrically Erasable a) can be used.
nd Programmable Read Only
Memory; hereinafter simply referred to as EEPROM. ) And other information necessary for plug and play.
DID (Extended Display IDen)
and the computer that has received the EDID data can display an optimal screen within the range supported by the monitor.

ED transferred from monitor to computer
The ID data includes a manufacturer ID, a manufacturing ID indicating a product model name, and a DPMS (Display Power M).
The information includes information such as presence / absence of support for an analysis signaling function, a monitor standard, and support timing.

Further, in the DDC standard, two levels of DDC1 and DDC2B are defined according to a method for transmitting information (EDID) relating to a monitor to a computer.

First, in the DDC1 system, as shown in FIG. 5, a computer sends a D-Sub pin connector # 14.
In this method, data is transmitted from the monitor to the computer one bit at a time via the signal cable # 12 pin in accordance with the vertical synchronization signal V-SYNC transmitted through the #th pin. As long as the vertical synchronization signal V-SYNC is input, it is possible to continuously transfer 128 bytes of EDID information.

On the other hand, in the DDC2B system, as shown in FIG. 6, a # 12 pin (data) and a # 15 pin (clock) of a D-Sub pin connector are transmitted from a computer.
The EDID data is transmitted from the monitor to the computer via the signal cable # 12 pin. When the computer determines that the data has been sufficiently transmitted and sends a stop signal to the monitor, the monitor stops transferring the EDID data.

Most of the data of the DDC standard supports both of these two methods. In the monitor, DDC1
In order to support / 2B, an internal block of a microcomputer may be used, but in most cases, as shown in FIG. 7, a DDC1 / 2B dedicated element is used.

The data signal SDA is transferred from the # 12 pin of the D-Sub pin connector, and the clock signal SCL is transferred from the # 15 pin to the DDC1 / 2B EEPROM. The change from the DDC1 system to the DDC2B system is performed when the clock signal SCL from the # 15th pin becomes low. Then, once the system is changed to the DDC2B system, the system does not return to the DDC1 system unless the monitor power supply is reset.

By the way, at the factory, an EEP for DDC1 / 2B
When storing the automatically adjusted image data in the ROM,
Using the clock signal SCL and data signal SDA line of the microcomputer, the # 12 pin of the D-Sub pin connector,
Data is transferred and stored via pin # 15.

For this purpose, as shown in FIG.
The data line SDA and clock line SCL for the / 2B EEPROM are superimposed on the data line DATA and clock line CLOCK of the microcomputer. In this case, when the microcomputer is power-on reset and all the ports hold the low state, the clock signal SCL of the EEPROM superimposed on the clock signal CLOCK of the microcomputer also holds the low state. Therefore, EEPRO
At M, the clock signal SCL is converted to a low state,
The mode shifts to the DC2B mode. As described above, when the power-on reset state of the microcomputer is determined to be low when the monitor is turned on, the operation of the DDC 1 becomes impossible.

The operation process will be described in more detail with reference to the waveform diagram shown in FIG. FIG. 9A shows how the operating voltage of the EEPROM is secured when the monitor is turned on, and FIG. 9B shows that the microcomputer is internally operated when the operating voltage of the EEPROM is secured (operating point). Shows a state in which the power-on reset has not been completed. When the microcomputer completes the power-on reset within a time period of about 8 to 10 ms, all the ports are kept low for about 12 μs, and then the port initialization is completed and normal operation is started.

However, the problem here is that
The point is that during about 12 μs when all ports are held low, the EEPROM which is already ready for operation will perform mode conversion. That is, about 12 μs executed after the power-on reset operation of the microcomputer is completed.
Causes a high-to-low mode conversion of the clock signal SCL line, resulting in an error of the DDC1.

In other words, the EEPRO in the DDC1 state
M determines that this mode conversion operation is mode conversion to DDC2B by temporary mode conversion for about 12 μs performed during the power-on reset operation of the microcomputer, and an error of DDC1 occurs.

This phenomenon occurs when all the ports are in the low state when the microcomputer is powered on, and the data line DATA and the clock line CLOCK of the microcomputer are superimposed on the data signal SDA and the output signal SCL of the EEPROM. Is a problem that always occurs.

[0021]

SUMMARY OF THE INVENTION The present invention relates to a conventional DD
This was devised in order to solve the above-mentioned problem of the display device supporting the C standard, and it is possible to correct the above DDC1 error by forcibly resetting the EEPROM after the power-on reset of the microcomputer. It is an object of the present invention to provide a display device having a new and improved DDC error correction circuit and a control method thereof.

[0022]

According to a first aspect of the present invention, to solve the above problems, the present invention stores the unique information of the display device and stores the unique information. A display device having a storage device capable of transmitting to a computer main body in at least two modes, comprising reset means for forcibly resetting the storage device to an initial mode after a power-on reset of a microcomputer capable of controlling the storage device. A display device is provided.

According to this configuration, the high-to-low mode change signal required for port initialization after the power-on reset of the microcomputer is sent to the storage device, and the mode of the storage device is changed by the mode change signal. Even in the case where the error occurs, the storage device is forcibly reset to the initial mode by the reset means, so that it is possible to avoid occurrence of an error when the power is turned on.

If the reset means comprises switching means which is controlled by a microcomputer and temporarily shuts off power supply to the storage device, the storage device is reset with a simple configuration. be able to.

In order to solve the above-mentioned problem, the second aspect of the present invention
According to a third aspect of the present invention, there is provided a control method of a display device including a storage device capable of storing unique information of a display device and transmitting the unique information to a computer main body in at least two modes. Power-on reset when the microcomputer that can control the storage device is powered on or reset, port initialization process to initialize all output ports of the microcomputer, and forcibly reset the storage device to the initial mode And a resetting step for controlling the display device.

According to this configuration, a high-to-low mode change signal required for port initialization after power-on reset of the microcomputer is sent to the storage device, and the mode of the storage device is changed by the mode change signal. Even in this case, since the storage device is forcibly reset to the initial mode by the reset means, it is possible to avoid occurrence of an error when the power is turned on.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a display device having a DDC error correction circuit according to the present invention and a control method thereof will be described below in detail with reference to the accompanying drawings.

FIG. 1 shows a DDC error correction circuit according to the present embodiment. The DDC error correction circuit receives the color signals R, G, B and the synchronization signal H from the computer.
/ VSYNC, and as shown, a D-Sub pin connector 1 for exchanging information using a specific pin.
And the data signal SDA is input from the # 12 pin of the D-Sub pin connector 1 and the clock signal SCL is provided from the # 15 pin.
EEPROM 2 and # 1 of D-Sub pin connector 1
The clock signal CL is connected to the 2nd pin and # 15 pin.
Microcomputer 3 for superimposing OCK and data signal DATA
And a switching element TR connected to a specific port of the microcomputer 3 at its base end and configured to output an EEPROM control signal from its collector end.

Next, the operation of the DDC error correction circuit configured as described above will be described. First, when power is applied, the DDC1 / 2B EEPROM 2 is boosted to a normal operating voltage within a predetermined time, for example, within about 8 to 10 ms. The microcomputer 3 completes the power-on reset and holds all the ports in a low state for a predetermined time, for example, for about 12 μs. Then, the microcomputer 2 performs a high-to-low operation for about 12 μs to perform the DDC1 / 2B EEPROM 2 operation.
Is converted to the DDC2B mode. However, according to the present embodiment, the microcomputer 3 momentarily outputs a drive control signal for the switching element TR to a specific port after completing the reset.

The drive control signal output to a specific port of the microcomputer 3 is input to the base end of the switching element TR, and the switching element TR is turned on instantaneously.
As a result, the power supply Vcc provided to the power supply terminal of the DDC1 / 2B EEPROM 2 is momentarily cut off, and the DDC
The 1 / 2B EEPROM 2 is forcibly reset and forcibly returned to the DDC1 mode in the initial state.

Next, the DDC error correction method according to the present embodiment will be described in detail with reference to the flowchart of FIG.

First, when the power is turned on to the monitor, DDC1 /
The 2B EEPROM 2 rises to a normal operating voltage. At this point, the microcomputer has not completed the initial operation (power-on reset operation) for normal operation (S1). Then, the microcomputer 3 performs a predetermined time, for example, about 8 to 10 ms.
After a while, the power-on reset operation is completed, all the ports are set to the low state for about 12 μs, and the ports are initialized (S
2). By the initialization operation of such a port, DDC1 / 2B
EEPROM2 changes from initial DDC1 state to DDC2B
The state is converted to a state (S3).

The operation up to this point is the same as that of the conventional display device. However, according to the present embodiment, the microcomputer 3 which has completed the port initialization and has started the normal operation outputs a drive signal for the switching element TR through a specific port. (S
4). The switching element T according to the drive signal of the microcomputer 3
R is turned on at a time, and as a result, DDC1
The power supplied to the / 2B EEPROM 2 is temporarily shut off (S5). As a result, EEP for DDC1 / 2B
The ROM 2 is forcibly reset. Thereafter, when the power supplied to the base end of the switching element TR is cut off, the switching element TR returns to the turn-off state, and the power supply to the DDC1 / 2B EEPROM 2 is restarted (S6). In this way, by restarting the power supply, the DDC1 / 2B EEPROM 2 is forcibly returned to the DDC1 mode, which is the initial state (S7).

As described above, according to the present embodiment, DD
A switching element TR is added to the power supply end of the C1 / 2B EEPROM 2, and the microcomputer 3 controls ON / OFF of the switching element TR. That is, after the microcomputer 3 starts normal operation, the DDC1 / 2B EEP
By switching the power supply Vcc of the ROM 2 once and resetting it, the DDC1 / 2B EEPROM 2 can be forcibly returned to the normal DDC 1, so that the DDC error can be corrected.

While the preferred embodiments of the DDC error correction circuit and method according to the present invention have been described with reference to the accompanying drawings, the present invention is not limited to such examples. It is clear that a person skilled in the art can conceive various changes or modifications within the scope of the technical idea described in the claims, and those modifications naturally fall within the technical scope of the present invention. It is understood to belong.

For example, in the above embodiment, # 1
Although the present invention has been described by taking as an example a display device having a D-sub pin connector for transmitting a data signal and a clock signal using the second pin and the # 15 pin, the present invention is not limited to such an example, and the present invention is not limited to this example. It goes without saying that it can be applied to any display device supporting the standard.

Further, in the above embodiment,
The present invention has been described by taking the case where the EEPROM switches between the DDC1 mode and the DDC2B mode as an example. However, the storage device for storing the unique information of the display device according to the present invention is an EEPROM.
It is needless to say that the present invention is not limited to the EPROM, and the mode is not limited to the above two modes. For example, the present invention can be applied to a case of operating in three or more modes including DDC2AB.

Further, the present invention is not limited to the display device supporting the DDC standard, but includes a storage device which stores the unique information of the display device and can transmit the unique information to the computer in at least two modes. If it is a display device, it can be applied to all display devices.

[0039]

As described above, according to the present invention, D
In a display device, such as a DC standard, having a storage device capable of storing unique information of a display device and transmitting the unique information to a computer main body in at least two modes, a clock signal line CLOCK of a microcomputer and a data signal EEPR line data
When the OM DDC1 / 2B clock signal line SCL and the data signal line SDA are superimposed, the EEPROM is forcibly reset after the normal operation of the microcomputer, thereby returning the mode of the EEPROM converted to DDC2B to DDC1 and returning to normal. The operation can be maintained, and a DDC error can be avoided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a DDC error correction circuit according to the present invention.

FIG. 2 is a flowchart showing an outline of a DDC error correction operation according to the present invention.

FIG. 3 is a block diagram illustrating a configuration of a general display device.

FIG. 4 is a cross-sectional view showing signal lines connecting a computer system and a display device.
A b-pin connector is shown, and (b) shows a BNC connector.

FIG. 5 is a configuration diagram illustrating a transmission system according to the DDC1 standard between the computer system and the display device.

FIG. 6 is a configuration diagram showing a transmission system according to the DDC2B standard between the computer system and the display device.

FIG. 7 is a configuration diagram illustrating a connection state of a dedicated element that performs a transmission scheme according to the DDC standard.

FIG. 8 is a configuration diagram showing a case where data and a clock line of an EEPROM and a microcomputer are superimposed.

FIG. 9 is a waveform diagram of an EEPROM and a microcomputer operating voltage.

[Explanation of symbols]

 Reference Signs List 1 D-sub pin connector 2 EEPROM for DDC1 / 2B 3 Microcomputer TR Switching element

Claims (3)

[Claims] 1. A display device comprising a storage device for storing unique information of a display device and capable of transmitting said unique information to a computer main body in at least two modes, wherein said microcomputer is capable of controlling said storage device. A display device, comprising: reset means for forcibly resetting the storage device to an initial mode after a power-on reset. 2. The display device according to claim 1, wherein the reset unit is a switching unit that temporarily shuts off power supply to the storage device. 3. A method for controlling a display device, comprising: a storage device for storing unique information of a display device and transmitting the unique information to a computer main body in at least two modes, wherein the storage device is controllable. A power-on reset at power-on or reset of a microcomputer, a port initialization step of initializing all output ports of the microcomputer, and a reset step of forcibly resetting the storage device to an initial mode. A control method of a display device, characterized by comprising: