CN1195797A - Method for transmitting and receiving asynchronous serial data in digital signal processor - Google Patents
Method for transmitting and receiving asynchronous serial data in digital signal processor Download PDFInfo
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- CN1195797A CN1195797A CN98104479A CN98104479A CN1195797A CN 1195797 A CN1195797 A CN 1195797A CN 98104479 A CN98104479 A CN 98104479A CN 98104479 A CN98104479 A CN 98104479A CN 1195797 A CN1195797 A CN 1195797A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
Abstract
Methods of transmitting and receiving asynchronous serial data using a serial port of a digital signal processor are provided. The method of asynchronously receiving serial data includes the steps of determining whether a start bit is received, enabling the serial port when the received start bit falls from high to low, setting the initial value of the reception timer counter to half the value in the reception pulse section register, receiving one bit of data whenever the value of the reception timer counter becomes equal to the value in the reception timer period register, the reception is repeated until a stop bit is received, and disabling the serial port when the stop bit is received. According to this method, very reliable asynchronous serial communication is possible.
Description
The present invention relates to serial data communication method, particularly use the serial port of digital signal processor (DSP) to be used for asynchronous transmission and receive the method for data.
TMS320C30 DSP (by the digital signal processor of Texas Instruments's manufacturing) is now to be widely used in the special digital processor that reaches image processing in the servo controller.General digital signal processor has serial port or parallel port so that send data and receive data from it to another processor.TMS320C30 DSP has the asynchronous serial communication port, and carries out asynchronous serial communication with another TMS320C30 DSP at a high speed by communication port.
In general, if the DSP serial port can be connected to such as personal computer (PC) or the such general-purpose system of notebook, then very easy to use.For example, the program of for example encoding on PC can download to DSP, and perhaps the data at dsp system duration of work DSP can be logged continuously by PC.If the output valve of the controller of the servo-drive system of use DSP is logged and is analyzed by PC then, then be easy to realize a kind of controller of optimization.And notebook can send operational order to dsp system, makes dsp system can make specific operation, can carry out simple emulation thus.In other words, if the DSP serial port can be connected on the general-purpose system, no matter then how and can detect external system workplace and equipment.
Yet, in the serial communication method of the serial port that uses DSP DSP can not with carry out data communication such as the general-purpose computing system of PC or notebook PC.Thereby, need a kind of special asynchronous communication method with the serial communication of realization with general-purpose computing system.Yet because asynchronous data is this fact that begins with non-real data start bit partly, asynchronous communication needs some hardware and software.In other words, the starting of Data Receiving is to use start bit to be identified, and reads follow-up position according to receiving the timer counter register shown in Figure 1B.Similarly, when sending data, also be to use the transmission timer counter register to send the position one by one.
Yet we can find by communication experiment, no matter whether carry out serial communication, the transmission among the TMS320C30 DSP/reception timer counter all synchronously carries out the continuous counter operation with the time clock of processor.So the value of transmission/reception timer counter is inconsistent at the time point that start bit is sent out or receives, this will cause the communication failure in tediously long communication period.
The method that the objective of the invention is to provide the serial port of a kind of DSP of use to be used to transmit and receive data, thus, when receiving the asynchronous data that sends by serial port, the numerical value that can receive timer counter by resetting is that predetermined value prevents the communication errors when receiving start bit, so that in the intermediate point reading of data of each data signal bits pulse burst, and during data send, be zero to regulate and send each pulse burst of transmission signal by the transmission timer counter that resets of the transmission starting point at start bit.
In order to realize above purpose, the invention provides the method for the asynchronous reception serial data of serial port of a kind of TMS320C30 DSP of passing through, this TMS320C30 DSP comprises: be used for the reception timer cycle register of storage pulse segment information, when this information representation is shown the pulse burst of being made up of a plurality of time clock when 1 bit time segment table of the serial data that sends one of how many time clock correspondence serial datas; And be used for clock pulse count to being zero and the reception timer counter of counting again of starting from scratch by the numerical value that receives numerical value that the timer cycle register determines, reset count, said method may further comprise the steps: determine whether start bit is received; Starting serial port when the start bit that receives lands from high to low; The initial value that receives timer counter when being started, serial port be set be in the received pulse segment register numerical value of half; When becoming the numerical value that equals to receive register in the timer cycle, the numerical value that receives timer counter receives the one digit number certificate, till receiving stop signal; And when receiving position of rest, forbid serial port.
In order to realize above purpose, the present invention also provides a kind of method by the serial port asynchronous transmission serial data among the TMS320C30 DSP, this TMS320C30 DSP comprises: be used for the transmission timer period register of storage pulse segment information, when this information representation is shown the pulse burst of being made up of a plurality of time clock when 1 bit time segment table of the serial data that sends one of how many time clock correspondence serial datas; And to be used for clock pulse count be zero and the transmission timer counter of counting again of starting from scratch to the numerical value of the numerical value of being determined by the transmission timer period register, reset count, and said method may further comprise the steps: by to the beginning of data division to be sent with starting is added at the end and position of rest formation asynchronous data produces the transmission data; Time point initialization transmission timer counter when sending start bit is zero; When becoming the numerical value that equals in the transmission timer period register, the numerical value of transmission timer counter sends the one digit number certificate; And repeat to send one step till sending position of rest.
Below by preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, above-mentioned purpose of the present invention and advantage will be more obvious, and these accompanying drawings are:
Figure 1A to 1B represents to use the communication port of TMS320C30 DSP to be used for the register that asynchronous data sends and receives;
Fig. 2 represents that according to the present invention receiving timer counter by resetting when receiving serial data is predetermined value, can stably receive at the center section of pulse data notion;
Fig. 3 is a process flow diagram of simply representing the asynchronous data receiving course;
Time point when Fig. 4 represents according to the present invention to reset the transmission timer counter during asynchronous data sends;
Fig. 5 is a process flow diagram of simply representing the serial data process of transmitting.
The RS232C serial data is made up of a start bit, eight data bit and a position of rest.An additional bit be can add and communication errors, for example parity check bit are used to detect.Yet the RS232C serial data is formed by 10 simply altogether usually.General serial communication controller receives data by identification starting and position of rest.Yet input just can rely on the numerical value of count pick up device to receive data simply as long as the DSP communication port is designed to data.
Here, start bit is not the information that the user needs, but designation data receives the position of starting.In asynchronous transmission, have only the beginning of using the start bit recognition data, could receive data.Start bit is in the beginning of data stream, so be not difficult to find start bit.
Figure 1A and 1B represent to use the communication port of TMS320C30 to be used for the register that asynchronous data sends and receives.Figure 1A represents the reception/transmission timer period register of storage pulse segment information, when the pulse burst that the data segment of 1 position that sends during serial sends is made up of a plurality of time clock was represented, what time clock of pulse burst information representation were corresponding to a data bit.Reception/transmission timer period register is 32 specifications, so that the 1 digit pulse section that the definition serial sends.Low 16 (position 0 to 15) expression sends 1 digit pulse sections, and high 16 (16 to 31) expression receives 1 digit pulse section.
Figure 1B illustrates the reception/transmission timer counter register of expression reception/transmission timer counter output.This reception/transmission timer counter is counted till the numerical value that is provided with in reaching reception/transmission timer period register to time clock, reset count numerical value returns zero, and stores the output numerical value of the reception/transmission timer counter that repeats the counting operation in the register again.Reception/transmission timer counter register is 32 a register, and its low 16 (0 to 15) are used for the transmission timer counter, and high 16 (16 to 31) are used to receive timer counter.
At first, use register to be used for the method for receiving asynchronous serial data explanation.Referring to Fig. 2, by being set, the initial value that receives timer counter stably receives data at the pulse center section at the serial data reception period.Time point place when start bit lands from high to low is provided with the numerical value that receives timer counter for receiving half of timer cycle register value, reads each the intermediate point of pulse burst of expression when determining its bit value with box lunch.
Referring to Fig. 3, DSP is by being installed in the serial port receiving asynchronous serial data among the DSP.Whether a common DSP recognition data is received by receiving register.So, after having received data, detect start bit at this DSP of step 300 and whether be received, so that get whether primary data is asynchronous.When serial data is landed from high to low, detect the existence of start bit or do not exist.Be received if detect start bit, then at step 310 starting serial port.Promptly when traffic spike is connected to the look-at-me line of DSP, when detecting start bit, produce an interruption.Then, notice DSP serial data waits to receive and start serial port.
After the starting serial port, receive timer counter then in step 320 initialization.No matter this is that owing to whether carry out serial communication the counter of TMS320C30 DSP is increased continuously by the clock of DSP.And Another reason will make bit value to be read at the intermediate point of the pulse burst of representing each data bit.Initialization is finished like this.At first, read the numerical value of reception/transmission timer period register and being stored in the temporary variable register that is called " sett ".Sett is moved right 16 then, because the pulse burst numerical value of every of data that receive high 16 corresponding to reception/transmission timer period register.After this, temporary variable register (sett) removed with two minutes, was moved to the left 16, and was stored in the register of expression reception timer counter output numerical value.The reason of carrying out above step is, if receive half of data bit pulse burst that timer counter numerical value is set to the every reception in time point place when start bit begins to be received, then counting operation begins with this numerical value, makes it possible to accurately read the intermediate point of the pulse burst of representing one.During this period, after step 320 has been finished the initialization of reception timer counter, at the synchronous counting of step 330 counter maintenance with the DSP time clock.Then, determine in step 340 whether the added value of counter equals to receive the numerical value of the pulse burst of 1 data bit that defines in the timer register.When detecting the counter values that has increased when with 1 digit pulse hop count value identical, this time is corresponding to half time of the pulse burst of one of expression, so be received of step 350 data.Receive timer counter zero clearing once more, and determine whether to receive position of rest in step 360.Repeating step 330,340,350 and 360 up to receiving position of rest.When having received by all eight bit data of synchronous serial port of TMS320C30 DSP and having received position of rest, interrupt forbidding serial port by the reception that produces DSP in step 370.Like this, just finished the asynchronous serial data reception.
Now, explanation is used the method for the asynchronous transmission serial data of register.In order to send in real time data, DSP has installed transmit queue storing data to be sent, and uses real-time counter to interrupt monitoring transmit queue.If detect the transmit queue non-NULL, then starting sends and interrupts to extract and to send the data in the transmit queue.If transmit queue is empty, then forbid sending and interrupt, interrupt shaking hands thereby carry out.
Because forming, real time processing system interrupts controlled transmission, so must manage formation so that send data to other parts in real time.The basic operation of formation is to leading address part write data and from tail address portion read data.When using real-time interrupt when formation sends data, send all data of interrupting in the transmit queue, and reassign current mantissa's certificate by regulating the tail address then by the data volume that sends.
Yet system increases when the speed of data is imported in formation during operation, the phenomenon that leading address is crossed the tail address may occur.Under this situation, because the destruction of formation and can not the correct execution data management, so will send the data of mistake.In order to prevent this problem, can not enlarge formation simply.In order to address this problem, the formation of pre-sizing is divided into two levels.The data that first order queue stores will be sent by system.If find data in first order formation, then data are placed into second level formation.At this moment, upgrade the tail pointer of first formation.Send time durations to overflow so prevented this formation at long hair.When first order formation becomes (" awaiting orders " state) when full, be stored in the extraction of the data in the formation by reading storer, make formation be cleared.Reduced the stand-by period like this.
And, when DSP uses the controlled serial communication controller of interruption to send data, produce a large amount of interruptions.When central stopping pregnancy is given birth to, just applied the very big burden of serving interruption to DSP.And in the processing procedure of starting and disabled interrupt, it is complicated that the operation of DSP becomes.So operation failure may take place.In order to overcome the above problems, DSP has installed direct memory visit (DMA) module therein.DMA can combine with serial port.When the transmit buffer of storer was addressed, DMA automatically was written to serial port to data slice.When serial port was finished the transmission data, DMA automatically write other data, to reduce the burden of DSP.
Fig. 4 represents the time point that the transmission timer counter is eliminated when according to the present invention data being carried out asynchronous transmission, so that make a pulse burst that is sent out be standardized into to be numerical value by the definition of transmission timer period register.
Fig. 5 represents that simply DSP passes through the process flow diagram of the processing procedure of serial port asynchronous transmission serial data.At first, for asynchronous communication, starting and position of rest add beginning and the end that is stored in the eight bit data in the formation buffer to, produce in step 500 thus and send Frame.Then, at step 510 initialization transmission timer counter.That is, the numerical value of transmission timer counter is reset to zero in the moment that sends start bit.After the initialization of transmission timer counter, keep counting synchronously with the DSP time clock at step 520 counter.Then in step 530, determine the numerical value of the 1 digit pulse the section whether added value of counter equals to define in the transmission timer period register.In step 540, when two numerical value are identical, send one.Again be reset to zero at step 550 transmission timer counter then, and determine whether to have sent position of rest.Repeating step 520,530,540 and 550 up to having sent position of rest.Thus, finished the transmission of carrying out asynchronous serial data by the synchronous serial port of TMS320C30 DSP.
Therebetween, the asynchronous serial data method of sending and receiving has added simple hardware, so it can be applicable to RS232C and two kinds of methods of RS422 corresponding to the asynchronous communication international standard.
According to aforesaid the present invention, asynchronous data sends and receives and can realize by the synchronous serial port of TMS320C30 DSP.And, even also can not break down, thereby can carry out very reliable asynchronous serial communication in long-time communication period.
Claims (5)
1. the method for the asynchronous reception serial data of serial port by TMS320C30 DSP, this TMS320C30 DSP comprises: be used for the reception timer cycle register of storage pulse segment information, when this information representation is shown the pulse burst of being made up of a plurality of time clock when 1 bit time segment table of the serial data that sends one of how many time clock correspondence serial datas; And the reception timer counter is used for to be zero and the counting again of starting from scratch to the numerical value by the definite numerical value of described reception timer cycle register, reset count, to said method comprising the steps of described clock pulse count:
Determine whether start bit is received;
When landing from high to low, starts the start bit of described reception described serial port;
The initial value that described reception timer counter is set when described serial port is started is half a numerical value in the described received pulse segment register;
When becoming the numerical value that equals register in the described reception timer cycle, the numerical value of described reception timer counter receives the one digit number certificate, till receiving stop signal; And
When receiving described position of rest, forbid described serial port.
2. the asynchronous serial data method of reseptance described in claim 1, wherein when described start bit reduces from high to low, interrupt the described serial port of starting, and when receiving described position of rest, interrupt forbidding described serial port by producing a reception by producing one.
3. method by the serial port asynchronous transmission serial data among the TMS320C30 DSP, this TMS320C30 DSP comprises: be used for the transmission timer period register of storage pulse segment information, when this information representation is shown the pulse burst of being made up of a plurality of time clock when 1 bit time segment table of the serial data that sends one of how many time clock correspondence serial datas; And the transmission timer counter, be used for the numerical value of described clock pulse count to the numerical value of being determined by described transmission timer period register, reset count is zero and starts from scratch and count again, said method comprising the steps of:
By to the beginning of data division to be sent with starting is added at the end and position of rest formation asynchronous data produces Frame;
The described transmission timer counter of time point initialization when sending described start bit is zero;
When becoming the numerical value that equals in the described transmission timer period register, the numerical value of described transmission timer counter then sends the one digit number certificate; And
The described step that repeats to send one is till sending described position of rest.
4. the asynchronous serial data sending method described in claim 3, if wherein described DSP also comprises the described transmit queue that is used for temporary transient storage data to be sent, then the data to the input of described Frame generation step at first are stored in transmit queue, and may further comprise the steps in described transmit queue data storing method:
Determine whether described transmit queue data are empty; And
When described transmit queue data are not empty, start to send and interrupt, and when described transmit queue data are sky, forbid that described transmission interruption sends so that stop data so that send data to described transmit queue.
5. the asynchronous serial data sending method described in claim 4, wherein said transmit queue comprises:
First transmit queue is used to store the data to be sent by described DSP; And
Second transmit queue, being used to store the data of described first transmit queue and producing step to described frame provides data.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970012794A KR100230451B1 (en) | 1997-04-08 | 1997-04-08 | Method of transceiving asynchronous serial data of digital signal processor |
| KR12794/97 | 1997-04-08 |
Publications (1)
| Publication Number | Publication Date |
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| CN1195797A true CN1195797A (en) | 1998-10-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN98104479A Pending CN1195797A (en) | 1997-04-08 | 1998-02-19 | Method for transmitting and receiving asynchronous serial data in digital signal processor |
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| Country | Link |
|---|---|
| US (1) | US6240151B1 (en) |
| JP (1) | JP2971849B2 (en) |
| KR (1) | KR100230451B1 (en) |
| CN (1) | CN1195797A (en) |
| RU (1) | RU2145729C1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101140551B (en) * | 2006-09-07 | 2010-06-16 | 中国科学院长春光学精密机械与物理研究所 | Device for realizing digital signal processor asynchronous serial communication |
| CN105871383A (en) * | 2016-03-29 | 2016-08-17 | 上海斐讯数据通信技术有限公司 | Data cut-off bit extraction circuit, series-parallel conversion circuit and serial lighting circuit |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW484101B (en) * | 1998-12-17 | 2002-04-21 | Hitachi Ltd | Semiconductor device and its manufacturing method |
| KR100533864B1 (en) * | 1999-03-09 | 2005-12-07 | 가부시키가이샤 산요붓산 | A control apparatus for a ball-projection type game machine |
| US6393502B1 (en) * | 1999-08-31 | 2002-05-21 | Advanced Micro Devices, Inc. | System and method for initiating a serial data transfer between two clock domains |
| JP4364041B2 (en) * | 2004-04-01 | 2009-11-11 | Ｏｋｉセミコンダクタ株式会社 | Data transfer circuit |
| US7929714B2 (en) * | 2004-08-11 | 2011-04-19 | Qualcomm Incorporated | Integrated audio codec with silicon audio transducer |
| CN100338845C (en) * | 2004-12-24 | 2007-09-19 | 上海协同科技股份有限公司 | Input / output module of inner communication through serial synchronous communication bus |
| KR100688516B1 (en) * | 2005-01-11 | 2007-03-02 | 삼성전자주식회사 | Method for serial data communication using a single line and apparatus therefor |
| US8077625B1 (en) * | 2005-06-30 | 2011-12-13 | National Semiconductor Corporation | Apparatus and method for using a communication resource for performing a timing operation |
| US8761324B1 (en) * | 2009-07-10 | 2014-06-24 | Marvell Israel (M.I.S.L) Ltd. | Method and apparatus for phase signaling |
| GB2537856A (en) * | 2015-04-28 | 2016-11-02 | Nordic Semiconductor Asa | Communication between intergrated circuits |
| CN105005511A (en) * | 2015-06-30 | 2015-10-28 | 宁波东海仪表水道有限公司 | Serial communication data checking method |
| KR101921119B1 (en) | 2016-07-19 | 2018-12-06 | 주식회사 지엠케이 | Asynchronous digital communication module |
| CN113094305B (en) * | 2021-04-02 | 2024-03-26 | 北京黑蚁兄弟科技有限公司 | Asynchronous communication processing method, device and storage medium |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6220451A (en) | 1985-07-19 | 1987-01-29 | Nec Corp | Code converter |
| JPS6281840A (en) | 1985-10-04 | 1987-04-15 | Tsubakimoto Chain Co | Synchronizing circuit |
| JPS63238745A (en) | 1987-03-26 | 1988-10-04 | Matsushita Electric Works Ltd | Data transmission equipment |
| EP0389696A1 (en) | 1989-03-29 | 1990-10-03 | International Business Machines Corporation | Serial data receiver |
| JPH0385043A (en) | 1989-08-29 | 1991-04-10 | Fujitsu Kiden Ltd | Data transfer equipment |
| JP3466738B2 (en) * | 1994-11-21 | 2003-11-17 | ヤマハ株式会社 | Asynchronous serial data receiver |
-
1997
- 1997-04-08 KR KR1019970012794A patent/KR100230451B1/en not_active IP Right Cessation
-
1998
- 1998-02-19 CN CN98104479A patent/CN1195797A/en active Pending
- 1998-02-19 RU RU98103524A patent/RU2145729C1/en active
- 1998-04-07 JP JP10095018A patent/JP2971849B2/en not_active Expired - Fee Related
- 1998-04-08 US US09/056,763 patent/US6240151B1/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101140551B (en) * | 2006-09-07 | 2010-06-16 | 中国科学院长春光学精密机械与物理研究所 | Device for realizing digital signal processor asynchronous serial communication |
| CN105871383A (en) * | 2016-03-29 | 2016-08-17 | 上海斐讯数据通信技术有限公司 | Data cut-off bit extraction circuit, series-parallel conversion circuit and serial lighting circuit |
| CN105871383B (en) * | 2016-03-29 | 2020-02-11 | 上海斐讯数据通信技术有限公司 | Data cut-off bit extraction circuit, serial-parallel conversion circuit, and serial lighting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| US6240151B1 (en) | 2001-05-29 |
| JP2971849B2 (en) | 1999-11-08 |
| RU2145729C1 (en) | 2000-02-20 |
| KR100230451B1 (en) | 1999-11-15 |
| KR19980076203A (en) | 1998-11-16 |
| JPH10303993A (en) | 1998-11-13 |
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