JPS63238745A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To reproduce the amplitude and timing of a transmission signal and to cause the delay to be smaller by resetting a reception processing part and an output processing part with a resetting signal obtained by counting while a starting signal is received. CONSTITUTION:When an input transmission signal Di is received, a counter 2 starts the counting with the rise of a starting signal ST, a counting signal CN is coded by a decoder 3, sends a sample timing signal SP to an output processing part and generates a resetting signal RS. At an output processing part 4, the signal SP is received, the signal Di is sampled by the rise and a reproducing output Do is obtained. A reception processing part 1 to receive the signal RS turns off the signal ST, and the counter 2, since the signal ST falls, resets the counting signal. The decoder 3 stops the output of the signal RS by the resetting of the signal CN from the counter 2. By a series of actions, the transmission of one frame is completed, and the delay of the output Do to the signal Di comes to be a half bit only.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a data transmission device used in an asynchronous data transmission system.

[Background Art 1] Conventionally, asynchronous data transmission systems have had the following problems. In other words, the transmission signal may be lost in the optical fiber or electric wire, resulting in its amplitude becoming small, or waveform distortion may occur due to the characteristics of the transmitting system and receiving system, resulting in a timing shift. In particular, when data is transmitted over multiple stages, the distortion accumulates, resulting in a loss of bit width and the problem that accurate data cannot be transmitted.

Traditionally, dog-like methods have been used to solve these problems.

In other words, in these methods, the amplitude of the transmitted signal is as shown in Figure 3(a).
If the amplitude becomes smaller as shown in Figure 4 (a), you can use a repeater to regenerate the amplitude and return it to its original level as shown in Figure 4 (a).
), the 810 circuit once received the transmission signal for 17 frames as shown in (b) of the same figure, regenerated the timing, and transmitted it as shown in (c) of the same figure. .

However, in the former method, if there is distortion H in the transmission signal, this distortion H remains and the timing cannot be reproduced.

Furthermore, the latter method has a problem in that the transmission timing of the transmitted signal to be reproduced and transmitted is delayed by 17 frames.

[Object of the Invention] The present invention has been made in view of the above-mentioned problem, and its purpose is to provide a data transmission device in which the amplitude and timing of a transmission signal can be easily reproduced and the delay can be minimized. be.

[Disclosure of the Invention] The present invention includes: a reception processing unit that detects a start bit of an input transmission signal and outputs a start signal; a counter that receives the start signal and counts a reference clock while receiving the start signal; Note: A decoder that generates a sampling timing signal by counting No. 13 of the counter, decodes the count value of the counter to detect the end of the input transmission signal, and generates a reset signal upon this detection, and a decoder that generates a reset signal at the rising edge of the sampling timing signal. The input transmission signal is sampled synchronously and the value at that time is reproduced and outputted as the output transmission signal. It is characterized by stopping the output of.

The present invention will be explained below with reference to Examples.

1. Figure 1 shows a circuit block of the embodiment, in which the reception processing section 1 detects the start bit of the input transmission signal Di, outputs the start signal ST, and resets the circuit with the reset signal R8 from the decoder 3. The output of the start bit ST is stopped.

The counter 2 is configured to count the clock from the reference clock oscillator 5 only while receiving the start signal ST after receiving the start signal ST from the reception processing section 1.

The decoder 3 generates a sampling timing signal SP based on the count signal CN from the counter 2, detects the end of data by decoding the count value of the counter 2, and outputs a reset signal R6.

The output processing unit 4 samples the input transmission signal Di in synchronization with the rising edge of the sampling timing signal SP, and outputs the value at that time as the output transmission signal.

The reset signal R8 from the decoder 3 is reproduced and output as
When received, there will be no signal.

The specific operation of the circuit shown in FIG. 1 will be explained below using the timing chart shown in FIG.

First, in the embodiment, 17 frames of the transmission signal are set to start bit Sb, data 9 bit Db, stop bit) S.
tb has an 11-bit configuration, and the reference clock has a width of 1 bit/16.

Now, suppose that the asynchronous signal without time distortion is distorted by the transmission system and is input to the reception processing unit 1 as the input transmission signal Di shown in t52 (a). Detects the start bit Sb (start bit Sb) and sends the start signal ST shown in FIG. The clock is counted and the count signal CN shown in FIG.
Every time the clock is counted, a sample timing signal SP shown in FIG.
ooo'', it is decoded to create a reset signal R3 as shown in FIG. 2(e), and the reception processing unit 1
and sends it to the output processing section 4.

The output processing unit 4 receives the sample timing signal SP from the decoder 3, and at the rising edge of the sample timing signal SP, outputs the input transmission signal Di.
Sample and playback. FIG. 2(f) 6 shows the output transmission signal Do reproduced from 1 and becomes a no-signal state when receiving the reset signal R8.

Upon receiving the reset signal R3 output from the decoder 3, the reception processing section 1 turns off the start signal ST, and the counter 2 resets the count output when the start signal ST falls. Also, in decoder 3, counter 2
By resetting the count signal CN from , the output of the reset signal R8 is stopped.

Through this series of operations, the transmission of 17 frames is completed, and the output transmission No. 16 Do for the input transmission signal Di is completed.
The delay is from the start of counting to the sample timing signal SP.
It takes only half a bit until it starts up.

[Effect of the Invention 1] The present invention includes a reception processing unit that detects a start bit of an input transmission signal and outputs a start signal, a counter that receives the start signal and counts a reference clock while receiving the start signal, and a counter that receives the start signal and counts a reference clock while receiving the start signal. A decoder that generates a sampling timing signal based on the count signal of a counter, decodes the count value of the counter to detect the end of the input transmission signal, and generates a reset signal based on this detection, and a decoder that generates a reset signal according to the rising edge of the sampling timing signal. and an output processing section that regenerates and outputs the value at that time as an output transmission signal by sampling the manually transmitted signal, and resets the reception processing section and the output processing section by the above reset signal to output the start signal and output the output transmission signal. Since the output is stopped, even if the amplitude of the transmission signal goes up the transmission line and decreases and becomes smaller, the amplitude can be restored to its original thickness, and even if the transmission signal is distorted, the end of the 7th frame of the transmission signal can be restored. is detected by the count value of the counter,
Even if there is waveform distortion in the input transmission signal, accurate timing can be reproduced, and the delay in the output transmission signal is also small.

[Brief explanation of the drawing]

Figure Pt51 is a circuit block diagram of the embodiment of the present invention, Figure 2 is a timing chart for explaining the same operation as above, and Figures 3 and 4 are explanatory diagrams of the conventional example, respectively. DESCRIPTION OF SYMBOLS 1... Reception processing section, 2... Counter, 3... Decoder, 4... Output processing section, 5... Reference clock oscillation section, Di... Input transmission signal, Do... Output Transmission signal, ST...start signal, R5...reset signal,
CN... Counting starts. Agent Patent Attorney Ishi 1) Ai Figure 7 Figure 3 (a) (b) Figure 4 Procedural Amendment (Voluntary)

Claims (1)

[Claims] (1) A reception processing unit that detects a start bit of an input transmission signal and outputs a start signal, a counter that receives the start signal and counts a reference clock while receiving the start signal, and a count signal of the counter a decoder that generates a sampling timing signal by decoding the count value of the counter to detect the end of the input transmission signal and generates a reset signal upon this detection; and an output processing section that samples and reproduces and outputs the value at that time as an output transmission signal, and the reception processing section and the output processing section are reset by the reset signal to stop outputting the start signal and outputting the output transmission signal. A data transmission device characterized by: