JPS5455105A - Re-synchronizing circuit for start-stop synchronizing signal - Google Patents
Re-synchronizing circuit for start-stop synchronizing signalInfo
- Publication number
- JPS5455105A JPS5455105A JP12143877A JP12143877A JPS5455105A JP S5455105 A JPS5455105 A JP S5455105A JP 12143877 A JP12143877 A JP 12143877A JP 12143877 A JP12143877 A JP 12143877A JP S5455105 A JPS5455105 A JP S5455105A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- signals
- synchronizing
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/22—Arrangements affording multiple use of the transmission path using time-division multiplexing
- H04L5/24—Arrangements affording multiple use of the transmission path using time-division multiplexing with start-stop synchronous converters
Abstract
PURPOSE:To reduce transmission errors due to code distortion to a low rate with causing the delay of a signal by re-synchronizing bits of one character at every time when a repeater station receives a start bit. CONSTITUTION:Since detection circuit 321 turns OFF initialization signal INL by detecging a start bit, reception-bit counting circuit 322 starts counting up clock signals CLK and outputs set signals ST at an interval for one bit, and holding circuit 323 latches reception signal RD at every time of receiving signals ..ST and outputs it as re-synchronizing signal RD' to transmitter circuit 33. At the same time, counting circuit 322 counts up signals ST and outputs reset signal RST, after outputting signals ST for one character, to reset detection circuit 321, so that the counting circuit will also return to an intial state by signal INL. In this way, bits are made to synchronize again.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12143877A JPS5455105A (en) | 1977-10-12 | 1977-10-12 | Re-synchronizing circuit for start-stop synchronizing signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12143877A JPS5455105A (en) | 1977-10-12 | 1977-10-12 | Re-synchronizing circuit for start-stop synchronizing signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5455105A true JPS5455105A (en) | 1979-05-02 |
Family
ID=14811130
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12143877A Pending JPS5455105A (en) | 1977-10-12 | 1977-10-12 | Re-synchronizing circuit for start-stop synchronizing signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5455105A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63238745A (en) * | 1987-03-26 | 1988-10-04 | Matsushita Electric Works Ltd | Data transmission equipment |
-
1977
- 1977-10-12 JP JP12143877A patent/JPS5455105A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63238745A (en) * | 1987-03-26 | 1988-10-04 | Matsushita Electric Works Ltd | Data transmission equipment |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
ES391039A1 (en) | Receiver timing and synchronization system | |
JPS55110448A (en) | Digital signal transmission system | |
FR2313827A1 (en) | Binary elements train transmission system - has simple means of synchronising receiver timer, this timer having multiphase circuit | |
JPS5455105A (en) | Re-synchronizing circuit for start-stop synchronizing signal | |
JPS5435666A (en) | Timing extraction system | |
EP0108702A3 (en) | Serial to parallel data conversion circuit | |
EP0148098A3 (en) | Process and circuit for regenerating significant moments of a periodic signal | |
JPS543412A (en) | Signal detection circuit | |
SE7711007L (en) | DEVICE FOR AUTOMATIC RE-SYNCHRONIZATION OF DATA RECEIVERS | |
JPS5318904A (en) | Code receiving system | |
JPS5399710A (en) | Signal transmission circuit | |
JPS5247608A (en) | Transmission method of dc data | |
JPS5242302A (en) | Inter-call system | |
JPS5528620A (en) | Synchronizing system of communication line | |
JPS5738040A (en) | Signal transmitter | |
SU1172047A1 (en) | Device for transmission and reception of digital signals | |
JPS5739639A (en) | Delay type phase correction system | |
JPS5266304A (en) | Cyclic transmitter | |
JPS5725748A (en) | Start-stop synchronizing system | |
JPS5491004A (en) | Data transmission circuit | |
JPS5563153A (en) | Error detection system for digital communication equipment | |
JPS53139968A (en) | A-d convertor | |
JPS522207A (en) | Receiving circuit | |
JPS5437459A (en) | Receiver circuit | |
JPS5792413A (en) | Demodulation system for phase-modulated signal |