CN1188948C - 用于配置可编程逻辑单元阵列的方法及装置 - Google Patents
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Abstract
一种用于配置包括有那些与FPGA装置相关的可编程逻辑单元的阵列的技术,通过一新颖的基于DRAM的配置控制结构,不仅能实现“飞击式”的可改变芯片和类似装置的重配置,而且在希望时还可是自己修改用于区分该装置的功能性的重配置,以消除当前严重的可重配置性的限制和相关问题,同时能以低成本显著增强系统运行性能。在FPGA内部大量的存储器可供利用和以很小数量的引线进行访问从而使得重配置时间能以明显降低的成本较之传统方法快,例如4个数量级。
Description
技术领域
本发明是关于可重新配置逻辑单元阵列的方法及装置,尤其是但并不仅是关于场可编程门阵列(FPGA)和类似的体系结构。
背景技术
可重配置门阵列,也称之为场可编程门阵列(FPGA)在工业上被广泛用于实现各种数字电路。应用范围包括计算机,工作站,控制系统等。一典型的传统FPGA装置包含有多个被配置来满足特定设计要求的逻辑单元。一未经编程的FPGA含有如后面所述的预定的逻辑单元结构。每一个所述单元均被配置来执行一特定任务(一逻辑电路)以实现所希望的功能性,编程信息通常由配置存储元件以一相对缓慢的过程被串行装载进FPGA(一些装置被通过8位宽的总线装载,仍然为一非常缓慢的过程),其中,只要对装置加电,编程信息就被固有地保持,该配置存储元件一般由分布式静态RAM(SRAM)来实现。在内部该装置也可在电源接通时遵循一包括前述的重配置数据的缓慢串行装载的预定编程序列来加以重配置。作为示例,Xilinx公司的装置XC4025,一传统的FPGA,要求422128位的编程信息和约需42ms来完成编程(即重新配置)此装置。在装置的尺寸增加时,这一延时增大。
对于某些应用,其中,FPGA仅在加电时被编程一次,从而就不存在重新配置的问题,这种相当大的配置时间通常是可允许的。但是它无法满足一些如果重新配置时间被大大降低时能明显改善运行性能的其他应用的需要。这一问题在所有类型的应用中是普遍存在的,包括实时模拟,协同处理器,数字信号处理和各种其他算法,等等。
本发明的目的是消除当前的重配置限制和有关的问题和在降低成本下能显著增强系统运行性能,使得能由提供即时(on-the-fly)可变芯片或其他逻辑层次结构来实现对许多应用的基本上的通用。
大量这样的系统设计,特别是在高速计算机和工作站中,由于功能单元的固定结构严重地阻碍它们的特定范畴之外的任何操作的运行性能,对一定类别的应用例如模拟,运行性能受到限制。这些问题可用最好的“即时”可重新配置性来解决,但由于重新配置所需时间它仍未得到解决。
这样,对某些被广泛应用的需要能作动态再配置逻辑的低成本高性能机器的可能性基本上仍不明朗,即,直至本发明的出现才提供一种新颖的自我修正即时可重配置的FPGA体系结构,消除这些问题从而以显著降低的成本大大增强运行性能。
虽然下面为更好地理解这些问题和本发明克服它们的方式,给出说明性模拟和协作处理器应用作为示例,本发明丝毫没有意图认为被仅限于这些举例范围。
模拟应用举例
大的数字集成电路设计在其昂贵和费时的制造周期之前被加以模拟以使在制造之后的校正功能的机会最大化。该设计针对所有可能的输入条件通过提供激励和观察响应而在高性能技术工作站上被广泛地检验。如果此应答不符合预期结果,即对设计检验以纠正。继续这一重复过程直至所有可能的情况均得到验证。模拟是极费时、昂贵的,并增加进入市场的时间,但这一问题是设计方法的关键部分而现今利用将大的模拟任务在多个工程师中加以分割然后编辑结果来管理,这是一非常易於出错的过程,虽然它确实以实质上较高的成本提高了任务的速度。新近利用Intel Pentium微处理器浮点单元的失败即是恰当的例证。
作为一例,考虑被设计为下一代的CPU在二个时钟周期内对二个32位数相加的新的高速功能单元。它的基于软件的门级模拟在一高速工作站上将需要数千个时钟周期。当对这样的新功能单元设计需要验证多重操作周期时,所得的延迟较实际设计的操作延长了数个数量级,耗费整个模拟的相当多的时间。
这一问题的另一途径是“设计模拟”(例如QuickTurn公司的模拟手册中所介绍的),在此,一设计被映射在通过外部硬件连接的很大数量的传统的FPGA上,再实时地以较运行速度低得多的速度运行。这种模拟设备极为昂贵,需要长时间来建立各模拟周期,而有时根本不能映射实际的设计,因而未得到广泛应用。
在计算领域应用的举例
现在考虑一为作背景说明的在计算领域应用的示例,其中,一复杂的递归64位乘法运算功能性要由一另外的功能性来仿效,并要由一32位CPU执行1024个取样。由于CPU没有专用单元来执行这一任务,它被分割成包括64位乘算的多步骤32位实现在内的各种子任务并由执行多重32位加算将结果加到另一64位部分。此过程重复1024次。很明显这种执行耗费相当大的CPU时间,从而大大降低运行性能。
事实上本发明正是针对有效地解决这些和类似的问题,相信本发明是开发新型FPGA和相关体系结构和方法中的一个突破,它:
a以体系结构刷新提供即时可重配置性而不完全依靠装置速度;
b.提供自修正能力以便能实现高效高速流水线作业;
c.在芯片内部存储大量的配置信息(configuration);
d.为所提供功能设置较少的管脚数量;
e.因管脚减少而能相应地降低成本;以及
f.提供简单的系统接口以最小化设计工作量。
发明内容
因而,本发明一个目的就是提供一能排除包括上述这些的现有重新配置性限制及相关问题的采用新颖的基于DRAM的配置控制结构的新型完善的可作动态配置的门阵列系统、体系结构和方法,而同时低成本地大大增强系统运行性能,从而使得能对众多的应用基本上通用。
另一目的是提供一根据预定标准能自己修正逻辑实施的方法和设备。
再一目的是提供这样的新型系统,其中,在FPGA内部有可供应用的大量存储器并以小数量管脚加以访问,从而使得能在明显低的成本下重新配置时间较之传统措施快4个数量级。
还有一个目的是提供一基于这种新颖体系结构的在非重配置和重新配置应用中同样有效工作的系统。
其他的目的将在下面说明并在所附权利要求中作更具体的描述。
从一个主要观点出发,总的说本发明是增强一种配置可编程逻辑单元阵列的方法,其中每个单元各自具有被一相关的配置位存储器所控制的逻辑功能,它包括:在一DRAM芯中存储定义多重程序配置的位信息;连接总线到此阵列,使得能以定义所希望配置的位信息对单元的配置位存储器作DRAM行宽装载;和根据一配置命令至少一次一行地由DRAM芯检索配置位信息和在该单元的位存储器中装载这样的信息以控制对应的单元逻辑功能来实现所希望的配置编程。
根据本发明的另一方面,提供了一种用于配置一各自具有受相关配置位存储器控制的逻辑功能的可编程逻辑单元的阵列的设备,该设备组合有:用于存储定义多重程序配置的位信息的DRAM芯;将此阵列与DRAM芯相互连接的总线,以使得能以定义所希望配置的位信息对逻辑单元阵列的配置位存储器作DRAM行宽装载;用于生成配置命令的装置;以及根据这样的配置命令并作为响应由DRAM芯至少一次一行地检索配置位信息的装置;和用于将这些信息装载进逻辑单元的所述位存储器中以控制对应的单元逻辑功能来实现所希望的配置编程的装置。
后面详细说明优选和最佳方式设计和技术。
附图说明
现在结合附图说明本发明,附图1-3说明现有技术,所列附图为:
图1为典型的现有技术FPGA接口的方框图;
图2表明一典型的现有技术FPGA内部逻辑结构或阵列和路由通道;以及
图3说明用于例如图2中配置中的典型的现有技术配置逻辑单元;
图4为按照本发明构成的在此称之为“SONAL”体系结构的部分顶层体系结构的方框图,其中该名称代表Self-modifying,On-the-flyAlterable Logic(自修正即时可变逻辑);
图5为这种能实现自修正逻辑功能的新型体系结构的方框图。
图6也是按照本发明构成的实现称做“SONAL”FPGA的本发明的自修正“即时”可变逻辑的系统体系结构的方框图;
图7表示本发明“SONAL”FPGA的接线输出的举例;
图8为适用于一所谓的“PARAS”接口和访问机制(1994.10.7提交的共有未决的美国专利申请No.08/320058中有说明)和具有低管脚数的集成存储器体系结构的前述图7的“SONAL”FPGA的变型。
具体实施方式
现在顺序说明按照其新型的以“SONAL”为中心的解决方案的本发明,通过极大地降低消耗在FPGA的重新配置中的时间量和在需要时通过提供自修正模式来使得无需外部干预地作功能变换从而大大加速执行时间,以消除重新配置延迟和其它前面描述的瓶颈问题。另外的好处还包括FPGA内部大存储器的可行性,结果就降低了系统的成本,如前述。
如前面提到的,图1表示采用通过一总线系统并如所标记的,由与主存储器协同工作的CPU编程的FPGA单元(#1……#n)的现有技术FPGA接口,FPGA单元具有图2的内部逻辑单元结构或阵列和路由通路,其中各可配置逻辑单元具有如图3中所示由相关配置静态RAM(SRAM)所控制的逻辑功能,其中,配置数据被存储在小的经定位的内部静态RAM位中。但在本发明中,一如图4中所示的DRAM芯被用来存放多重配置信息,一访问控制电路,被连接到DRAM芯的输入并连接到一DRAM仲裁及刷新逻辑模块和一外部DRAM接口中之一或两者。还提供为装置配置所需的配置SRAM位。设置有一DRAM行宽总线(其中这里所用术语“行”也包含一行的部分即局部),它直接连接到SRAM位,随后再控制可编程元件。在给出一配置命令之后,每次检索一行并存放进所述SRAM位,直至所有需要的配置存储元素均被装载。由仅仅装载那些必须加以改变的SRAM位可实现局部再配置。本发明的进一步提高是提供屏蔽能力使得仅仅需加改变的位才被装载进配置SRAM。还有可能在芯片运行时装载新的配置数据进入DRAM。同一DRAM还可用作为能由外部I/O或通过内部逻辑访问的存储空间。从外部接口看将具有一窄的I/O宽度数据接口,但在内部其行宽总线则可被用来在一次访问中存储/检索最大一行宽的数据。一旦在内部选择了一行,以非常高的速度访问列数据的能力使其构成了用于状态机应用的理想空间。无需遵循传统的行和列相当数量的方法,在某些情况中,使行数多于列数的结构可能更有利于提供更快速的动态重配置。对全部这些功能性可利用示例作最佳说明。
现在考虑一需要32768位来配置其全部可编程元素并具有能加以重新配置的最大串行速率为10Mhz的传统的FPGA。其重配置时间则大致为3.3ms。假定一相应的“SONAL”含有一256K×8的DRAM芯作为图4中所示的其体系结构的一部分。在接收到重配置命令之后,在“SONAL”FPGA中检索一含有4096位的行(每行512位×8位宽)并存放于相应的配置SRAM位中。这种行检索和其后存储过程在这一例中重复8次以装载全部所需配置SRAM位。如果行检索速率为40ns,则为完全地重新配置FPGA需要总共320ns。这是本发明胜过当前存在的要求3.3ms的FPGA方案的最大优点。这样,本发明即提供优于传统措施近4个数量级的改善。还应指出,总线不一定必须是整个行宽而是并带有某种性能降低的可以如前述的这里仍称之为一“行”的行的一部分。
“SONAL”的这种快速的重新配置时间可借助于多重DRAM块(bank)的组合,如“m”个DRAM块,而得到进一步改善。这样,如果需要“r”行来配置装置并以“t”毫微秒检索一行,则
配置时间=r×t/m
具有配置SRAM位的一个原因是DRAM芯的刷新需要。当然也有可能通过经定位的DRAM单元来替代这些SRAM位,但由于因刷新需求所造成的干扰这不是最佳解决办法。这些位的消除将降低装置的成本和功率消耗。本发明的替换实施例包括采用二个相同的DRAM存储单元使得同一配置数据被装载进它们双方。假定一行提供为配置整个FPGA足够的数据,则无需任何SRAM位;而当一个存储单元在进行刷新时,另一个提供配置数据。这一概念可扩充到“m”个单元使得“m/2”个存储单元具有与另一“m/2”个存储单元同样的配置信息。
在该装置的一种应用中,多路复用的串行数据流能够被分割成组成该串行数据流的多个子串行数据流,并将这些子串行数据流转换成并行格式,同时装载进位于不同的预定地址的DRAM行。
在本发明的另一替换实施例中,一内部DRAM存储单元仅被用于重配置数据而另一内部存储单元则主要用于通用存储器,以使得二存储单元在外部通过同一接口加以访问以最大限度降低成本。
在本发明的又一实施例中,设计了如图5中所示的可实现的自修正电路。在自修正电路中设置有一访问控制电路,其连接到DRAM芯的输入,并响应由SRAM存储器芯发出的对应于DRAM行地址的数据位,从而内部地驱动DRAM的所选的行地址,该行地址的数据位包含等于唯一地译码DRAM行地址所需的位数的数据宽度,该SRAM芯还被连接于逻辑单元阵列以从逻辑单元阵列中接收地址位配置命令信号。在此自修正体系结构中SRAM芯地址单元数受制于重新配置能力所要求的程度。作为这种情况的一个示例,表示为32×9 SRAM。该SRAM芯具有5个地址位,由FPGA控制逻辑驱动。响应来自逻辑单元阵列的配置数据位命令或者在一定逻辑条件被满足时的适当事件或时刻,SRAM芯的输出被用来检索行宽配置数据。新的电路实现可具有驱动SRAM芯地址输入的不同控制逻辑,根据各种电路元件的状态自动地连续实现另一个电路功能,这样,芯片功能性即能动态地变换到服从于一定的逻辑条件的结果的预定逻辑实现。此技术提供要求来自相连CPU的干预最小的高效率自修正电路,从而大大增强整个系统的运行性能,并具有在数字信号处理算法、流水线设计等中广泛范围的应用。一种潜在的应用是将大的流水线设计分段成为多重配置和这些配置程序如需要时由处理硬件加以装载。由于门的可重复使用性,这大大减少实现设计所需的门的数量,从而降低芯片成本。这仅因为非常高速度的“即时”自修正能力才能实现。
此SRAM芯也可利用其他的技术例如Flash或EEPROM来实现。
在此系统层次,可将多重这样的“SONAL”装置连接在系统总线上以增强机器的能力,如图6中所示。应当指出,这种即时重新配置措施或自修正电路并不仅限于FPGA,而且也能是含有类似的可重配置元素的CPU的部分。
例如考虑被专门设计为独立平台的“JAVA”(最广泛应用的互联网语言),藉此提供在各种机器中的完全可移值性。缺点是“JAVA”运行极为缓慢,因为它不能利用不同CPU的独特的体系结构能力。改善“JAVA”执行速度的一种途径是通过对其提供在非常高速度时可改变的公用虚拟硬件平台(在传统CPU功能之外)。这一虚拟硬件可通过在CPU自身上提供带有“SONAL”能力的可配置性来实现或者以作为分开的“SONAL”FPGA来实现。这样,这一体系结构维持独立平台的关键元素,但取得较高的执行速度。
‘SONAL’I/O接口
此芯片具有某种不同的接线输出反映其独特的体系结构。一种可能的接线输出示例如图7所示,提供具有分开的地址和数据总线的传统的DRAM接口。现在考虑一带有256K×8 DRAM的“SONAL”示例。利用传统的DRAM访问方式,需要21根接线(地址9个,数据8个,“RAS”、“CAS”、“WRITE”和“Output Enable”各1个)。每当发生FPGA单元与DRAM芯之间的内部传输时还提供系统总线接口一个“WAIT”信号。CPU(或其他主控器)可以或者利用它来延迟访问的起始,或者在一替代实现中,可扩展访问周期来使得在此访问继续前进之前完成此内部传输。如果连同此“SONAL”结构一起采用所述的同时申请的被称为“PARAS”DRAM的接口访问机制,即能进一步完善本发明来减少接线数并因而降低成本。(这一申请中揭示一种用于依靠新颖的接口和访问过程来改善异步和同步动态随机存取存储器装置的访问能力的方法和设备,其中,同样的接线在读和写周期双方均被用于每一行、列和数据访问,这样使得能在基本同样尺寸的封装但具有较少接线的条件下有效地增加数据带宽和寻址范围。)采用这种“PARAS”模块,如图8中所示仅需13根接线和一附加的用于“WAIT”的接线。另外还应注意到,在配置数据已被装载后无需访问DRAM并因而无需外部访问的应用中,相同的接线可被用作为传统的FPGAI/O接线。
通过将行和列地址分割成多重的子地址和通过在相同引线上共享数据和控制接线,还有可能进一步降低I/O接线数。这显然会减缓来自外部装置如CPU的访问时间,但提供更低的接线数,降低的成本,和运行中的即时可变FPGA。
利用‘SONAL’实现的模拟应用
作为一例,如果为下一代CPU设计一个能在2个时钟周期内计算二个32位数的快速32位加法器并将给工作站配置作为协作处理器运行的“SONAL”型FPGA,则加法器模拟一般将需数个时钟周期。按照此优选实施例,“SONAL”可进行动态重新配置而后可通过在这样配置的“SONAL”上实时执行任务来验证其功能。这远远胜过传统的无“SONAL”措施的工作站,后者通常需数千个周期。
利用‘SONAL’实现的计算应用
再次用来说明基础情况,一伴随有加法功能的复杂的递归64位乘法功能的计算应用例,如果对1024个取样由一32位CPU执行它,设置有“SONAL”的CPU将其配置为在一步中执行此递归64位功能的功能专门单元而运行,由此而能较之前面说明的传统措施大大改善机器运行性能。
因此如前面已指出的,利用本发明的这种新颖FPGA体系结构的优点就在于:提供带体系结构创新的即时可重配置性而不致完全依赖装置的速度;自修正能力使得高效高速的实现;在芯片内部存储大量的配置信息,减少用于所设置功能的接线数,因接线数减少而使成本相对降低;和提供近乎与现有FPGA单元同样的系统设计接口,从而使设计周期最小。
对于本技术领域中熟悉人员还可作的进一步变更,其中包括设置能使高速串行数据装载进用于网络化、多媒体和其他应用的DRAM的逻辑,并作为CPU本身的部分而不是一外部装置实施该措施,或连同用于快速可重配置性的内部连接一起应用这种外部DRAM接口到除FPGA外的其他装置,而这些均被认为是属于如所附权利要求中所定义的本发明的精神实质和范畴之内。
Claims (26)
1、一种用于配置各自具有受一相关的配置位存储器控制的逻辑功能的可编程逻辑单元的阵列的方法,包括:
在一DRAM芯中存储定义多重程序配置的位信息;
连接一总线到此阵列使得能以定义所希望配置的位信息对单元的配置位存储器作DRAM行宽装载;和根据一配置命令,由DRAM芯至少一次一行地检索配置位信息,并将这种信息装载进单元的位存储器以控制对应单元逻辑功能来实现所希望的配置编程。
2、如权利要求1中所述方法,其特征是所述一次一行的检索和装载使得能作即时重新配置。
3、如权利要求1中所述方法,其特征是所述阵列包括一FPGA装置,和逻辑单元位存储器包括配置SRAM位。
4、如权利要求1中所述方法,其特征是在由逻辑单元阵列完成一功能后,生成位命令来指示阵列的新的所希望功能,和设置一辅助存储器芯,该芯包含一DRAM行地址并被连接来响应下一功能的位命令并相应地驱动DRAM,检索并在单元的位存储器中装载代表所述下一功能的配置位信息,控制对应的单元逻辑功能并由此可自行重配置此阵列以执行下一功能。
5、如权利要求4中所述方法,其特征是所述可自行重配置性对于随后的所希望的功能命令能自动地继续进行。
6、如权利要求3中所述方法,其特征是由仅装载那些需加变更的SRAM位来实现部分的重新配置。
7、如权利要求1中所述方法,其特征是DRAM芯也被用作为可由外部I/O接口和内部逻辑双方访问的存储空间。
8、如权利要求7中所述方法,其特征是在进行外部接口期间,在一次访问中内部行宽总线存储/检索最大一行宽的数据,和一旦内部选择了一行,就快速地存取列数据。
9、如权利要求1中所述方法,其特征是在装置运行中将新的配置数据装载进DRAM芯。
10、一种用于配置一各自具有受相关配置位存储器控制的逻辑功能的可编程逻辑单元的阵列的设备,该设备组合有:用于存储定义多重程序配置的位信息的DRAM芯;将此阵列与DRAM芯相互连接的总线,以使得能以定义所希望配置的位信息对逻辑单元阵列的配置位存储器作DRAM行宽装载;用于生成配置命令的装置;以及根据这样的配置命令并作为响应由DRAM芯至少一次一行地检索配置位信息的装置;和用于将这些信息装载进逻辑单元的所述位存储器中以控制对应的单元逻辑功能来实现所希望的配置编程的装置。
11、如权利要求10中所述设备,其特征是此阵列包括一FPGA装置,和逻辑单元位存储器包括配置SRAM位。
12、如权利要求10中所述设备,其特征是设置有一访问控制电路,被连接到DRAM芯的输入并连接到一DRAM仲裁及刷新逻辑模块和一外部DRAM接口中之一或两者。
13、如权利要求11中所述设备,其特征是设置有一访问控制电路,其连接到DRAM芯的输入,并响应由SRAM存储器芯发出的对应于DRAM行地址的数据位,从而内部地驱动DRAM的所选的行地址,该行地址的数据位包含等于唯一地译码DRAM行地址所需的位数的数据宽度,该SRAM芯还被连接于逻辑单元阵列以从逻辑单元阵列中接收地址位配置命令信号。
14、如权利要求13中所述设备,其特征是所述配置命令信号在完成一功能后由逻辑单元阵列产生,并作为阵列下一所希望功能的新的配置,和根据被指定的DRAM行地址从访问控制装置相应地译码DRAM芯,用于装载从DRAM芯返回的代表所述下一功能的配置位信息的装置,在逻辑单元的位存储器中,由此来控制对应的单元逻辑功能并因此自行再配置此阵列以执行下一功能,其中所述自行再配置自动地针对随后所希望的功能命令继续进行。
15、如权利要求14中所述设备,其特征是逻辑单元阵列生成5个地址位和SRAM单元生成对应于DRAM行地址的9个数据位,此SRAM单元含有32×9位。
16、如权利要求10中所述设备,其特征是逻辑单元阵列在完成一功能后生成一位命令以指示阵列下一个所希望的功能;并还设置有包含一DRAM行的位地址的辅助存储器芯并被连接在阵列与DRAM芯之间来响应所述下一功能位命令和相应地驱动DRAM以在阵列的单元的位存储器中检索并装载表示所述下一功能的配置位信息来控制对应的单元逻辑功能,由此使阵列的自行重配置能执行所述下一功能。
17、如权利要求16中所述设备,其特征是此辅助存储器芯包括SRAM芯。
18、如权利要求16中所述设备,其特征是根据随后所希望的功能命令自动地进行自行重配置。
19、如权利要求11中所述设备,其特征是仅实现部分重新配置,其中此装载装置仅装载那些需要改变的SRAM位。
20、如权利要求10中所述设备,其特征是DRAM芯也被用作为可由外部I/O接口和内部逻辑访问的存储空间。
21、如权利要求20中所述设备,其特征是在进行外部接口期间,内部行宽总线在一次访问中存储/检索最大一行宽的数据,和一旦内部选定一行,即提供装置迅速访问列数据。
22、如权利要求10中所述设备,其特征是此阵列为可编程装置的一部分,并且新的配置数据在装置运行时装载进DRAM芯中。
23、如权利要求22中所述设备,其特征是此装置包括FPGA。
24、如权利要求11中所述设备,其特征是此一次一行的检索和装载使得能进行即时重配置。
25、如权利要求11中所述设备,其特征是设置有各自被装载有相同配置数据的两个相同的DRAM存储单元。
26、如权利要求24中所述设备,其特征是在一存储单元在对其DRAM芯进行刷新时另一个提供配置数据。
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- 1997-08-12 WO PCT/IB1997/000987 patent/WO1998008306A1/en active IP Right Grant
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CA2264060A1 (en) | 1998-02-26 |
KR100458371B1 (ko) | 2004-11-26 |
CA2264060C (en) | 2008-01-08 |
EP0931380A1 (en) | 1999-07-28 |
EP0931380B1 (en) | 2002-07-03 |
CN1234923A (zh) | 1999-11-10 |
WO1998008306A1 (en) | 1998-02-26 |
ATE220263T1 (de) | 2002-07-15 |
US5838165A (en) | 1998-11-17 |
JP3801214B2 (ja) | 2006-07-26 |
AU3705297A (en) | 1998-03-06 |
JP2000516418A (ja) | 2000-12-05 |
DE69713784T2 (de) | 2003-03-13 |
DE69713784D1 (de) | 2002-08-08 |
HK1023458A1 (en) | 2000-09-08 |
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