CN118786524A - 采用焊盘金属化层以增加信号路由容量的封装基板、相关集成电路（ic）封装件和制造方法 - Google Patents

采用焊盘金属化层以增加信号路由容量的封装基板、相关集成电路（ic）封装件和制造方法 Download PDF

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Publication number
CN118786524A
CN118786524A CN202380024363.6A CN202380024363A CN118786524A CN 118786524 A CN118786524 A CN 118786524A CN 202380024363 A CN202380024363 A CN 202380024363A CN 118786524 A CN118786524 A CN 118786524A
Authority
CN
China
Prior art keywords
metal
layer
pad
metallization layer
interconnects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202380024363.6A
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English (en)
Chinese (zh)
Inventor
J·R·V·鲍特
Z·王
A·帕蒂尔
卫洪博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN118786524A publication Critical patent/CN118786524A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
CN202380024363.6A 2022-03-25 2023-02-24 采用焊盘金属化层以增加信号路由容量的封装基板、相关集成电路（ic）封装件和制造方法 Pending CN118786524A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/656,477 US20230307336A1 (en) 2022-03-25 2022-03-25 Package substrates employing pad metallization layer for increased signal routing capacity, and related integrated circuit (ic) packages and fabrication methods
US17/656,477 2022-03-25
PCT/US2023/063216 WO2023183692A1 (en) 2022-03-25 2023-02-24 Package substrates employing pad metallization layer for increased signal routing capacity, and related integrated circuit (ic) packages and fabrication methods

Publications (1)

Publication Number Publication Date
CN118786524A true CN118786524A (zh) 2024-10-15

Family

ID=85724526

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202380024363.6A Pending CN118786524A (zh) 2022-03-25 2023-02-24 采用焊盘金属化层以增加信号路由容量的封装基板、相关集成电路（ic）封装件和制造方法

Country Status (7)

Country Link
US (1) US20230307336A1 (https=)
EP (1) EP4500590A1 (https=)
JP (1) JP2025509901A (https=)
KR (1) KR20240161103A (https=)
CN (1) CN118786524A (https=)
TW (1) TW202407815A (https=)
WO (1) WO2023183692A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20250309168A1 (en) * 2024-03-29 2025-10-02 Micron Technology, Inc. Semiconductor package having an array of multi-sized interconnect structures

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5150518B2 (ja) * 2008-03-25 2013-02-20 パナソニック株式会社 半導体装置および多層配線基板ならびにそれらの製造方法
US9603247B2 (en) * 2014-08-11 2017-03-21 Intel Corporation Electronic package with narrow-factor via including finish layer
US9431351B2 (en) * 2014-10-17 2016-08-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US9420695B2 (en) * 2014-11-19 2016-08-16 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor process
KR102065943B1 (ko) * 2015-04-17 2020-01-14 삼성전자주식회사 팬-아웃 반도체 패키지 및 그 제조 방법
US10475736B2 (en) * 2017-09-28 2019-11-12 Intel Corporation Via architecture for increased density interface
US11769719B2 (en) * 2018-06-25 2023-09-26 Intel Corporation Dual trace thickness for single layer routing
US20200027728A1 (en) * 2018-07-23 2020-01-23 Intel Corporation Substrate package with glass dielectric
US11488918B2 (en) * 2018-10-31 2022-11-01 Intel Corporation Surface finishes with low rBTV for fine and mixed bump pitch architectures
US11948877B2 (en) * 2020-03-31 2024-04-02 Qualcomm Incorporated Hybrid package apparatus and method of fabricating
US11605595B2 (en) * 2020-08-14 2023-03-14 Qualcomm Incorporated Packages with local high-density routing region embedded within an insulating layer

Also Published As

Publication number Publication date
WO2023183692A1 (en) 2023-09-28
EP4500590A1 (en) 2025-02-05
JP2025509901A (ja) 2025-04-11
US20230307336A1 (en) 2023-09-28
TW202407815A (zh) 2024-02-16
KR20240161103A (ko) 2024-11-12

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