CN118486346A - Signal processing circuit - Google Patents

Abstract

The embodiment of the disclosure relates to the field of semiconductors, in particular to a signal processing circuit, which is applied to a semiconductor memory and used for writing data and reading data, wherein the semiconductor memory comprises a data port, a first memory block and a second memory block which are longitudinally arranged, and the signal processing circuit comprises: the first output module is positioned at one side of the first storage block close to the data port, is connected with a first global data line of the first storage block, and is used for receiving first data of the first storage block through the first global data line and outputting the first data to the data port; the second output module is positioned between the first storage block and the second storage block, connected in series between the first global data line and the second global data line of the second storage block, and used for receiving second data of the second storage block through the second global data line and outputting the second data to the data port through the first global data line. The embodiment of the disclosure is beneficial to solving the problem of larger power consumption of the semiconductor memory.

Description

Signal processing circuit

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a signal processing circuit.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory device commonly used in computers and consists of many repeated memory cells. Each memory cell typically includes a capacitor and a transistor having a gate connected to a word line, a drain connected to a bit line, and a source connected to the capacitor, a voltage signal on the word line being capable of controlling the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information to the capacitor through the bit line for storage.

Along with the increasing fields of DRAM application, such as DRAM being increasingly applied to the mobile field, the requirement of users on DRAM power consumption index is higher and higher, and specific requirements on the speed and power saving of DRAM are met, so that the DRAM can save more power, and meanwhile, the signal integrity and the reliability of data transmission and storage can be ensured, which is a problem to be solved in the industry.

Disclosure of Invention

The embodiment of the disclosure provides a signal processing circuit which is at least beneficial to solving the problem of high power consumption of a semiconductor memory.

The embodiment of the disclosure provides a signal processing circuit applied to a semiconductor memory for writing data and reading data, the semiconductor memory including a data port and first and second memory blocks arranged longitudinally, the signal processing circuit comprising: the first output module is positioned at one side of the first storage block far away from the second storage block, is connected with a first global data line of the first storage block and is used for receiving and outputting first data of the first storage block through the first global data line; the second output module is positioned between the first storage block and the second storage block, is connected in series between the first global data line and the second global data line of the second storage block, and is used for receiving second data of the second storage block through the second global data line and outputting through the first global data line.

In some embodiments, further comprising: the first write driving module comprises a first write driving unit which is connected with the first global data line and is used for responding to a first write enabling signal and data to be written to output write data, and the write data is transmitted to the first storage block through the first global data line or transmitted to the second storage block through the first global data line and the second global data line.

In some embodiments, the first memory block further comprises: a first global complementary data line, the first memory block receives the write data through the first global data line and the first global complementary data line; further comprises: and the first inverting circuit is used for responding to the enabling of a write signal, the input end of the first inverting circuit is connected with the first global data line and is used for receiving the write data in the first global data line, and the output end of the first inverting circuit is connected with the first complementary global data line.

In some embodiments, further comprising: the verification module is connected with the first output module and the first writing driving module; the verification module corrects the first output data based on the first verification data by receiving the first output data output by the first output module and the first verification data corresponding to the first output data, and outputs corrected first correction data, wherein the first verification data is output by the first output module; the verification module also receives second output data output by the second output module and second verification data corresponding to the second output data through the first global data line, so as to correct the second output data based on the second verification data and output verified second correction data; the first write data includes: the system comprises first original input data and first original check data, wherein the first original check data is generated by the check module according to the first original input data.

In some embodiments, further comprising: the first global complementary data line is connected to the first memory block and the first write driving module, and the first write driving module further includes: and a second write driving unit for outputting complementary write data, which is transferred to the first memory block via the first global complementary data line, in response to the first write enable signal and complementary data to be written.

In some embodiments, further comprising: the second write driving module is positioned between the first storage block and the second storage block, responds to a second write enabling signal and second data to be written to output second write data, and the second write data is transmitted to the second storage block through the second global data line; the second write data includes: the system comprises a verification module, a first original input data and first original verification data, wherein the first original verification data is generated by the verification module according to the first original input data.

In some embodiments, the second write driving module includes two sub write driving units, where one of the sub write driving units is configured to receive the second write enable signal and the second data to be written, and output the second write data, where the second write data is transmitted to the second storage block through the second global data line; the other sub-write driving unit is used for receiving the second write enabling signal and complementary second data to be written and outputting complementary second write data, and the complementary second write data are transmitted to the second storage block through the second global complementary data line.

In some embodiments, further comprising: the read driving module is located between the first storage block and the second storage block, connected to the first global data line and the second output module, and used for responding to a read enabling signal and the second output data to output read data, and the read data is transmitted to the first output module through the first global data line.

In some embodiments, further comprising: a first global complementary data line, the first output module being connected to the first global data line and the first global complementary data line, configured to: and receiving and outputting first data represented by the first global data line and the first global complementary data line.

In some embodiments, further comprising: and the second inverting circuit is used for responding to the reading signal enabling, the input end of the second inverting circuit is connected with the first global data line and is used for receiving the first data in the first global data line, and the output end of the second inverting circuit is connected with the first global complementary data line.

In some embodiments, further comprising: a second global complementary data line, the second output module being connected to the second global data line and the second global complementary data line, configured to: and receiving and outputting the second data represented by the second global data line and the second global complementary data line.

The technical scheme provided by the embodiment of the disclosure has the following advantages:

in the technical scheme of the signal processing circuit provided by the embodiment of the disclosure, the first output module is arranged on one side, close to the data port, of the first storage block, the second output module is arranged between the first storage block and the second storage block, and the second output module and the first output module respectively receive the first data from the first storage block and the second data from the second storage block. Because the first output module is closer to the data port DQ, the transmission path of the output data output by the first output module to the data port DQ is shorter, the transmission distance of the output data output by the first output module crossing the first storage block is saved, the transmission loss of the first data can be reduced, and the power consumption can be saved.

In addition, the second output module processes the second data and outputs the output data through the first global data line of the first storage block, namely, the first global data line of the first storage block is used as a transmission line of the output data of the second output module, so that the line is saved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a schematic diagram of a DRAM (Dynamic Random Access Memory );

FIG. 2 is a schematic diagram of a DRAM structure according to an embodiment of the present disclosure;

Fig. 3 to 13 are 11 structural diagrams of a signal processing circuit according to an embodiment of the disclosure.

Detailed Description

As is clear from the background art, there is a problem that the power consumption of the semiconductor memory is high at present. One of the reasons why the power consumption of the semiconductor memory is high is found by analysis that, referring to fig. 1, in the semiconductor memory, a common output module 3 is generally provided between the first memory block 1 and the second memory block 2, and the first data from the first memory block 1 and the second data from the second memory block 2 are received and outputted. Since the output module 3 is located between the first memory block 1 and the second memory block 2, the first data in the first memory block 1 needs to be transferred to the output module 3 through the first global data line YIO of the first memory block 1, and the second data in the second memory block 2 needs to be transferred to the output module 3 through the second global data line YIO of the second memory block 2. Since the distance between the output module 3 and the data port DQ is longer, an external data line Databus needs to be set to cross the first memory block 1, so that the data output by the output module 3 is transmitted to the data port DQ through the external data line Databus, and the external data line Databus crosses the first memory block 1, so that the external data line is too long, which will cause the problem of large power consumption for each reading and writing, and cause the problem of too high power consumption.

The embodiment of the disclosure provides a signal processing circuit, in which a first output module 101 is disposed on one side of a first memory block 1 near a data port DQ, a second output module 102 is disposed between the first memory block 1 and a second memory block 2, and the second output module 102 and the first output module 101 respectively receive first data from the first memory block 1 and second data from the second memory block 2. Because the first output module 101 is closer to the data port DQ, the transmission path of the output data outputted by the first output module 101 to the data port DQ is shorter, which saves the distance that the first data of the first memory block 1 need to cross the first memory block 1 after being outputted, not only reduces the transmission loss of the first data, but also saves the power consumption.

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. The technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.

In the embodiments of the present disclosure, the signal processing circuit is applied to a semiconductor memory for writing data to and reading data from the semiconductor memory.

In some embodiments, the semiconductor Memory may be a ROM (Read only Memory) or a RAM (Random Access Memory ), for example, may be a DRAM, an SRAM (Static Random-Access Memory), or an SDRAM (synchronous dynamic Random Memory).

Referring to fig. 2, taking a semiconductor memory as an example of a DRAM, the DRAM may be composed of a plurality of memory blocks (banks), each of which includes a number of memory arrays.

Each read operation is performed for only one memory block. That is, when one of the plurality of memory blocks is operated, the other memory block is not operated. The data read out from the memory block is output through the DQ port by the signal processing circuit.

In some embodiments, the semiconductor memory is in an array structure, and the structures of the plurality of memory blocks may be the same, but the data output by each memory block may be different due to different input data. The number of memory blocks, the number of bits of data of each memory block, and the number and number of bits of data of the data port DQ are not limited by the embodiment of the present disclosure. For example, the number of memory blocks may be 8, and each memory block includes a first memory block 1 and a second memory block 2, that is, the number of first memory blocks may be 8, which are respectively denoted as Bank0P, bank P, … …, and Bank7P; the number of the second memory blocks may be 8, and is respectively denoted as Bank0Q, bank Q, … …, and Bank7Q.

The signal processing circuit of the embodiment of the present disclosure will be described below by taking one of the memory blocks as an example.

Referring to fig. 2, the signal processing circuit includes: the first output module 101 is located at a side of the first memory block 1 near the data port DQ, the first output module 101 is connected to the first global data line YIO of the first memory block 1, and the first output module 101 is configured to receive the first data of the first memory block 1 through the first global data line YIO and output the first data to the data port DQ; the second output module 102 is located between the first memory block 1 and the second memory block 2, and the second output module 102 is connected in series between the first global data line YIO and the second global data line YIO and is configured to receive the second data of the second memory block 2 and output the second data to the data port DQ through the first global data line YIO 1.

The data port DQ is located at a side of the first memory block 1 far away from the second memory block 2, so that the first output module 101 is closer to the data port DQ, so that a transmission path for transmitting output data output by the first output module 101 to the data port DQ is shorter, and an external data line crossing the first memory block 1 is not required to be additionally arranged, so that the distance that the first data of the first memory block 1 need to cross the first memory block 1 after being output is avoided, the transmission loss of the first data can be reduced, and the power consumption can be saved.

In addition, the output data output after the second output module 102 processes the second data is output through the first global data line YIO1 of the first memory block 1, that is, the first global data line YIO1 of the first memory block 1 is used as a transmission line of the output data of the second output module 102, so that the line is saved.

Referring to fig. 3 and 4, in some embodiments, further comprising: the first write driving module 103, where the first write driving module 103 includes a first write driving unit 111 connected to the first global data line YIO, and the first write driving unit 111 is configured to output write data in response to a first write enable signal and data to be written, and the write data is transmitted to the first memory block 1 through the first global data line YIO1 or transmitted to the second memory block 2 through the first global data line YIO1 and the second global data line YIO. In some embodiments, the first write driving unit 111 is configured to receive data to be written, output first write data, the first write data is configured to be transferred to the first memory block 1, and output second write data, the second write data is configured to be transferred to the second memory block 2.

In some embodiments, referring to fig. 4, further comprising: the first global complementary data line YIOF1, the first global complementary data line YIOF1 and the first global data line YIO1 transmit signals that are opposite to each other, and the first memory block 1 receives write data through the first global data line YIO and the first global complementary data line YIOF 1. The first global data line YIO and the first global complementary data line YIOF are differential data lines, and the data transmitted in the two data lines can be mutually referred to, so that the accuracy of the transmitted write-in data is improved.

In some embodiments, the first write driving module 103 includes only one first write driving unit 111, and then further includes: the input end of the first inverter circuit is connected to the first global data line YIO for receiving the write data in the first global data line YIO1, and the output end of the first inverter circuit is connected to the first complementary global data line. In the data writing stage, the input end of the first inverting circuit receives the writing transmission data transmitted in the first global data line YIO, the output end of the first inverting circuit outputs complementary writing transmission data inverted with the writing transmission data, and the writing transmission data and the complementary writing transmission data form writing data, so that the writing data transmitted to the first storage block 1 comprises two signals which are inverted mutually and are mutually referenced, and the accuracy of data transmission is improved. That is, the signal transmitted in the first global complementary data line YIOF is obtained by inverting the data output in the first write driving unit 111.

In some embodiments, the first inverter circuit is a first inverter 4, an input terminal of the first inverter 4 is connected to the first global data line YIO, and an output terminal of the first inverter 4 is connected to the first global complementary data line YIOF.

Referring to fig. 5, in some embodiments, further comprising: the first global complementary data line YIOF, connected to the first memory block 1 and the first write driving module 103, the first write driving module 103 may further include: the second write driving unit 112, the second write driving unit 112 is configured to output complementary write data in response to the first write enable signal and complementary data to be written, and the complementary write data is transferred to the first memory block 1 via the first global complementary data line YIOF. That is, when the first write driving module 103 includes the first write driving unit 111 and the second write driving unit 112, the first write driving unit 111 and the second write driving unit 112 are respectively configured to output signals in opposite directions for being transferred to the first memory block 1 via the first global data line YIO and the first global complementary data line YIOF, respectively. That is, before the data to be written is input into the second writing driving unit, the data to be written is inverted to obtain complementary data to be written, and the data to be written and the complementary data to be written are input into the writing driving module and then output to the first storage block 1.

In some embodiments, when the first write driving module 103 includes the first write driving unit 111 and the second write driving unit 112, it may further include: the input end of the second inverter 5 receives the data to be written, and the output end of the second inverter 5 is connected to the input end of the second writing driving unit 112 to input the complementary data to be written to the input end of the second writing driving unit 112.

It is noted that in some embodiments, when the data to be written is transferred through the first global data line YIO and the first global complementary data line, the data to be written is transferred only into the first memory block 1, and not into the second memory block 2. This is because, when the first global data line YIO and the first global complementary data line are used to write data into the first memory block 1, the first memory block 1 is activated, when the internal functional module operates, the first global data line YIO and the first global complementary data line will be interfered by the data signal transmitted by the first global data line YIO, in order to ensure the accuracy of the data, the complementary global data line pair needs to be used to transmit the data, and when the data signal is transmitted to the second memory block 2, since the first memory block 1 is not activated, only the second memory block 2 is activated, therefore, there is no concern about the influence on the data signal transmitted by the first global data line YIO and the first global complementary data line when the internal functional module operates, the accuracy of the data can be ensured by using only the first global data line YIO, and when the data signal is transmitted to the second memory block 2, in order to avoid the interference on the data signal when the functional module operates, the complementary data signal to be generated between the first memory block 1 and the second memory block 2 is generated, the accuracy of the complementary data to be written can be ensured, and the accuracy of the data to be improved can be guaranteed.

In some embodiments, the first write driving unit 111 and the second write driving unit have the same structure, the input terminal of the first write driving unit 111 receives the data to be written, and the input terminal of the second write driving unit 112 receives the complementary write data which is inverted to the data to be written, so that the signals output by the first write driving unit 111 and the second write driving unit 112 are inverted signals. The configuration of the write driver module is described below taking the first write driver module 103 as an example.

Referring to fig. 6, in some embodiments, the first write driving unit 111 may include:

The two input ends of the first nand gate 12 respectively receive the first write enable signal WriteEn1 and the data to be written.

The first nor gate 11 has a first input terminal receiving data to be written, a second input terminal receiving a complementary first write enable signal WriteEnF, and complementary first write enable signals WriteEnF and WriteEn1 being opposite signals to each other.

The first PMOS transistor MP1, the gate of the first PMOS transistor MP1 is connected to the output end of the first nand gate 12, the drain of the first PMOS transistor MP1 is connected to the first global data line YIO1, and the source of the first PMOS transistor MP1 is connected to the high-level voltage VCC.

The gate of the first NMOS transistor MN1 is connected to the output end of the first nor gate 11, the drain of the first NMOS transistor MN1 is connected to the first global data line YIO and the drain of the first PMOS transistor MP1, and the source of the first NMOS transistor MN1 is connected to the low-level voltage VSS, for example, may be connected to the ground.

In some embodiments, the first write enable signal WriteEn may be a logic high signal, corresponding to a logic level of "1", and the data to be written may be either a logic high signal or a logic low signal, so that the logic level output after the first nand gate 12 receives the first write enable signal WriteEn1 and the data to be written is the same as the logic level output after the first nor gate 11 receives the complementary first write enable signal WriteEnF1 and the data to be written, and is either a logic high level "1" or a logic low level "0". Therefore, only the first PMOS transistor MP1 is driven to be turned on or the first NMOS transistor MN1 is driven to be turned on, so that one of the high level voltage VCC or the low level voltage VSS is transmitted to the first global data line YIO1.

For example, if the first nand gate 12 and the first nor gate 11 both output a logic high level "1", the first NMOS transistor MN1 is turned on, the first PMOS transistor MP1 is turned off, and the level of the first global data line YIO is pulled down to the low level voltage VSS; if the first nand gate 12 and the first nor gate 11 both output a logic low level "0", the first PMOS transistor MP1 is turned on, the first NMOS transistor MN1 is turned off, and the level of the first global data line YIO is pulled up to the high-level voltage VCC.

Referring to fig. 7, in some embodiments, further comprising: further comprises: the second write driving module 104 is located between the first memory block 1 and the second memory block 2, and the second write driving module 104 outputs second write data in response to the second write enable signal and the second data to be written, and the second write data is transferred to the second memory block 2 through the second global data line YIO. The second data to be written is transmitted to the first write driving unit 111 through the data port DQ, is output through the first write driving unit 111, and is transmitted to the input end of the second write driving module 104 through the first global data line YIO 1.

In some embodiments, further comprising: the second global complementary data line YIOF2, the second global complementary data line YIOF2 and the second global data line YIO2 transmit signals that are opposite to each other, and the second write data and the complementary second write data are transmitted to the second memory block 2 through the second global data line YIO and the second global complementary data line YIOF2, and the second write data and the complementary second write data constitute second data. The data transferred in the second global data line YIO and the second global complementary data line YIOF may be referred to each other, improving accuracy of the data transferred into the second memory block 2.

Referring to fig. 8, in some embodiments, the second write driving module 104 includes two sub-write driving units 113, wherein one sub-write driving unit 113 is configured to receive a second write enable signal and second data to be written, and output second write data, and the second write data is transmitted to the second memory block 2 through the second global data line YIO; the other sub write driving unit 113 is configured to receive a second write enable signal and complementary second data to be written and output complementary second write data, and the complementary second write data is transferred to the second memory block 2 through the second global complementary data line YIOF.

The complementary second data to be written is an inversion signal of the second data to be written, and in some embodiments, the complementary second data to be written is obtained by inverting the second data to be written, instead of being transmitted to the input terminal of the sub-write driving unit 113 by the first global complementary data line YIOF. This is because, if the second memory block 2 is far from the data port DQ, if the complementary second data to be written is transmitted to the second write driving module 104 via the first global complementary data line YIOF, the transmission distance is far, which may result in that the complementary second data to be written is more lossy and requires additional power consumption (or requires larger driving capability), and the complementary second data to be written is obtained after the second data to be written is inverted, so that a part of transmission paths of the complementary second data to be written can be omitted, and further, accuracy of the complementary second data to be written can be improved.

Referring to fig. 8, in some embodiments, the second data to be written is transmitted from the first global data line YIO to the input terminal of one sub-write driving unit 113, and further includes that the input terminal of the third inverter 6 is connected to the first global data line YIO1 for receiving the second data to be written transmitted in the first global data line YIO1, and the output terminal of the third inverter 6 is connected to the input terminal of another sub-write driving unit 113 for transmitting the complementary second data to be written, which is inverted to the second data to be written, to the input terminal of another sub-write driving unit 113.

Referring to fig. 9, in some embodiments, the two sub-write driving units 113 have the same structure, and taking one of the sub-write driving units 113 as an example, the sub-write driving unit 113 may include:

The two input ends of the second nand gate 22 respectively receive the second write enable signal WriteEn and the second data to be written.

The second nor gate 21, the first input terminal of the second nor gate 21 receives the second data to be written, the second input terminal receives the complementary second write enable signal WriteEnF, and the complementary second write enable signal WriteEnF and the second write enable signal WriteEn2 are opposite signals.

The gate of the second PMOS MP2 is connected to the output end of the second nand gate 22, the drain of the second PMOS MP2 is connected to the second global data line YIO2, and the source of the second PMOS MP2 is connected to the high-level voltage VCC.

The gate of the second NMOS transistor MN2 is connected to the output end of the second nor gate 21, the drain of the second NMOS transistor MN2 is connected to the second global data line YIO and the drain of the second PMOS transistor MP2, and the source of the second NMOS transistor MN2 is connected to the low-level voltage VSS, for example, may be connected to the ground.

It is noted that, in the other sub-write driving unit 113, the two input ends of the second nand gate 22 respectively receive the second write enable signal WriteEn and the complementary second data to be written. The first input of the second nor gate 21 receives complementary second data to be written. The drain of the second PMOS transistor MP2 is connected to the complementary second global data line YIO2, and the drain of the second NMOS transistor MN2 is connected to the complementary second global data line YIO.

In some embodiments, the first write enable signal WriteEn and the second write enable signal WriteEn may be the same signal or the same signal from the same source but delayed differently.

The first output module 101 and the second output module 102 are respectively configured to process and output the first data and the second data, and because the distance between the first output module 101 and the data port DQ is relatively short, the transmission distance from the output data output by the first output module 101 to the data port DQ is relatively short, which saves the distance that the first data of the first memory block 1 need to span the first memory block 1 after being output, not only reduces the transmission loss of the first data, but also saves the power consumption. And the output data output after the second output module 102 processes the second data is output through the first global data line YIO of the first memory block 1, that is, the first global data line YIO1 of the first memory block 1 is used as a transmission line of the output data of the second output module 102, so that the line is saved.

In some embodiments, the first output module 101 is further configured to amplify and output the first data, and the second output module 102 is further configured to amplify and output the second data. The first output module 101 receives the first data, outputs the first amplified data, and the second output module 102 receives the second data, and outputs the second amplified data.

Referring to fig. 6, in some embodiments, the first output module 101 may be the first amplifier 10, for example, may be a Differential Sense Amplifier (DSA). Referring to fig. 9, the second output module 102 may be the second amplifier 20, for example, may be a Differential Sense Amplifier (DSA).

Referring to fig. 10, in some embodiments, further comprising: the first global complementary data line YIOF1, the first output module 101 is connected to the first global data line YIO1 and the first global complementary data line YIOF1, configured to: first data represented by the first global data line YIO and the first global complementary data line YIOF are received and output. The first global complementary data line YIOF and the first global data line YIO transmit signals that are opposite to each other, so that the data transmitted by the first global data line YIO and the first global complementary data line YIOF can be mutually referenced to improve the accuracy of the first data transmitted to the first output module 101.

In some embodiments, further comprising: and a second inverter circuit, responsive to the sense signal enable, having an input coupled to the first global data line YIO for receiving the first data in the first global data line YIO1 and an output coupled to the first global complement data line YIOF1.

In the data readout stage, the input terminal of the second inverter circuit receives the first data transmitted in the first global data line YIO, the output terminal of the second inverter circuit outputs the complementary first data to the first global complementary data line YIOF1, and the first global complementary data line YIOF1 outputs the complementary first data to the first output module 101, where the complementary first data and the first data are mutually inverted signals.

In some embodiments, the second inverter circuit may be a fourth inverter 7, where an input terminal of the fourth inverter 7 is connected to the first global data line YIO and an output terminal is connected to the first global complementary data line YIOF.

In some embodiments, the second inverter circuit may be disposed between the first memory block 1 and the first output module 101, that is, the complementary first data is generated before being input to the first output module 101, so as to reduce the transmission power consumption of the complementary first data and reduce the driving capability requirement of the second inverter circuit, and the lower the driving capability requirement is, the smaller the required size is; in other embodiments, the second inverting circuit may be disposed between the second output module and the first memory block, that is, the entire first global complementary data line YIOF of the first memory block 1 is used to transmit the complementary first data, and forms a reference with the first data, so that it is beneficial to avoid that the first data is interfered during transmission and cannot be effectively identified.

Referring to fig. 8, in some embodiments, further comprising: the second global complementary data line YIOF2, the second output module 102 connected to the second global data line YIO2 and the second global complementary data line YIOF2, is configured to: second data represented by the second global data line YIO and the second global complementary data line YIOF are received and output. The second global complementary data line YIOF and the second global data line YIO transmit signals that are opposite to each other, so that the data transmitted by the second global data line YIO and the second global complementary data line YIOF can be mutually referenced to improve the accuracy of the second data transmitted to the second output module 102.

Referring to fig. 11, in some embodiments, further comprising: the read driving module 105, the read driving module 105 is located between the first memory block 1 and the second memory block 2 and connected to the first global data line YIO and the second output module 102, and the read driving module 105 is configured to output read data in response to the read enable signal and the second output data, where the read data is transmitted to the first output module 101 through the first global data line YIO. The read driving module 105 is provided to enhance the signal strength of the transmitted second output data. The second output data is data output by the second output module 102 based on the second data.

Referring to fig. 12, in some embodiments, the read drive module 105 includes:

The third NAND gate 32, the two inputs of the third NAND gate 32 respectively receive the read enable signal ReadEn and the second output data, and in some embodiments, the read enable signal ReadEn may be a logic high signal, corresponding to a logic level of "1".

The third nor gate 31 has a first input terminal receiving the second output data, a second input terminal receiving the complementary read enable signal ReadEnF, and the complementary read enable signal ReadEnF and the read enable signal ReadEn being opposite signals.

The gate of the third PMOS MP3 is connected to the output end of the third nand gate 32, the drain of the third PMOS MP3 is connected to the first global data line YIO1, and the source of the third PMOS MP3 is connected to the high-level voltage VCC.

The gate of the third NMOS transistor MN3 is connected to the output end of the third nor gate 31, the drain of the third NMOS transistor MN3 is connected to the first global data line YIO1 and the drain of the third PMOS transistor MP3, and the source of the third NMOS transistor MN3 is connected to the low-level voltage VSS, for example, may be connected to the ground.

Referring to fig. 13, in some embodiments, further comprising: the verification module 106, the verification module 106 is connected with the first output module 101 and the first writing driving module 103; the verification module 106 receives the first output data output by the first output module 101 and the first verification data corresponding to the first output data, so as to correct the first output data based on the first verification data, and outputs corrected first correction data, wherein the first verification data is output by the first output module 101; the verification module 106 further receives the second output data output by the second output module 102 and the second verification data corresponding to the second output data through the first global data line YIO, so as to correct the second output data based on the second verification data, and outputs the verified second correction data; the first write data includes: the first raw input data and the first raw verification data, the first raw verification data being generated by the verification module 106 from the first raw input data.

In some embodiments, the second write data comprises: the second raw input data and second raw verification data, the second raw verification data being generated by the verification module 106 from the second raw input data.

Referring to fig. 2 and 13, in some embodiments, further comprising: the external data line Databus, the external data line Databus is connected between the data port DQ and the verification module 106, the first original input data and the second original input data can be transmitted from the data port DQ to the verification module 106 via the external data line Databus, and the verification module 106 generates the first original verification data corresponding to the first original input data and the second original verification data corresponding to the second original input data.

It should be noted that the external data line Databus in the embodiments of the present disclosure is only for distinguishing the same transmission line as the first global data line YIO1 and the second global data line YIO, and the "external" in the external data line Databus is an external data line with respect to the first global data line YIO1, the second global data line YIO and the memory cell block, not an external data line of the semiconductor memory.

In the process of storing the first original input data into the first storage block1 and the second original data into the second storage block2, the first original check data is stored together into the first storage block1, and the second original check data is stored together into the second storage block 2. That is, the first data includes first original input data and first original check data, and the second data includes second original input data and second original check data.

When the first data or the second data is read out, the first original input data and the first original check data are read out from the first storage block 1, the first original check data are checked by the check module 106 and corrected based on the first original check data, or the second original input data and the second original check data are read out from the second storage block 2, the second original check data are checked by the check module 106 and corrected based on the second original check data, so that the accuracy of the data output from the first storage block 1 and the second storage block 2 is ensured.

The check module 106 is located at a side of the first output module 101 far away from the first storage block 1, so that after the first output module 101 processes the first data, the output data is directly output to the check module 106 for correction, and compared with the case that the check module 106 is located between the first storage block 1 and the second storage block 2, the transmission distance of the first data across the first storage block 1 can be saved, and further the readout power consumption is saved.

In the technical solution of the signal processing circuit provided in the foregoing disclosure embodiment, the first output module 101 is disposed on a side of the first memory block 1 close to the data port DQ, the second output module 102 is disposed between the first memory block 1 and the second memory block 2, and the second output module 102 and the first output module 101 respectively receive the first data from the first memory block 1 and the second data from the second memory block 2. Because the first output module 101 is closer to the data port DQ, the transmission path of the output data outputted by the first output module 101 to the data port DQ is shorter, which saves the distance that the first data of the first memory block 1 need to cross the first memory block 1 after being outputted, not only reduces the transmission loss of the first data, but also saves the power consumption.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should be assessed accordingly to that of the appended claims.

Claims (11)

1. A signal processing circuit applied to a semiconductor memory for writing data and reading data, the semiconductor memory comprising a data port, a first memory block, and a second memory block arranged longitudinally, the signal processing circuit comprising:

the first output module is positioned on one side of the first storage block, which is close to the data port, of the second storage block, and is connected with a first global data line of the first storage block, and the first output module is used for receiving first data of the first storage block through the first global data line and outputting the first data to the data port;

the second output module is positioned between the first storage block and the second storage block, is connected in series between the first global data line and the second global data line of the second storage block, and is used for receiving second data of the second storage block through the second global data line and outputting the second data to a data port through the first global data line.

2. The signal processing circuit of claim 1, further comprising: the first write driving module comprises a first write driving unit which is connected with the first global data line and is used for responding to a first write enabling signal and data to be written to output write data, and the write data is transmitted to the first storage block through the first global data line or transmitted to the second storage block through the first global data line and the second global data line.

3. The signal processing circuit of claim 2, wherein the first memory block further comprises: a first global complementary data line, the first memory block receives the write data through the first global data line and the first global complementary data line; further comprises: and the first inverting circuit is used for responding to the enabling of a write signal, the input end of the first inverting circuit is connected with the first global data line and is used for receiving the first write data in the first global data line, and the output end of the first inverting circuit is connected with the first complementary global data line.

4. The signal processing circuit of claim 2, further comprising: the verification module is connected with the first output module and the first writing driving module; the verification module corrects the first output data based on the first verification data by receiving the first output data output by the first output module and the first verification data corresponding to the first output data, and outputs corrected first correction data, wherein the first verification data is output by the first output module; the verification module also receives second output data output by the second output module and second verification data corresponding to the second output data through the first global data line, so as to correct the second output data based on the second verification data and output verified second correction data; the first write data includes: the system comprises first original input data and first original check data, wherein the first original check data is generated by the check module according to the first original input data.

5. The signal processing circuit of claim 2, further comprising: the first global complementary data line is connected to the first memory block and the first write driving module, and the first write driving module further includes: and a second write driving unit for outputting complementary write data, which is transferred to the first memory block via the first global complementary data line, in response to the first write enable signal and complementary data to be written.

6. The signal processing circuit of claim 4, further comprising: the second write driving module is positioned between the first storage block and the second storage block, responds to a second write enabling signal and second data to be written to output second write data, and the second write data is transmitted to the second storage block through the second global data line; the second write data includes: the system comprises a verification module, a first original input data and first original verification data, wherein the first original verification data is generated by the verification module according to the first original input data.

7. The signal processing circuit of claim 6, wherein the second write driver module comprises two sub-write driver units, wherein,

The sub-write driving unit is used for receiving the second write enabling signal and the second data to be written, outputting the second write data, and transmitting the second write data to the second storage block through the second global data line; the other sub-write driving unit is used for receiving the second write enabling signal and complementary second data to be written and outputting complementary second write data, and the complementary second write data are transmitted to the second storage block through the second global complementary data line.

8. The signal processing circuit of claim 4, further comprising: the read driving module is located between the first storage block and the second storage block, connected to the first global data line and the second output module, and used for responding to a read enabling signal and the second output data to output read data, and the read data is transmitted to the first output module through the first global data line.

9. The signal processing circuit of claim 1, further comprising: a first global complementary data line, the first output module being connected to the first global data line and the first global complementary data line, configured to: and receiving and outputting first data represented by the first global data line and the first global complementary data line.

10. The signal processing circuit of claim 9, further comprising: and the second inverting circuit is used for responding to the reading signal enabling, the input end of the second inverting circuit is connected with the first global data line and is used for receiving the first data in the first global data line, and the output end of the second inverting circuit is connected with the first global complementary data line.

11. The signal processing circuit of claim 9, further comprising: a second global complementary data line, the second output module being connected to the second global data line and the second global complementary data line, configured to: and receiving and outputting the second data represented by the second global data line and the second global complementary data line.