RU2797927C1 - Read-write conversion circuit and memory - Google Patents

Abstract

FIELD: semiconductors.

SUBSTANCE: invention is used as a read-write and memory conversion circuit. The read-write conversion circuit also comprises a read amplifier, a local data line, a local complementary data line, a global data line and a global additional data line, and the read-write conversion module comprises a local read-write unit and a global read-write unit, wherein the read data path of the read-write conversion circuit passes from the bit line and the complementary bit line to the local data line and the local complementary data line through the read amplifier, then to the local read-write unit through the local data line and the local complementary data line, then to the global data line and the global complementary data line via the local read/write unit, and finally to the global read/write unit via the global data line and the global complementary data line.

EFFECT: speed of the read-write operation of the read-write conversion circuit is variable, so that the performance of the memory is improved.

10 cl, 7 dwg

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application refers to Chinese Patent Application No. 202010505672.3, filed June 5, 2020, entitled "Read-Write Conversion Circuit and Memory", and Chinese Patent Application No. 202021024456.9, filed June 5, 2020, entitled "Read -Write Conversion Circuit and Memory", the disclosures of which are incorporated herein by reference in their entirety.

FIELD OF TECHNOLOGY

[0002] Embodiments of the present invention relate to the technical field of semiconductors and, in particular, to the read-write conversion circuit and memory.

BACKGROUND OF THE INVENTION

[0003] Dynamic Random Access Memory (DRAM) is a semiconductor memory device that is widely used in computers and consists of many repeating memory cells. Each memory cell usually contains a capacitor and a transistor. The transistor includes a gate connected to the number line, a drain connected to the bit line, and a source connected to a capacitor. The voltage signal on the word line may turn on or off the transistor to read data information stored in the capacitor via the bit line or write data information to the storage capacitor via the bit line.

[0004] DRAM can be classified as Double Data Rate (DDR) DRAM, Graphics Double Data Rate (GDDR) DRAM, or Double Data Rate Low Power DRAM data (Low Power Double Data Rate (LPDDR) DRAM). With the increase in the number of applications of DRAM, for example, with the application of DRAM in the field of mobile communication, the demands of users on the speed of DRAM have increased.

[0005] However, there is still a need to improve the performance of prior art DRAMs.

DISCLOSURE OF THE INVENTION

[0006] According to embodiments of the present invention, a read-write and memory conversion scheme is provided as a solution to a technical problem. The read/write operation speed of the read/write conversion circuit is variable, so that memory performance is improved.

[0007] In order to solve the above problem, embodiments of the present invention provide a read-write conversion circuit, which is characterized in that said circuit comprises: a read-write conversion module performing a read-write operation in response to a read-write control signal; and a control module outputting a variable read/write control signal in response to the read/write speed configuration signal to control the speed of a read/write operation of the read/write conversion module to be variable.

[0008] In addition, a speed configuration module can also be included, which can be connected to the control module and configured to output a read-write speed configuration signal to the control module.

[0009] In addition, the read-write control signal may comprise a read control signal and a write control signal. The read-write conversion module may perform a read operation in response to the read control signal and perform a write operation in response to the write control signal. The speed configuration module may include a read speed configuration unit configured to output a read speed configuration signal in the read-write speed configuration signal to the control module, causing the read control module to output, in response to the read speed configuration signal, a speed control variable control signal. read operations so that it is a variable. The speed configuration module may also include a write speed configuration unit configured to output the write speed configuration signal in the read-write speed configuration signal to the control module to cause the control module to output, in response to the read speed configuration signal, a variable write control signal to control the speed of the write operation so that it is variable.

[0010] In addition, a local data line, a local complementary data line, and a global data line may also be included. During a read-write operation, data transmission between each of the local data line, the local complementary data line, and the global data line may be performed, during which the data signals of the local data line and the local complementary data line may be out of phase.

[0011] Further, the read-write conversion module may comprise a local read-write unit performing a local read-write operation in response to a local read-write control signal in the read-write control signal. The control module may include a local control unit outputting, in response to a local read/write speed configuration signal in the read/write speed configuration signal, a variable local read/write control signal to control the speed of a local read/write operation of the local read/write unit, thereby to be a variable.

[0012] In addition, the read-write conversion circuit may also include a local speed configuration module connected to the local control unit and configured to output the local read-write speed configuration signal to the local control unit.

[0013] In addition, the read-write conversion circuit may also include a read amplifier connected to the local read-write unit via a local data line and a local complementary data line and configured to sense the voltage of the bit line.

[0014] In addition, the same local read-write unit can be connected to a plurality of read amplifiers via a local data line and a local complementary data line.

[0015] In addition, the read data path may be from the local read-write unit to the read amplifier through the local data line and the local complementary data line, and then to the bit line through the read amplifier. The read data path may be from the bit line to the local data line and the local complementary data line through the read amplifier, and then to the local read-write unit through the local data line and the local complementary data line.

[0016] In addition, the read-write conversion module may comprise a global read-write unit that performs a global read-write operation in response to a global read-write control signal in the read-write control signal. The control module may comprise a global control module outputting, in response to the global read/write rate configuration signal in the read/write rate configuration signal, a variable global read/write control signal to control the rate of a global read/write operation of the global read/write unit, thus to be a variable.

[0017] In addition, the read-write conversion circuit may also include a global speed configuration module connected to the global control unit and configured to output the global read-write speed configuration signal to the global control unit.

[0018] In addition, the local read-write unit may include a local amplifier connected between the local data line and the local complementary data line and configured to amplify the local data line data and the local complementary data line data.

[0019] In addition, the local amplifier may include a first phase inverter, in which the first input of the first phase inverter is electrically connected to the local data line, and the first output of the first phase inverter is electrically connected to the local complementary data line; and a second phase inverter, in which the second input of the second phase inverter is electrically connected to the first output of the first phase inverter and a local complementary data line, and the second output of the second phase inverter is electrically connected to the first input of the first phase inverter and the local data line.

[0020] Further, the first phase inverter may comprise a first p-channel metal-oxide-semiconductor (pMOS) transistor and a first n-channel metal-oxide-semiconductor (nMOS) transistor. The gate of the first pMOS transistor may be connected to the gate of the first nMOS transistor to serve as the first input of the first phase inverter, the source of the first pMOS transistor may be connected to the operating power, and the drain of the first pMOS transistor may be connected to the drain of the first nMOS transistor, to serve as the first output of the first phase inverter. The second phase inverter may include a zero pMOS transistor and a zero nMOS transistor. The gate of the zero pMOS transistor may be connected to the gate of the zero nMOS transistor to serve as the second input of the second phase inverter. The source of the zero pMOS transistor can be connected to the operating power, and the drain of the zero pMOS transistor can be connected to the drain of the zero nMOS transistor to serve as the second output of the second phase inverter.

[0021] In addition, the local read-write unit may comprise a local read conversion circuit configured to transfer the data of the local data line and the local complementary data line to the global data line in response to the local read control signal in the local read-write control signal. The local read conversion circuit may include a third nMOS transistor and a fourth nMOS transistor. The drain of the third nMOS transistor may be connected to the global data line, the gate of the third nMOS transistor may be connected to the local complementary data line, and the source of the third nMOS transistor may be connected to the drain of the fourth nMOS transistor. The gate of the fourth nMOS transistor may receive a local read signal in a local read control signal, while the source may be grounded.

[0022] In addition, the read-write conversion circuit may also comprise a global complementary data line, wherein the data signals of the global complementary data line and the global data line may be out of phase during a read operation. The local read conversion circuit may also include an eighth nMOS transistor and a ninth nMOS transistor. The drain of the eighth nMOS transistor may be connected to the global complementary data line, the gate of the eighth nMOS transistor may be connected to the local data line, and the source of the eighth nMOS transistor may be connected to the drain of the ninth nMOS transistor. The gate of the ninth nMOS transistor can receive a local read signal while the source can be grounded.

[0023] Further, the local read/write unit may comprise a local write conversion circuit configured to transfer global data line data to the local data line and the local complementary data line in response to the local write control signal in the local read/write control signal. The local write conversion circuit may include a fifth nMOS transistor, a sixth nMOS transistor, and a seventh nMOS transistor. The drain of the fifth nMOS transistor may be connected to the local complementary data line, the gate of the fifth nMOS transistor may be connected to the source of the seventh nMOS transistor, and the source of the fifth nMOS transistor may be connected to the drain of the sixth nMOS transistor. The gate of the sixth nMOS transistor may receive a local write signal in the local write control signal, while the source may be grounded. The drain of the seventh nMOS transistor may be connected to a local data line, while the gate may receive a local write signal.

[0024] In addition, the read-write conversion circuit may also comprise a global complementary data line, wherein the data signals of the global complementary data line and the global data line may be out of phase during a read-write operation. The local write conversion circuit may also include a tenth nMOS transistor, an eleventh nMOS transistor, and a twelfth nMOS transistor. The drain of the tenth nMOS transistor may be connected to the local data line, the gate of the tenth nMOS transistor may be connected to the source of the twelfth nMOS transistor and the global complementary line, and the source of the tenth nMOS transistor may be connected to the drain of the eleventh nMOS transistor. The gate of the eleventh nMOS transistor can receive a local write signal, while the source can be grounded. The drain of the twelfth nMOS transistor may be connected to a local complementary data line, while the gate may receive a local write signal.

[0025] In addition, the local read-write unit may also include a pre-charge circuit connected between the local data line and the local complementary data line and configured to pre-charge the local data line and the local complementary data line in response to the pre-charge control signal.

[0026] In addition, the pre-charge circuit may include a third pMOS transistor, a fourth pMOS transistor, and a fifth pMOS transistor. The gate of the third pMOS transistor, the gate of the fourth pMOS transistor, and the gate of the fifth pMOS transistor can receive a pre-charge control signal. The source of the third pMOS transistor and the source of the fourth pMOS transistor may be connected to the operating power. The drain of the third pMOS transistor may be electrically connected to the local data line. The drain of the fourth pMOS transistor may be electrically connected to the local complementary data line. The fifth pMOS transistor may be electrically connected to the local data line and the local complementary data line in response to the precharge control signal.

[0027] Accordingly, according to embodiments of the present invention, a memory is also provided that may include the aforementioned read-write conversion circuit.

[0028] Compared with the prior art, the technical solutions proposed in these embodiments of the present invention have the following advantages.

[0029] According to embodiments of the present invention, a highly structured read-write conversion circuit is provided, which includes a read-write conversion module that performs a read-write operation in response to a read-write control signal, and a control module that outputs variable read-write control signal in response to the read-write speed configuration signal, so that the speed of the read-write operation of the read-write conversion module remains variable. Since the read-write control signal output by the control module is variable, the speed of the read-write operation performed by the read-write conversion module after receiving the variable read-write control signal is also variable, and therefore the speed of the read-write operation of the read-write conversion circuit can be configured. Compared with the prior art in which the speed of the read/write operation of the read/write conversion circuit is fixed, the read/write conversion scheme provided by the embodiments of the present invention allows the speed of the read/write operation to be adjusted according to practical needs, so that this the read-write conversion scheme can be applied more widely, for example, not only to a low-speed read-write operation, but also to a high-speed read-write operation. In addition, with the adoption of the read-write conversion scheme proposed according to the embodiments of the present invention, the high-speed read-write operation when it is not needed can be adjusted to the low-speed read-write operation, thereby solving the problem of high power consumption caused by the high-speed operation. . Therefore, the performance of the read-write scheme proposed according to the embodiments of the present invention can be improved.

[0030] In addition, the read-write conversion module comprises a local read-write unit, and the control module comprises a local control module outputting a variable local read-write control signal in response to the local read-write speed configuration signal in the read-speed configuration signal- writes, so that the speed of a local read-write operation of the local read-write block remains variable. Therefore, the speed of the local read-write operation of the read-write conversion scheme proposed according to the embodiments of the present invention can be configured.

[0031] In addition, the read-write conversion module comprises a global read-write block, and the control module comprises a global control block outputting a variable global read-write control signal in response to the local read-write speed configuration signal in the read-write speed configuration signal - writes, so that the rate of the global read-write operation of the global read-write block remains variable. Therefore, the speed of the global read-write operation of the read-write conversion scheme proposed according to the embodiments of the present invention can be configured.

[0032] In addition, the local read-write unit includes a local amplifier connected between the local data line and the local complementary data line and configured to amplify the local data line data and the local complementary data line data. The local amplifier helps to speed up the discrimination between the local data line and the local complementary data line, and helps not only to increase the speed of the local read-write operation, but also to reduce the driving requirements of the local data line and the local complementary data line to the sense amplifier, which simplifies the design. readout amplifiers.

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG. 1 is a schematic diagram for a read-write conversion circuit according to an embodiment of the present invention.

[0034] FIG. 2 is a schematic diagram for a read-write conversion circuit in accordance with yet another embodiment of the present invention.

[0035] FIG. 3 is another schematic diagram for a read-write conversion circuit in accordance with yet another embodiment of the present invention.

[0036] FIG. 4 is a sequence diagram of a read-write control signal corresponding to a high-speed write operation and a low-speed write operation in a write operation of a read-write conversion circuit according to another embodiment of the present invention.

[0037] FIG. 5 is a sequence diagram of a read-write control signal corresponding to a high-speed read operation and a low-speed read operation in a read operation of a read-write conversion circuit according to another embodiment of the present invention.

[0038] FIG. 6 is a schematic diagram of a local read-write circuit structure in a read-write conversion circuit according to another embodiment of the present invention.

[0039] FIG. 7 is a schematic diagram of another local read/write block circuit structure in a read/write conversion circuit according to another embodiment of the present invention.

IMPLEMENTATION OF THE INVENTION

[0040] In an exemplary implementation for the same DRAM, the speed (including read speed and write speed) of a read-write operation is fixed. Because the read/write speed of the DRAM is fixed, if the DRAM is designed for a low read/write speed, it is difficult to require the DRAM to have a high read/write speed at some times. On the other hand, if the DRAM is designed for a fixed high read/write speed, then during times when the DRAM has low read/write speeds, the fixed high read/write speed of the DRAM will lead to a power consumption problem. Those. Currently, the memory is facing the problem of fixed read/write speed and high power consumption.

[0041] In order to solve the above problem, according to embodiments of the present invention, a read-write conversion circuit is provided that includes a read-write conversion module and a control module. The control module outputs, in response to the read/write speed configuration signal, a variable read/write control signal to control the speed of the read/write operation of the read/write conversion module to be variable. Thus, in accordance with embodiments of the present invention, the read/write operation speed can be configured to adjust the read/write speed of the read/write conversion circuit to the expected speed, avoiding unnecessary power consumption of the read/write conversion circuit, and improving the performance of the circuit. read-write transformations.

[0042] In order to make the objectives, technical solutions and advantages of the embodiments of the present invention more clear, each embodiment of the invention will be described in detail below in conjunction with the drawings. However, those skilled in the art may note that, in each embodiment of the present invention, numerous technical details are provided in order for readers to better understand the invention. However, the technical details claimed in the invention can also be implemented even without these technical details, variations and modifications, as explained in each of the following implementation options.

[0043] FIG. 1 is a schematic diagram for a read-write conversion circuit according to an embodiment of the present invention.

[0044] With reference to FIG. 1, in this embodiment, the read-write conversion circuit includes: a read-write conversion unit 101 performing a read-write operation in response to a read-write control signal; and a control unit 102 outputting, in response to the read/write speed configuration signal, a variable read/write control signal for controlling the read/write operation speed of the read/write conversion unit 101 to be variable.

[0045] The read-write conversion scheme proposed according to this embodiment will be described in detail below in conjunction with the drawings.

[0046] In this embodiment, the read-write mapping scheme may also comprise a local data line Ldat, a local complementary data line Ldat#, and a global data line Gdat. During the read-write operation, data is transmitted between each of the local data line Ldat, the local complementary data line Ldat#, and the global data line Gdat, the data signal of the local data line Ldat and the data signal of the local complementary data line Ldat# are opposite in phase.

[0047] In this embodiment, the data signals read or written by the read-write conversion circuit are paired. Each pair of data signals contains two pieces of data. During a read/write operation, one of the two pieces of data is a high level signal, while the other piece of data is a low level signal. Thus, the read-write conversion circuit comprises at least one pair of local data line Ldat and local complementary line Ldat#, and the two pieces of data are local data line data Ldat and local complementary data line data Ldat#, respectively. Specifically, during a read operation of the read-write conversion scheme, data is transferred from the local data line Ldat and the local complementary data line Ldat# to the global data line Gdat; and during the write operation of the read-write conversion circuit, data is transferred from the global data line Gdat to the local data line Ldat and the local complementary data line Ldat#.

[0048] The local data line Ldat is also called the local data line, the local complementary data line Ldat# is also called the local complementary data line, and the global data line Gdat is also called the global data line.

[0049] In this embodiment, for the global data line Gdat, the read-write conversion schemes use a one-way transmission method, namely, in the read-write conversion scheme, there is no global additional line that is complementary to the global data line Gdat in data signal phase.

[0050] It should be noted that in yet another implementation for the global data line of the read-write conversion scheme, a two-way transfer method can also be used, namely: the write conversion scheme may also contain a global complementary write line, and during the read-write operation the data signal of the global complementary data line and the data signal of the global data line are opposite in phase.

[0051] In a particular implementation, a read-write conversion scheme is applied to the memory. The memory includes a column selector 100 and a plurality of memory cells. The local data line Ldat is connected to the bit line BL by the column select unit 100, and the local complementary data line Ldat# is connected to the complementary bit line BL# by the column select unit 100. The memory location for a read operation or a write operation is selected by the column selection module 100 . Accordingly, signals are transmitted between the bit line BL connected to the selected memory cell and the local data line Ldat, and signals are transmitted between the complementary bit line BL# connected to the selected memory cell and the local complementary data line Ldat#.

[0052] During the read operation, the read-write conversion module 101 transmits the data of the local data line Ldat and the data of the local complementary data line Ldat# to the global data line Gdat; and during the write operation, the read-write conversion unit 101 transfers data from the global data line Gdat to the local data line Ldat and the local complementary data line Ldat#.

[0053] The read-write control signal comprises a column select signal, a local read-write control signal, and a global read-write control signal. The local read-write control signal is configured to control the read-write conversion unit 101 to perform a local read-write operation. The global read-write control signal is configured to control the read-write conversion unit 101 to perform a global read-write operation.

[0054] The speed of the read-write control signal affects the speed of the read-write operation of the read-write conversion circuit. For example, if the speed of the read/write control signal is higher, then the speed of the read/write operation is correspondingly faster, and if the speed of the read/write control signal is lower, then the speed of the read/write operation is correspondingly slower.

[0055] The read-write control signal is provided by the control module 102, and the read-write control signal output by the control module 102 is variable, in particular, the rate of the read-write control signal is variable. The read/write speed configuration signal is related to the expected speed of a read/write operation. When the speed of the read/write operation is not as expected, the read/write control signal output by the control unit 102 changes. Those. the speed of the read-write control signal is changed, thereby changing the speed of the read-write operation performed by the read-write conversion unit 101 in response to the changed read-write control signal, so that the read-write speed of the read-write operation matches the expected speed.

[0056] In a specific implementation, when the speed of the read-write operation performed by the read-write conversion module 101 in response to the first read-write control signal is lower than the expected speed, the control module 102 outputs the second read-write control signal in response to the signal configuring read-write to increase the speed of the read-write operation of the module 101 conversion read-write to the expected speed. When the speed of the read/write operation performed by the read/write conversion unit 101 in response to the third read/write control signal is higher than the expected speed, the control unit 102 outputs the fourth read/write control signal in response to the read/write configuration signal to reduce the speed. read-write operations of the read-write conversion module 101 up to the expected speed.

[0057] Since the read-write operation speed of the read-write conversion unit 101 is variable, the read-write operation speed of the read-write conversion unit 101 can be adjusted according to practical performance requirements. For example, increasing or decreasing the data transfer rate in a read/write operation can be used to meet read/write performance requirements as well as reduce unnecessary power consumption.

[0058] In this embodiment, the read-write conversion circuit may also include a speed configuration module 103 connected to the control module 102 and configured to output a read-write speed configuration signal to the control module 102. Thus, the write speed configuration unit 103 is embedded in the read-write conversion circuit to help reduce the length of the transmission path for transmitting the read-write speed configuration signal to the control unit 102 and speed up the response speed of the control unit 102 to output the corrected read-write control signal more timely. in order to quickly achieve a change in the speed of the read-write operation of the read-write conversion unit 101 .

[0059] The read-write control signal comprises a read control signal and a write control signal. The read-write conversion unit 101 performs a read operation in response to the read control signal and performs a write operation in response to the write control signal. In this embodiment, the control unit 102 outputs, in response to the read-write speed configuration signal, a variable read control signal to control the read operation speed of the write conversion unit 101 to be variable. The control unit 102 outputs, in response to the read/write speed configuration signal, a variable write control signal to control the speed of the write operation of the read/write conversion unit 101 to be variable.

[0060] Accordingly, the read-write speed configuration signal comprises a read speed configuration signal and a write speed configuration signal. The speed configuration unit 103 includes: a read speed configuration unit 113, configured to output a read speed configuration signal in the read-write speed configuration signal to the control unit 102, which then outputs a variable read control signal in response to the read speed configuration signal to control the operation speed. reading in such a way that it is a variable; a write speed configuration unit 123, configured to output the write speed configuration signal in the read/write speed configuration signal to the control unit 102, which then, in response to the write speed configuration signal, outputs a variable write control signal to control the speed of the write operation so that it was a variable

[0061] It should be noted that the rate configuration module may also include a local rate configuration module and a global rate configuration module. The local rate configuration module is configured to output the local read rate configuration signal to the control module to control the rate of the local read/write operation of the read/write conversion module to be variable. The global speed configuration module is configured to output the global read/write speed configuration signal to the control module to control the speed of the global read/write operation of the read/write conversion module to be variable.

[0062] It should also be noted that, in another embodiment, the rate configuration module may also be provided with a circuit other than the read-write conversion circuit.

[0063] According to the read-write conversion scheme shown in this embodiment, the control unit 102 outputs a variable read-write control signal to make the read-write operation speed of the read-write conversion unit 101 variable. This allows the read-write conversion scheme to be applied to more scenarios, for example, to apply not only to a high-speed read-write operation, but also to a low-speed read-write operation. In addition, it solves the problem of high power consumption caused by a long stay in a state of high-speed read/write operation.

[0064] In yet another embodiment of the present invention, a read-write conversion scheme is also provided. This read-write mapping scheme is essentially the same as the read-write mapping scheme proposed in the previous implementation. The difference is that in this implementation, the read-write conversion module and the control module are described in more detail. The read-write conversion scheme proposed according to this embodiment will be described in detail below in conjunction with the drawings. For a description of details that match or correspond to those of the previous embodiment, see the detailed descriptions in the previous embodiment.

[0065] FIG. 2 shows a read-write conversion circuit in accordance with yet another embodiment of the present invention.

[0066] With reference to FIG. 2, the read-write conversion circuit comprises a local data line Ldat, a local complementary data line Ldat#, a global data line Gdat, a global complementary data line Gdat#, a read-write conversion unit 201, and a control unit 202. The read-write conversion unit 201 performs a read-write operation in response to the read-write control signal to realize data communication between each of the local data line Ldat and the local complementary data line Ldat# and each of the global line Gdat and the global complementary line Gdat# data. During the read-write operation, the data signals of the local data line Ldat and the local complementary data line Ldat# are opposite in phase, and the data signals of the global data line Gdat and the global complementary data line Gdat# are opposite in phase.

[0067] It should be noted that in yet another embodiment, the read-write conversion scheme may not provide a global complementary data line, or only provide a global data line. See the previous implementation for details.

[0068] In this embodiment, the read-write conversion module 201 includes a local read-write unit 211 that performs a local read-write operation in response to a local read-write control signal in the read-write control signal. The local read-write control signal comprises a local read signal Rd and a local gain enable signal.

[0069] Accordingly, the control unit 202 includes a local control unit 212 outputting, in response to a local read-write speed configuration signal in the read-write speed configuration signal, a variable local read-write control signal to control the speed of a local read-write operation in local block 211 read-write so that it is a variable.

[0070] Thus, the speed of the local read-write operation in the read-write conversion scheme is variable. In particular, the speed of the local read operation in the local read/write operation is variable, and the speed of the local write operation in the local read/write operation is also variable. For example, a local read operation may be changed from a high speed read to a low speed read, or changed from a low speed read to a high speed read. The local write operation can be changed from high speed recording to low speed recording, or changed from low speed recording to high speed recording. Since the speed of the local read/write operation is variable, the speed of the local read/write operation can be adjusted as practical to meet the data transfer rate requirement and, at the same time, to take advantage of the low power consumption of the read/write conversion circuit.

[0071] In this embodiment, the read-write conversion circuit may also include a local rate configuration module 213 connected to the local control module 212 and configured to output the local read-write rate configuration signal to the local control module 212 to make the local signal adjustable. read-write control output by the local control unit 212 .

[0072] It should be noted that in yet another implementation, the local read/write rate configuration signal may also be provided to the local external circuit control unit, i.e., the read/write conversion circuit does not need a local rate configuration module.

[0073] The read-write conversion circuit may also include a read amplifier 214. The sense amplifier 214 is connected to the local read/write unit 211 via the local data line Ldat and the local complementary data line Ldat#, and is configured to read the voltages of the bit line BL and the complementary bit line BL#.

[0074] The bit line BL is connected to the local data line Ldat through a sense amplifier 214, and the complementary bit line BL# is connected to the local complementary data line Ldat# through the same sense amplifier 214.

[0075] In this embodiment, the sense amplifier 214 receives the column select signal CSL. The sense amplifier 214 includes two nMOS transistors (not marked), and the gates of the nMOS transistors receive the column select signal CSL. One nMOS transistor is connected to bit line BL and local data line Ldat in response to column select signal CSL, while the other nMOS transistor is connected to complementary bit line BL# and local complementary data line Ldat# in response to column select signal CSL. Specifically, when the nMOS transistor receives the column select signal CSL and turns on, the bit line BL is connected to the local data line Ldat, and the complementary bit line BL# is connected to the local complementary data line Ldat#. When the nMOS transistor stops receiving the column select signal CSL, the bit line BL is disconnected from the local data line Ldat, and the complementary bit line BL# is disconnected from the local complementary data line Ldat#.

[0076] It is understood that in another implementation, the sense amplifier may comprise any number of transistors, such as a plurality of nMOS transistors and/or a plurality of pMOS transistors. As a sense amplifier, any device capable of implementing the function of a sense amplifier can be used.

[0077] The bit line BL is connected to a storage transistor (not marked). The gate of the storage transistor is connected to the number line WL. One end of the storage transistor is connected to the bit line BL, while the other end is connected to the voltage Vplate through a capacitor (not marked). The complementary bit line BL# is connected to the control transistor (not marked). One terminal of the control transistor is connected to the complementary bit line BL# while the other terminal is connected to the voltage Vplate.

[0078] In addition, the same local read-write unit 211 may be connected to a plurality of read amplifiers 214 via a local data line Ldat and a local complementary data line Ldat#. For ease of illustration and description, FIG. 2, only one sense amplifier 214 is shown.

[0079] In this embodiment, a read-write conversion scheme is applied to the memory. The write data path extends from the local read-write block 211 to the read amplifier through the local data line Ldat and through the local complementary data line Ldat#, and then to the bit line BL and the complementary bit line BL# through the read amplifier 214. The read data path extends from the bit line to the local data line Ldat and the local complementary data line Ldat# through the read amplifier 214 and then to the local read/write unit 211 via the local data line Ldat and the local complementary data line Ldat#.

[0080] In this embodiment, the read-write conversion module 201 also includes a global read-write block 221 that performs a global read-write operation in response to a global read-write control signal in the read-write control signal.

[0081] The control unit 202 includes a global control unit 222 outputting, in response to a local read-write speed configuration signal in the read-write speed configuration signal, a variable global read-write control signal to maintain a variable speed of the global read-write operation in global block 221 read-write. Thus, the speed of the global read-write operation in the read-write conversion scheme is variable. In particular, the rate of a global read operation in a global read/write operation is variable, and the rate of a global write operation in a global read/write operation is variable.

[0082] i.e. in this embodiment, the variable is not only the speed of the local read/write operation, but also the speed of the global read/write operation.

[0083] It should be noted that in another embodiment, the control module may contain only one of the local control unit or the global control unit, and, accordingly, the variable is only the speed of the local read-write operation or the variable is only the speed of the global read-write operation .

[0084] Accordingly, the read-write conversion circuit may also comprise a global rate configuration module 223 coupled to the global control unit 222 and configured to output the global read-write rate configuration signal to the global control unit 222.

[0085] Local module 213 rate configuration and global module 223 rate configuration can be built into one module 203 rate configuration. The speed configuration unit 203 is configured to output the local read/write speed configuration signal to the local control unit 212, and is also configured to output the global read/write speed configuration signal to the global control unit 222.

[0086] It is understood that in another implementation, the global read/write rate configuration signal may also be provided to the global external circuit control block, i. e. the read-write conversion scheme does not need a global speed configuration module.

[0087] FIG. 3 shows another read-write conversion scheme according to another implementation. With reference to FIG. 3, in yet another example, the read-write conversion circuit may also include a read speed configuration unit 243 configured to output the read speed configuration signal in the read/write speed configuration signal to the local control unit 212 and the global control unit 222. This causes the local control unit 212 to output, in response to the read speed configuration signal, a variable local read control signal to control the speed of the local read operation so that it is variable. In addition, this causes the global control block 222 to output, in response to the read rate configuration signal, a variable global read control signal to control the rate of the global read operation so that it is variable. The read/write conversion circuit may also include a write speed configuration unit 253 configured to output the write speed configuration signal in the read/write speed configuration signal to the local control unit 212 and a global control unit 222 causing the local control unit 212 to output a variable write control signal. in response to the write speed configuration signal to control the speed of the local write operation so that it is variable. This causes the global control block 222 to output, in response to the write speed configuration signal, a variable global write control signal to control the speed of the global write operation so that it is variable. The read speed configuration unit 243 and the write speed configuration unit 253 may be built into one speed configuration unit 203 . Descriptions of the rate configuration unit 203 are given in the above embodiment.

[0088] In the case of a read-write conversion scheme with a global read-write block 221, the write data path passes to the global data line Gdat and the global complementary data line Gdat# via the global read-write block 221, then to the global read-write block 211 via the global data line Gdat and the global complementary data line Gdat#, from the local read/write unit 211 to the read amplifier 214 through the local data line Ldat and the local complementary data line Ldat#, and then to the bit line BL and the complementary bit line BL# through the amplifier 214 readings.

[0089] In the case of a read-write conversion scheme with a global read-write unit 221, the read data path extends from the bit line BL and the complementary bit line BL# to the local data line Ldat and the local complementary data line Ldat# through the read amplifier 214, then to to the local read-write block 211 via the local data line Ldat and the local complementary data line Ldat#, then to the global data line Gdat and the global complementary data line Gdat# via the local read-write block 211, and finally to the global read-write block 221 via the global data line Gdat and the global complementary data line Gdat#.

[0090] With reference to FIG. 2 and FIG. 3, in this embodiment, the local read/write unit 211 comprises a local read conversion circuit 2111 that is configured to transmit the data of the local data line Ldat and the local complementary data line Ldat# to the global data line Gdat and the global complementary data line Gdat# in response. to the local read signal in the local read-write signal.

[0091] The control unit 202 outputs a local read control signal and a variable local read control signal in response to the read-write speed configuration signal to correct the read speed of the local read conversion circuit 2111, making the local read operation speed of the read-write conversion unit 201 variable.

[0092] The local read/write unit 211 also includes a local write conversion circuit 2112 configured to transfer the data of the global data line Gdat and the global complementary data line Gdat# to the local data line Ldat and the local complementary data line Ldat# in response to the local signal. writes in the local read-write signal.

[0093] The control unit 202 outputs a local write control signal, and the control unit 202 outputs a variable local write control signal in response to the read-write speed configuration signal to correct the write speed of the local write conversion circuit 2112 to also make the local write operation speed of the unit 201 variable. read-write transformations.

[0094] The read-write unit 211 also includes a local amplifier 2113 connected between the local data line Ldat and the local complementary data line Ldat# and configured to amplify the data of the local data line Ldat and the data of the local complementary data line Ldat#.

[0095] The control unit 202 outputs a variable local read control signal or a local write control signal to make the amplification rate of the local amplifier 2113 variable, so that the speeds of the local read operation and the local write operation of the read-write conversion unit 201 can be changed to a certain extent.

[0096] The local amplifier 2113 forms a circuit for amplifying the local data line Ldat signal and the local complementary data line Ldat# signal, and helps speed up discrimination between the level of the local data line Ldat and the level of the local complementary data line Ldat#, thereby increasing the transmission rate of the data signal and improving read/write speed. In addition, since the data signals of the local data line Ldat and the local complementary data line Ldat# are amplified, the local data line Ldat and the local complementary data line Ldat# have reduced drive capability requirements of the memory sense amplifier. Thus, even if the area of the sense amplifier is gradually reduced, the sense amplifier has sufficient drive capability so that the local data line Ldat and the local complementary data line Ldat# satisfy device miniaturization trends while maintaining high electrical performance of the read-write conversion circuit, thereby improving storage efficiency of the memory containing the read-write conversion circuit.

[0097] The global read-write block 221 includes a read amplifier 2211, a pre-charge block 2212, and a write drive block 2213. The sense amplifier 2211 may amplify the data signal of the global data line Gdat and the data signal of the global complementary data line Gdat#. The precharger 2212 may precharge the global data line Gdat and the global complementary data line Gdat#.

[0098] The control unit 202 outputs a variable global read control signal to correct the speed of the global read operation or the global write operation of the global read-write block 221 so that the correction of the amplification speed of the read amplifier 2211, the precharge speed of the precharge block 2212, and the drive speed of the block 2213 the excitation of the write has achieved the purpose of changing the global read-write operation of the read-write conversion module 201 .

[0099] With reference to FIG. 2, in this embodiment, the read-write conversion circuit may also include a pre-charge circuit 204. The precharge circuit 204 is connected between the local data line Ldat and the local complementary data line Ldat#, and is configured to precharge the local data line Ldat and the local complementary data line Ldat# in response to the precharge control signal.

[00100] FIG. 4 is a sequence diagram of a read-write control signal corresponding to a high-speed write operation and a low-speed write operation in the write operation of the read-write conversion circuit according to this embodiment. FIG. 5 is a sequence diagram of a read/write control signal corresponding to a high-speed read operation and a low-speed read operation in a read operation of the read/write conversion circuit according to this embodiment. FIG. 4 and FIG. 5 also shows a bit line/complementary bit line (BL/BL#) signal, a global data line/global complementary data line (Gdat/Gdat#) signal, and a local data line/local complementary data line (Ldat/Ldat#) signal. It is clear that high speed and low speed are relative.

[00101] With reference to FIG. 4, when a write operation is performed, the read-write control signal comprises a global write control signal, a column select signal CSL, a local write signal Wr, and a local gain enable signal. It is understood that when performing a low-speed write operation, the local gain resolution level may be 0, and thus the low-speed write operation corresponds to a sequence diagram in which the local gain resolution is not shown.

[00102] From FIG. 4, it is easy to see that when a high-speed write operation is changed to a low-speed write operation, the speed of the read-write control signal is reduced, the data rates of the global data line Gdat and the global complementary data line Gdat# are reduced, and the data rates of the local data line Ldat and the local complementary the data lines Ldat# are reduced, and when the low-speed write operation is changed to the high-speed write operation, the speed of the read-write control signal is increased, the data rates of the global data line Gdat and the global complementary data line Gdat# are increased, and the data rates of the local data line Ldat and local complementary Ldat# data lines are incremented.

[00103] In addition, in FIG. 4 only shows the sequence diagram of each read-write control signal during one clock period. Based on the entire clock period, when a low-speed write operation is changed to a high-speed write operation, the speed of the write control signal in the corresponding read-write control signal increases, and when the high-speed write operation is changed to a low-speed write operation, the speed of the write control signal in the corresponding control signal read-write decreases.

[00104] With reference to FIG. 5, when a read operation is performed, the read-write control signal comprises a column select signal CSL, a local read signal Rd, a global gain enable, a global precharge signal, and a local gain enable. It is understood that when performing a low-speed read operation, the local gain resolution level may be 0, and thus the low-speed read operation corresponds to a sequence diagram that does not show the local gain resolution. From FIG. 5, it is easy to see that: when a high-speed read operation is changed to a low-speed read operation, the speed of the read-write control signal is reduced, the data rates of the local data line Ldat and the local complementary data line Ldat# are reduced, and the data rates of the global data line Gdat and the local complementary data lines Gdat# decrease; and when the low-speed read operation is changed to the high-speed read operation, the speed of the read-write control signal is increased, the data rates of the local data line Ldat and the global complementary data line Ldat# are increased, and the data rates of the global data line Gdat and the global complementary data line Gdat# increase.

[00105] FIG. 5 only shows the sequence diagram of each read-write control signal during one clock period. Based on the entire clock period, when a low-speed read operation is changed to a high-speed read operation, the speed of the read control signal in the corresponding read-write control signal increases, and when the high-speed read operation is changed to a low-speed read operation, the speed of the read control signal in the corresponding control signal read-write decreases.

[00106] It should be noted that in FIG. 4 and FIG. 5 shows only some of the general control signals that affect the speed of a read/write operation, and in practical circuits, in accordance with other circuit designs, there may be other read/write control signals that affect the speed of a read/write operation.

[00107] In particular, the circuit structure of the local read-write unit in the read-write conversion circuit proposed in this embodiment will be described below in conjunction with the drawings.

[00108] FIG. 6 is a schematic diagram of the local read-write block circuit structure in the read-write conversion circuit according to this embodiment. FIG. 7 is a schematic diagram of another local read/write block circuit structure in the read/write conversion circuit according to this embodiment.

[00109] With reference to FIG. 6, for the global data line Gdat, a one-way transmission method is used, i. e. the read-write conversion scheme does not contain a global complementary data line. The local read/write unit 211 includes a local read conversion circuit 2111 configured to transfer the data of the local data line Ldat and the local complementary data line Ldat# to the global line Gdat in response to a local read control signal in the local read/write control signal.

[00110] In this embodiment, the local read conversion circuit 2111 comprises a third nMOS transistor MN3 and a fourth nMOS transistor MN4. The drain of the third nMOS MN3 is connected to the global data line Gdat, the gate of the third nMOS MN3 is connected to the local complementary data line Ldat#, and the source of the third nMOS MN3 is connected to the drain of the fourth nMOS MN4. The gate of the fourth nMOS transistor MN4 receives the local read signal Rd in the local read control signal while the source is grounded.

[00111] It is understood that the local schema 2111 may also be another suitable mapped schema. For example, the gate of the fourth nMOS transistor is connected to the local complementary data line, and the gate of the third nMOS transistor receives the local read signal.

[00112] In another example, with reference to FIG. 7, for the global data line Gdat, a two-way transmission method can also be used, namely: the read-write conversion circuit contains a global data line Gdat and a global complementary data line Gdat#. During a read operation, the data signals of the global complementary data line Gdat# and the global data line Gdat are opposite in phase. Accordingly, in addition to the aforementioned third nMOS transistor MN3 and the fourth nMOS transistor MN4, the local read conversion circuit 2111 also includes an eighth nMOS transistor MN8 and a ninth nMOS transistor MN9. The drain of the eighth nMOS transistor MN8 is connected to the global complementary data line Gdat#, the gate of the ninth nMOS transistor MN8 is connected to the local data line Ldat, and the source of the eighth nMOS transistor MN8 is connected to the drain of the ninth nMOS transistor MN9. The gate of the ninth nMOS transistor MN9 receives the local read signal Rd while the source is grounded.

[00113] The local read/write unit 211 includes a local write conversion circuit 2112 configured to transfer data from the global data line Gdat to the local data line Ldat and the local complementary data line Ldat# in response to the local write signal in the local read/write signal.

[00114] In this embodiment, the local write conversion circuit 2112 comprises a fifth nMOS transistor MN5, a sixth nMOS transistor MN6, and a seventh nMOS transistor MN7. The drain of the fifth nMOS transistor MN5 is connected to the local complementary data line Ldat#, the gate of the fifth nMOS transistor MN5 is connected to the source of the seventh nMOS transistor MN7, and the source of the fifth nMOS transistor MN5 is connected to the drain of the sixth nMOS transistor MN6. The gate of the sixth nMOS transistor MN6 receives the local write signal Wr in the local read control signal while the source is grounded. The drain of the seventh nMOS transistor MN7 is connected to the local data line Ldat, while the gate receives the local write signal Wr.

[00115] In another example, with reference to FIG. 7, the read-write conversion circuit 211 also contains a global complementary data line Gdat#. During a read operation, the data signals of the global complementary data line Gdat# and the global data line Gdat are opposite in phase. In addition to the aforementioned fifth nMOS transistor MN5, sixth nMOS transistor MN6, and seventh nMOS transistor MN7, the local write conversion circuit 2112 includes a tenth nMOS transistor MN10, an eleventh nMOS transistor MN11, and a twelfth nMOS transistor MN12. The drain of the tenth nMOS transistor MN10 is connected to the local data line Ldat, the gate of the tenth nMOS transistor MN10 is connected to the source of the twelfth nMOS transistor MN12 and the global complementary data line Gdat#, and the source of the tenth nMOS transistor MN10 is connected to the drain of the eleventh nMOS transistor MN11 . The gate of the eleventh nMOS transistor MN11 receives the local write signal Wr while the source is grounded. The drain of the twelfth nMOS transistor MN12 is connected to the local complementary data line Ldat# while the gate receives the local write signal Wr.

[00116] The local amplifier 2113 comprises: a first phase inverter 21, wherein the first input of the first phase inverter is electrically connected to the local data line Ldat and the first output out1 of the first phase inverter is electrically connected to the local complementary data line Ldat#; and a second phase inverter 22, wherein the second input in2 of the second phase inverter 22 is electrically connected to the second output out2 of the first phase inverter 21 and the local complementary data line Ldat#, and the second output out2 of the second phase inverter 22 is electrically connected to the first input in1 of the first phase inverter 21 and the local data line Ldat .

[00117] Specifically, the first phase inverter 21 includes a first pMOS transistor MP1 and a first nMOS transistor MN1. The gate of the first pMOS transistor MP1 is electrically connected to the gate of the first nMOS transistor MN1 to serve as the first input in1 of the first phase inverter, the source of the first pMOS MP1 is connected to the working power VDD, and the drain of the first pMOS MP1 is connected to the drain of the first nMOS transistor MN1 to serve as the first output out1 of the first phase inverter 21.

[00118] The second phase inverter 22 includes a null pMOS transistor MP0 and a null nMOS transistor MN0. The gate of the null pMOS transistor MP0 is electrically connected to the gate of the null nMOS transistor MN0 to serve as the second input in2 of the second phase inverter 22, the source of the null pMOS transistor MP0 is connected to the operating power VDD, and the drain of the null pMOS transistor MP0 is connected to the drain of the null nMOS transistor MN0 to serve as the second output out2 of the second phase inverter 22.

[00119] The first pMOS transistor MP1, the first nMOS transistor MN1, the zero pMOS transistor MP0 and the zero nMOS transistor MN0 form a local amplifier 2113.

[00120] In addition, the local amplifier 2113 also contains an enable nMOS transistor mn. The first phase inverter 21 and the second phase inverter 22 are also connected to the drain of the enable nMOS transistor mn. The drain of the enable nMOS transistor mn is grounded while the gate receives the local enable signal En. Specifically, the source of the first nMOS transistor MN1 is connected to the source of the zero nMOS transistor MN0 and the drain of the sixth nMOS transistor MN6. In some other implementations, the source of the first nMOS transistor MN1 is grounded and the source of the zero nMOS transistor MN0 is grounded.

[00121] Due to the structure of the local amplifier 2113, the data rate from the bit line BL to the local data line Ldat is increased, the data rate from the complementary bit line BL# to the local complementary data line Ldat# is increased, and the memory drive requirement of the amplifier readings are reduced. In particular, let us assume, as an example, that the data of the bit line BL is at a high level and the data of the complementary data bit line BL# is at a low level. Since the first input in1 of the first phase inverter 21 is connected to the second output out2 of the second phase inverter 22, and the first output out1 of the first phase inverter 21 is connected to the second input in2 of the second phase inverter 22, during transmission from the bit line BL and the complementary bit line BL# to the local data line Ldat and the local complementary data line Ldat#, the circuit structure of the amplifier 2113 can lower the voltage of the local complementary data line Ldat# with a lower voltage to "0" faster, or can quickly increase the voltage of the local complementary data line Ldat with a higher voltage to "1". Therefore, the voltage-up rate of the local data line Ldat# is increased, and the voltage-down rate of the local complementary data line Ldat# is also increased. Moreover, the local data line Ldat and the local complementary data line Ldat# have reduced driving requirements for the sense amplifier.

[00122] In addition, since the local data line Ldat and the local complementary line Ldat# can reach high levels or low levels faster, the transmission from the local data line Ldat and the local complementary data line Ldat# to the global data line Gdat and the global complementary line Gdat# data can be implemented earlier. Thus, when data is read, the transmission rate from the local data line Ldat and the local complementary data line Ldat# to the global data line Gdat and the global complementary data line Gdat# increases.

[00123] Accordingly, during a write operation, the local amplifier 2113 may also amplify the local data line Ldat and the local complementary data line Ldat# to increase the data rate from the global data line Gdat and the global complementary data line Gdat# to the local data line Ldat and the complementary line Ldat# data.

[00124] In this embodiment, the pre-charge circuit 204 includes a third pMOS MP3, a fourth pMOS MP4, and a fifth pMOS MP5. The gate of the third pMOS MP3, the gate of the fourth pMOS MP4, and the gate of the fifth pMOS MP5 receive the pre-charge control signal Eq. The source of the third pMOS MP3 and the source of the fourth pMOS MP4 are connected to the operating power VDD, the drain of the third pMOS MP3 is electrically connected to the local data line Ldat, and the drain of the fourth pMOS MP4 is electrically connected to the local complementary data line Ldat#. The fifth pMOS transistor MP5 is electrically connected to the local data line Ldat and the local complementary data line Ldat# in response to the pre-charge control signal Eq. The control unit 202, in response to the read-write speed configuration signal, outputs a read-write control signal to change the data reading speed of the local read conversion circuit 2111 or the local write conversion circuit 2112, etc., thereby adjusting the read-write operation speed of the conversion circuit read-write.

[00125] The read-write conversion scheme proposed in this embodiment can correct the speed of the local read-write operation, but also the speed of the global read-write operation, so that the convenience of correcting the read-write operation speed of the read-write conversion scheme is further improved.

[00126] Accordingly, according to an embodiment of the present invention, a memory is provided that includes the aforementioned read-write conversion circuit.

[00127] The memory may be a dynamic random access memory (DRAM), static random access memory (Static Random-Access Memory, SRAM), magnetoresistive random access memory (Magneto resistive Random-Access Memory, MRAM), ferroelectric random access memory (Ferroelectric Random-Access Memory (FeRAM), Phase Change RAM (PCRAM), NAND flash, NOR flash, or other memory. From the above analysis, it can be seen that the memory proposed in this embodiment has the advantage of a variable bit rate, places low demands on the drive capability of the sense amplifier, and contributes to the miniaturization trend of the device.

[00128] Those skilled in the art can appreciate that each of the above modes of implementation is a specific implementation of the present application, and that in practical applications, forms and details may be changed without going beyond the essence and scope of the present invention. Those skilled in the art may make appropriate variations or modifications within the spirit and scope of the present invention, and therefore the protection scope of the invention should be limited to that defined by the claims.

Claims (28)

1. Scheme for converting read-write in dynamic random access memory, containing: a read-write conversion module, configured to perform a read-write operation in response to the read-write control signal; And a control module configured to output, in response to the read-write speed configuration signal, a variable read-write control signal to control the speed of the read-write operation of the read-write conversion module in the dynamic random access memory so that it is variable, wherein the read-write conversion circuit also contains a read-write amplifier, a local data line, a local complementary data line, a global data line and a global additional data line, and the read-write conversion module contains a local read-write block and a global read-write block, wherein the read data path of the read-write conversion circuit passes from the bit line and the complementary bit line to the local data line and the local complementary data line through the read amplifier, then to the local read-write unit through the local data line and the local complementary data line, then to the global data line and the global complementary data line via the local read/write block, and finally to the global read/write block via the global data line and the global complementary data line. 2. The read-write conversion circuit of claim 1, further comprising a speed configuration module connected to the control module and configured to output a read-write speed configuration signal to the control module. 3. The read-write conversion circuit according to claim 2, wherein the read-write control signal comprises a read control signal and a write control signal, and the read-write conversion module performs a read operation in response to the read control signal and performs a write operation in response to record control signal, wherein the rate configuration module comprises: a read rate configuration unit configured to output the read speed configuration signal in the read-write rate configuration signal to the control module to cause the control module to output, in response to the read speed configuration signal, a variable read control signal for control the speed of the read operation so that it is variable, and a write speed configuration unit, configured to output the write speed configuration signal in the read-write speed configuration signal to the control module to cause the control module to output, in response to the read speed configuration signal, a variable write control signal to control the speed of the write operation, thereby, to be a variable. 4. The read-write conversion circuit according to claim 1, wherein during the read-write operation, data is transferred between each of the local data line and the local complementary data line and the global data line, and the data signals of the local data line and the local complementary data line opposite in phase. 5. The read-write conversion circuit of claim 4, wherein the local read-write unit is configured to performing a local read/write operation in response to the local read/write control signal in the read/write control signal; A the control module contains a local control unit configured to output, in response to the local read-write speed configuration signal in the read-write speed configuration signal, a variable local read-write control signal to control the speed of the local read-write operation of the local read-write control unit - writing in such a way that it is a variable, wherein the read-write conversion circuit also comprises a local rate configuration module connected to the local control unit and configured to output the local read-write rate configuration signal to the local control unit, or wherein the sense amplifier is connected to the local read/write unit via a local data line and a local complementary data line, and configured to sense the voltage of the bit line. 6. The read-write conversion circuit of claim 5, wherein the same local read-write unit is connected to a plurality of read amplifiers via a local data line and a local complementary data line. 7. The read-write conversion circuit of claim 5, wherein the write data path extends from the local read-write unit to the read amplifier through the local data line and the local complementary data line, and then to the bit line through the read amplifier. 8. The read-write conversion circuit of claim 4, wherein the global read-write block is configured to performing a global read/write operation in response to the global read/write control signal; A the control module contains a global control unit configured to output, in response to the global read-write speed configuration signal in the read-write speed configuration signal, a variable global read-write control signal in the read-write control signal to control the speed of the global read-write operation - writing the global read-write control block so that it is a variable, wherein the read-write conversion circuit also includes a global speed configuration module connected to the global control unit and configured to output the global read-write speed configuration signal to the global control unit. 9. The read-write conversion circuit of claim 5, wherein the local read-write unit comprises a local amplifier connected between the local data line and the local complementary data line and configured to amplify the local data line data and the local complementary data line data, wherein the local amplifier comprises: a first phase inverter, in which the first input of the first phase inverter is electrically connected to the local data line, and the first output of the first phase inverter is electrically connected to the local complementary data line; And the second phase inverter, in which the second input of the second phase inverter is electrically connected to the first output of the first phase inverter and a local complementary data line, and the second output of the second phase inverter is electrically connected to the first input of the first phase inverter and the local data line, while the first phase inverter contains the first transistor on the metal- a p-channel oxide semiconductor (pMOS) and the first metal-oxide-semiconductor n-channel transistor (nMOS), wherein the gate of the first pMOS transistor is connected to the gate of the first nMOS transistor to serve as the first input of the first phase inverter, the source of the first pMOS transistor is connected to the operating power, and the drain of the first pMOS transistor is connected to the drain of the first nMOS transistor to serve as a as the first output of the first phase inverter; while the second phase inverter contains a zero pMOS transistor and a zero nMOS transistor, wherein the gate of the zero pMOS transistor is connected to the gate of the zero nMOS transistor to serve as the second input of the second phase inverter, the source of the zero pMOS transistor is connected to the operating power, and the drain of the zero pMOS transistor is connected to the drain of the zero nMOS transistor to serve in as the second output of the second phase inverter. 10. A memory containing a read-write conversion scheme according to any one of paragraphs. 1-9.

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