CN118467431A - Bus interface circuit with changeable chip identifier and implementation method thereof - Google Patents

Abstract

The invention discloses a bus interface circuit with a changeable chip identifier and an implementation method thereof. The bus interface circuit comprises a master radio frequency front end chip and a slave radio frequency front end chip, wherein the slave radio frequency front end chip comprises a VIO detection module and an MIPI module; the device comprises a VIO detection module, a MIPI module, a main radio frequency front-end chip, a power supply signal and a data signal, wherein the VIO detection module and the main radio frequency front-end chip are connected and exchanged positively, and the VIO detection module generates a corresponding VIO_SEL signal according to the power supply signal and the data signal and inputs the VIO_SEL signal into the MIPI module; when the default identifier of the chip needs to be changed, the VIO_SEL signal is utilized to trigger the exchange between the power supply signal and the data signal, the USID_SEL signal is generated by the VIO_SEL signal, and the USID_SEL signal is input into the MIPI module; the MIPI module generates a different chip default identifier in response to the USID_SEL signal. By utilizing the invention, the default product identifier and the subordinate identifier of the radio frequency front-end chip can be flexibly changed through software or firmware configuration under the condition of not adding additional hardware pins.

Description

Bus interface circuit with changeable chip identifier and implementation method thereof

Technical Field

The invention relates to a bus interface circuit capable of changing a default identifier of a chip, and also relates to a corresponding implementation method, belonging to the technical field of digital buses.

Background

With the rapid development of wireless communication technology, the application of radio frequency front end chips in smart phones and mobile devices is becoming more and more widespread. Radio frequency front-end chips typically include key components such as power amplifiers, low noise amplifiers, filters, and antenna switches that work together to ensure efficient transmission and reception of wireless signals. However, due to the high demands of mobile devices for miniaturization and integration, the rf front-end chip faces a problem of limited number of pads (pads) in design. Pad is a critical interface for connection of the chip interior to external circuitry, and the limited number means that it becomes more and more difficult to implement more functions and connections in a limited space.

In a multi-chip application scenario, such as a multiple-input multiple-output (MIMO) system, it may be necessary to connect multiple radio frequency front-end chips on the same bus. Each chip needs to have independent control and identification so that the system can be managed and operated accurately. This requires that each chip possess a unique identifier, including a Product Identifier (PID) and a subordinate identifier (USID). PIDs are typically assigned at the time of product design to distinguish between different models or series of products; the USID is a unique identification at the bus level that is used to distinguish between different slave devices on the same bus. In the prior art, the method for realizing the unique identification often needs additional hardware support or complex software configuration, which not only increases the complexity of design, but also can influence the performance and reliability of the system.

To solve this problem, some solutions have been proposed in the industry. For example, some systems employ complex pin configuration and initialization procedures to distinguish between different radio frequency front end chips. In the chinese patent publication number CN103226536B, a system and method for bus interface is disclosed. It provides a mechanism for changing the address of bus interface circuit when the identity of input terminal is exchanged, but its configuration mode is complex and flexibility is not enough.

Disclosure of Invention

The primary technical problem to be solved by the present invention is to provide a bus interface circuit capable of changing a default identifier of a chip.

Another technical problem to be solved by the present invention is to provide a method for changing a default identifier of a chip by using the bus interface circuit.

In order to achieve the above purpose, the present invention adopts the following technical scheme:

according to a first aspect of an embodiment of the present invention, there is provided a bus interface circuit with a variable chip identifier, including a master rf front-end chip and a slave rf front-end chip; wherein,

The slave radio frequency front end chip comprises a VIO detection module and an MIPI module; the device comprises a VIO detection module, a MIPI module, a data signal generation module and a data signal generation module, wherein the VIO detection module and the main radio frequency front-end chip are connected and exchanged with each other in a positive mode, and the VIO detection module generates a corresponding VIO_SEL signal according to the power signal and the data signal and inputs the corresponding VIO_SEL signal into the MIPI module;

when a chip default identifier needs to be changed, utilizing the VIO_SEL signal to trigger the exchange between the power supply signal and the data signal, generating a USID_SEL signal by the VIO_SEL signal, and inputting the USID_SEL signal into the MIPI module; the MIPI module generates a different chip default identifier in response to the USID_SEL signal.

Preferably, the VIO detection module generates the vio_sel signal by using a vio_sel signal generating circuit therein;

The vio_sel signal generating circuit includes two transistors; wherein the drain of each transistor is connected to one of the power signal and the data signal, respectively; the grid electrodes are respectively grounded through pull-down resistors on one hand and connected with USID_SEL signals on the other hand; and the sources are connected in parallel and then output the VIO_SEL signal.

Preferably, in the initial state, the grid electrode of the transistor is pulled to a low level through a pull-down resistor; when the voltage of the power signal or the data signal exceeds the threshold voltage of a transistor, the corresponding transistor is turned on, generating a corresponding usid_sel signal, thereby allowing the power signal or the data signal to be identified and responded to.

Wherein preferably, the VIO detection module generates the usid_sel signal using a usid_sel signal generation circuit therein;

The USID_SEL signal generation circuit comprises two D triggers and two AND gate circuits; the VIO_SEL signal generates a POR signal through a power-on reset circuit to trigger the D trigger, so that the state of the zero clearing signal is changed; the clear signal generates a corresponding usid_sel signal by a logical and operation.

Wherein preferably the usid_sel signal comprises a first signal USID1 and a second signal USID2; the first signal USID1 is generated by a logical and operation of a zero clearing signal a_latch of the first D flip-flop and an inverted zero clearing signal b_ LATCHN of the second D flip-flop, and the second signal USID2 is generated by a logical and operation of a zero clearing signal b_latch of the second D flip-flop and an inverted zero clearing signal a_ LATCHN of the first D flip-flop.

Wherein preferably the D flip-flop is replaced by a latch, an SR flip-flop or a JK flip-flop.

Preferably, for the radio frequency front end chip with the read-back function, when the MIPI bus executes the write operation, the Sdata_i signal is processed by the shaping circuit and then is transmitted to the slave radio frequency front end chip, and meanwhile, the Sdata_oen signal is set high to be used as write enabling; when the MIPI bus performs a write operation, the Sdata_oen signal is set low, the path of the Sdata_i signal is closed, and the output path of the Sdata_o signal is activated to allow data to be directly transmitted from the RF front-end chip to the main RF front-end chip through the read-back circuit.

Preferably, for the radio frequency front end chip which does not need the read-back function, the Sdata_o signal line and the Sdata_oen signal control logic are omitted, and the Sdata_i is used as a unidirectional input signal and is directly output to the slave radio frequency front end chip.

According to a second aspect of the embodiment of the present invention, there is provided a method for implementing a change of a default identifier of a chip by using the bus interface circuit, including the steps of:

(1) The system is started, and the power supply signal and the data signal are initialized to be in a low level;

(2) The VIO detection module starts to monitor the power supply signal and the data signal which are input from outside and generates a corresponding VIO_SEL signal;

(3) Triggering an exchange between the power signal and the data signal with the vio_sel signal if a change in a chip default identifier is required; the VIO_SEL signal generates a POR signal through a power-on reset circuit, triggers a D trigger and generates a USID_SEL signal;

(4) The MIPI module generates different chip default identifiers in response to different combinations of the USID_SEL signals.

Preferably, in the step (3), the usid_sel signal is dynamically generated by a D flip-flop and an and circuit according to the vio_sel signal, the POR signal, and the inverted signal PORN thereof, and is divided into a first signal USID1 and a second signal USID2.

Wherein preferably, in the step (4), the MIPI module generates corresponding product identifier and subordinate identifier in response to different combinations of the first signal USID1 and the second signal USID 2.

Compared with the prior art, the bus interface circuit and the implementation method thereof can realize that the same product has different product identifiers and subordinate identifiers while keeping the module area of the radio frequency front end chip smaller by exchanging the power supply signal and the data signal, thereby obviously improving the flexibility and the expandability of the radio frequency front end system. In addition, the invention also reduces design complexity, shortens design and test construction period and reduces cost. The invention can change the default product identifier and the subordinate identifier of the radio frequency front-end chip through flexible configuration on software or firmware, thereby effectively meeting the requirement of independent addressing and control of the radio frequency front-end chip in a multi-chip application scene.

Drawings

FIG. 1 is a schematic diagram of a bus architecture specified by the MIPI protocol;

FIG. 2 is a simplified schematic diagram of a bus interface circuit with variable chip identifiers in accordance with the present invention;

FIG. 3 is an interface detail diagram of a bus interface circuit with variable chip identifiers provided by the present invention;

FIG. 4 is a schematic diagram of a VIO_SEL signal generating circuit in accordance with an embodiment of the present invention;

FIG. 5 is a schematic diagram of a USID_SEL signal generating circuit in an embodiment of the present invention;

FIG. 6 is a schematic diagram of an Sdata_driver circuit in an embodiment of the invention;

FIG. 7 is a schematic diagram of a logical relationship determination region of a VIO signal and a Sdata signal;

FIG. 8 is a flowchart of a method for changing a default identifier of a chip by using the bus interface circuit according to the present invention;

Fig. 9 is a schematic diagram of an electronic device employing a bus interface circuit with variable chip identifiers provided by the present invention.

Detailed Description

The technical contents of the present invention will be described in detail with reference to the accompanying drawings and specific examples.

Fig. 1 shows a bus architecture specified by the MIPI protocol. In this architecture, a radio frequency integrated circuit (RF IC) 100 and a plurality of Front End Modules (FEM) 110 are included. The rf integrated circuit 100 is a center of the entire rf front-end system, and is responsible for processing the main transceiver task of the wireless signal. Inside the rf integrated circuit 100, a Master rf front-end chip is integrated as a Master (Master-slave architecture), responsible for generating control instructions and transmitting these instructions through the bus architecture. The bus architecture includes a clock signal line and a data line, which are bridges for communication between the radio frequency integrated circuit and the front-end module. The radio frequency integrated circuit 100 provides a clock signal (Sclk) over the Sclk line, ensuring data synchronization; and transmitting a data signal (Sdata) through the Sdata line, and transmitting a specific control instruction. In addition, VIO is a power signal through which the radio frequency integrated circuit 100 provides power to each front-end module 110.

The front-end module 110, which cooperates with the same, internally integrates a Slave rf front-end chip as a Slave (Master-Slave chip in a Master-Slave architecture) for receiving control instructions from a Master. Each front-end module 110 has a unique ID information, i.e., a slave identifier (USID), that allows the radio frequency integrated circuit 100 to identify and control the corresponding front-end module by a particular USID. In this way, even if multiple front end modules are connected to the same bus, the masters can be addressed and controlled independently by their respective USIDs.

In the bus architecture shown in fig. 1, communication between the radio frequency integrated circuit 100 and the front-end module 110 is accomplished by control instructions that include configuration and control of various components in the front-end module, such as adjusting the operating state of the power amplifier, switching antenna switches, or changing the frequency of the filter. In this way, complex radio frequency signal paths can be flexibly managed, meeting the requirements of modern mobile communication for high performance and high efficiency. In addition, since each of the front-end modules 110 has different USID for each of the front-end rf chips serving as Slave, the Master front-end rf chip serving as Master can precisely control each front-end module, so as to implement fine management on the rf front-end network. The chip identifiers (including but not limited to PID, USID, etc.) in MIPI protocols are fixed by default and do not facilitate flexible use in multi-chip application scenarios.

To this end, the embodiments of the present invention innovatively change the default chip identifier by exchanging the power signal and the data signal, thereby meeting the requirements of the MIPI device in some special scenarios. Compared with the method for reworking the MIPI device with completely consistent functions except for the chip identifier, the method can reduce half of design, test construction period and cost. The following is a detailed description with reference to the embodiments shown in fig. 2 to 7.

FIG. 2 is a simplified schematic diagram of a bus interface circuit with variable chip identifiers according to an embodiment of the present invention. As can be seen from fig. 2, the architecture of the bus interface circuit is similar to the bus architecture specified by the MIPI protocol, and the main difference is that the main rf front-end chip and each slave rf front-end chip only perform the forward connection and exchange of the power signal and the data signal through the power signal line (VIO) and the data line (Sdata). The positive connection here means that the power supply signal VIO and the data signal Sdata are transmitted through their respective lines, respectively. Switching (Swap) refers to interchanging the lines of the two signals such that the line that originally should transmit the power supply signal VIO now transmits the data signal Sdata, and the line that originally transmitted the data signal Sdata now transmits the VIO signal. By exchanging these two signals, configuration and control of the individual slave rf front-end chips may be achieved, such as changing the default identifiers (e.g., PID and USID) of the slave rf front-end chips.

Fig. 3 is an interface detail diagram of a bus interface circuit with variable chip identifiers according to an embodiment of the present invention. In each slave rf front-end chip 121, a VIO detection module 111 and a MIPI module 112 are included. The connection between them and the main rf front-end chip 120 is shown in fig. 3. The main task of the VIO detection module 111 is to monitor the externally input VIO signal and Sdata signal, among other things. The detection device has a detection function, can identify the VIO signal and the Sdata signal, and generates a judging signal USID_SEL based on the signals and logic operation results of the signals. The USID _ SEL signal is a control signal that is then sent to the MIPI module 112 instructing it to take a corresponding action.

According to MIPI protocol, after the power-up of the VIO signal is completed, at least 120 nanoseconds need to be waited to start sending the control command. During this time window, the Sclk signal and the Sdata signal remain in a low state. The VIO detection module 111 uses this feature to determine which is the first powered up signal to identify the VIO signal. Once the VIO signal is determined, the VIO detection module 111 can properly process the subsequent Sdata signal, ensuring that the data is received and processed by the MIPI module 112 at the proper timing.

The function of the MIPI module 112 is not limited to implementing the MIPI protocol and various functions to meet product requirements, but it is also capable of modifying its own ID information according to the usid_sel signal received from the VIO detection module 111. This includes modifying the Product Identifier (PID) and the slave identifier (USID) so that the slave rf front-end chip can respond to specific instructions of the master rf front-end chip for more flexible configuration and control. In addition, the VIO detection module 111 is also responsible for transmitting the Sdata signal output by the MIPI module 112 to the main rf front-end chip 120 through an internal selection path. Therefore, the master radio frequency front end chip can send proper control instructions according to the state and the requirement of the slave radio frequency front end chip, and accurate management of the radio frequency front end equipment is completed. The whole process ensures the consistent communication coordination between the master radio frequency front end chip and the slave radio frequency front end chip, and meets the requirements of the radio frequency front end module on high-efficiency and flexible control.

Fig. 4 is a schematic diagram of the vio_sel signal generating circuit of the VIO detection module 111 according to an embodiment of the present invention. As shown in fig. 4, the vio_sel signal generating circuit includes: two PMOS transistors, labeled MPO and MP1, and two pull-down resistors R0 and R1, all having a resistance of 51kΩ. The drains of the two transistors are respectively connected with a signal A and a signal B; the grid electrode is grounded through pull-down resistors R0 and R1 respectively on one hand, and receives output signals USID1 and USID2 respectively on the other hand; the sources are connected in parallel, and the VIO_SEL signal is output to the outside. In one embodiment of the present invention, the signal a represents a VIO signal received from the outside and the signal B represents an Sdata signal received from the outside, but not limited thereto, it is also possible that the signal a represents an Sdata signal received from the outside and the signal B represents a VIO signal received from the outside.

The vio_sel signal generating circuit is responsible for identifying the power supply signal VIO and the data signal Sdata and generating therefrom a control signal usid_sel, which includes two status bits, USID1 and USID 2. The circuit uses logically controlled transistors MPO and MP1 to distinguish between signal a (VIO signal) and signal B (Sdata signal) and to determine the respective representative identities by comparing their voltage levels. Once the VIO signal is asserted, the corresponding transistor (e.g., MPO) will turn on, allowing current to flow, affecting the state of USID1 and USID 2. In the initial state, the gate of the transistor is pulled low through resistors R0 and R1, ensuring that the transistor is turned off. When the voltage of signal a or B exceeds the threshold voltage of the transistor, the corresponding transistor will turn on. This will change the state of the levels of USID1 or USID2, allowing the VIO signal and the Sdata signal to be identified and responded to.

Fig. 5 is a schematic diagram of the usid_sel signal generation circuit in the VIO detection module 111. The core of the circuit is two D flip-flops (dff_a and dff_b) that are triggered by clock signals (CP and CPN) and two clear signals (a_latch and b_latch). In addition, the circuit includes two inverters (PORN and A_ LATCHN/B_ LATCHN) for providing the desired inverted signal. VSS and vss_dig in the circuit represent analog ground and digital ground, respectively, for ensuring stable operation of the circuit and proper signal reference.

In the initial state, the usid_sel signals (USID 1 and USID 2) are in a high impedance state, meaning that they have not yet been activated. The initial voltages of signals a and B are 0 volts, which represent the VIO and Sdata signals from the main rf front-end chip 120.

When signal A (representing the VIO signal) begins to rise to 1.8V, the VIO_SEL signal also rises. The vio_sel signal passes through a power-on reset (POR) circuit to generate a rising edge trigger signal. This rising edge triggers the D flip-flop, resulting in a change of the a_latch and b_latch states. Specifically, when vio_sel rises to the threshold voltage of the MOS transistor in the D flip-flop, dff_a and dff_b are triggered, a_latch goes high, and b_latch goes low, and vice versa.

The states of A_LATCH and B_LATCH determine the values of USID1 and USID 2. USID1 is generated by a_latch and b_ LATCHN through a logical and operation, and USID2 is generated by b_latch and a_ LATCHN. This means that if a_latch is high, then USID1 will be high if b_ LATCHN (i.e., the inverse of b_latch) is also high; if B_LATCH is low, A_ LATCHN (i.e., the inverse of A_LATCH) will be low as well, USID2 will be low.

The circuit further comprises two pull-down resistors R0 and R1 (51 kΩ) which provide an initial low level for the gates of transistors MP0 and MP1, ensuring that the transistors are in an off state when no signal is present. The on state of transistors MP0 and MP1 determines the final voltage of the VIO_SEL signal, which is consistent with signal A.

It should be noted that the D flip-flop in the above circuit may be replaced by a Latch (Latch), an SR flip-flop, or a JK flip-flop. In some cases, this helps reduce the complexity and cost of the circuit. USID1 and USID2 may be combined into a single USID signal. This simplification may reduce the number of circuit elements required while maintaining the necessary functionality.

In summary, the circuit design of FIG. 5 achieves accurate identification and response of the VIO and Sdata signals through fine logic control and signal processing, thereby generating the USID_SEL signal that controls the behavior of MIPI module 112.

Fig. 6 is a schematic diagram of an sdata_driver circuit according to an embodiment of the present invention. This circuit enables the main radio frequency front end chip 120 to flexibly control the flow direction of the data signal, sending the data to the correct path depending on the state of the MIPI module 112 and the selection of the usid_sel signal.

The sdata_driver circuit is responsible for selectively routing the sdata_o signal according to the usid_sel signal. In this circuit, the vio_sel signal is used to control the routing of the data signals, while the sdata_oen signal is used as an enable signal to control the output of the data. Specifically, the circuit receives the sdata_o signal from the MIPI module 112, which is generated in response to a control command from the main rf front-end chip 120. The Sdata_i in the circuit is the result of signals A and B after a logical AND operation, and represents the data signal input to MIPI module 112. When the MIPI module 112 outputs the Sdata_o signal according to the USID_SEL signal, it outputs a low level of the sdata_oen signal to the Sdata_driver circuit.

At the heart of the sdata_driver circuit is a multiplexer (or selector) that determines whether to output sdata_o to signal a or signal B based on the combination of the usid_sel signal and the sdata_oen signal. If sdata_oen is low, this indicates that MIPI module 112 is ready to send data, and that sdata_driver will select the output path according to the state of the USID_SEL signal. If the USID_SEL signal indicates output to signal A, sdata_o will be routed to signal A; if the USID_SEL signal indicates output to signal B, sdata_o will be routed to signal B.

In addition, the Sdata_driver circuit includes a VSS_DIG ground that provides a common reference level for the bus interface circuits. The vio_sel signal may also be used as an additional control signal to ensure proper routing between the power signal and the data signal.

Optionally, in one embodiment of the present invention, for a radio frequency front end chip that requires a read back function, it is necessary to guarantee bidirectional transmission and flexibility of data. Thus, the design of the Sdata signal allows for bidirectional data transfer. When the MIPI bus executes write operation, sdata_i is used as a data input signal, processed by a shaping circuit and then transmitted to a Slave radio frequency front-end chip serving as a Slave. At the same time, the Sdata_oen signal is asserted high, as a write enable, ensuring that data can be received from the RF front-end chip. In contrast, when a read operation is performed, the sdata_oen signal is set low, the path of the sdata_i signal is closed, and the output path of the sdata_o signal is activated, allowing data to be directly transmitted from the radio frequency front end chip to the Master radio frequency front end chip as a Master through a read back Circuit (Readback Circuit). This mechanism requires that the sdata_driver circuit be able to dynamically route the sdata_o signal into the correct path based on the sdata_oen and usid_sel signals.

In another embodiment of the present invention, a simplified solution may be adopted for a rf front-end chip that does not require a read-back function. In this scheme, the portion of the sdata_driver circuit associated with the sdata_o signal output is omitted, including omitting the sdata_o signal line and sdata_oen signal control logic. In this way, the Sdata_i signal no longer needs the enabling of the Sdata_oen signal, but is directly output to the Slave radio frequency front end chip as a Slave as a continuous unidirectional input signal. This approach simplifies the circuitry and signal lines required for read-back, not only simplifying the circuit design, but also reducing costs. However, the above scheme is only suitable for those application scenarios requiring only unidirectional data transmission, and for products requiring bidirectional data transmission, a complete Sdata signal transmission mechanism must be reserved.

Fig. 7 shows a logical relationship determination area of the VIO signal and the Sdata signal for determining which of the signal a and the signal B is the VIO signal and which is the Sdata signal.

In the initial state, the voltages of signals a and B are both 0 volts. When signal A (representing the VIO signal) begins to slowly rise to the voltage domain of 1.8V, the VIO_SEL signal also rises. The rise of the VIO _ SEL signal triggers a power-on reset (POR) circuit that generates a POR signal that marks the system is powered up and ready to begin operation.

The rise of the vio_sel signal is also associated with two critical logic signals: a_latch and b_latch. A_LATCH captures the state of signal A, and B_LATCH captures the state of signal B. These two signals, together with their inverted signals (a_ LATCHN and b_ LATCHN), are used to generate two usid_sel signals: USID1 and USID2. These signals then control the states of transistors MP0 and MP1, which in turn affect the final voltage of the VIO_SEL signal.

Specifically, when the vio_sel signal rises to the threshold voltage of the MOS transistors in the D flip-flop, the D flip-flops dff_a and dff_b are triggered. This causes the a_latch signal to go high and the b_latch signal to go low, or vice versa, depending on the relative times of signals a and B. Then, USID1 is generated from the a_latch signal and the b_ LATCHN signal through a logical and operation, and USID2 is generated from the b_latch signal and the a_ LATCHN signal. If the A_LATCH signal is high and the B_ LATCHN signal is also high, USID1 will be high; if the B_LATCH signal is low and the A_ LATCHN signal is also low, USID2 will be low.

The body diode of transistor MP0 turns on when signal A rises, thereby keeping the VIO_SEL signal consistent with the voltage of signal A. As the VIO_SEL signal rises, the gate-to-source voltage (|VGS|) of MP0 increases, causing transistor MP0 to turn on further. Meanwhile, the transistor MP1 is turned off because |vgs| is 0 volt, and thus the state of the signal B (representing the Sdata signal) does not affect the output of the vio_sel signal.

Finally, the vio_sel signal ensures that the VIO and Sdata signals can be properly identified and processed, providing the necessary signal state information for subsequent MIPI module 112 operations.

Based on the bus interface circuit, the embodiment of the invention further provides a realization method for changing the default identifier of the chip by using the bus interface circuit. As shown in fig. 8, the implementation method at least includes the following steps:

(1) The system is started, and the power supply signal VIO and the data signal Sdata are initialized to be low level;

(2) The VIO detection module 111 starts to monitor the externally input VIO signal and Sdata signal, and generates a corresponding vio_sel signal;

specifically, once the VIO signal begins to rise, the VIO detection module 111 recognizes the VIO signal and generates a corresponding vio_sel signal.

(3) If a change in the chip default identifiers (e.g., PID and USID) is required, a switching operation is triggered with the VIO_SEL signal so that the line originally transmitting the VIO signal now transmits the Sdata signal and vice versa; wherein the vio_sel signal generates a rising edge trigger signal through the POR circuit, which triggers the D flip-flop, generating the usid_sel signal;

(4) The MIPI module 112 generates different chip default identifiers in response to different combinations of USID _ SEL signals.

Once the USID_SEL signal has stabilized, the master RF front-end chip and the respective slave RF front-end chip will operate in accordance with the new configuration, at which point the default identifier of the chip has been altered.

The following describes the specific steps of the implementation method in detail with reference to the interaction process between the main rf front-end chip 120 and the VIO detection module 111 and MIPI module 112 shown in fig. 2 to 7:

First, the main rf front-end chip 120 outputs a VIO signal and a Sdata signal, and it is assumed here that signal a represents the VIO signal, signal B represents the Sdata signal, and the initial states are all 0 v. The VIO_SEL signal is controlled by the A signal, which rises when the A signal rises to 1.8V. The vio_sel signal generates the POR signal via a power-on reset (POR) circuit. In fig. 4, two transistors MP0 and MP1 receive a low level through pull-down resistors R0 and R1. When the VIO signal (signal a) rises, transistor MP0 turns on and the voltage of the vio_sel signal rises accordingly to coincide with signal a. At this time, the usid_sel signal is dynamically generated by the D flip-flop and the and circuit based on the vio_sel signal, the POR signal, and its inverse PORN, and is split into two signals USID1 and USID2. These signals control the on/off states of transistors MP0 and MP1, ultimately causing the VIO_SEL voltage to remain consistent with signal A.

Second, signals a and B generate sdata_i signals through a logical and operation, which are then fed into the MIPI module 112. The MIPI module 112 responds to the corresponding read command according to the USID_SEL signal and generates a Sdata_o signal for output to the Sdata_driver circuit. The sdata_driver circuit decides to output the sdata_o signal to signal a or signal B according to the usid_sel signal and the sdata_oen signal. When VIO is high, the Sdata signal generates the sdata_i signal through a shaping circuit so that the MIPI module 112 can correctly recognize and respond.

As the VIO signal (signal a) rises to 1.8v, the vio_sel signal also rises to the threshold voltage of the MOS transistors in the D flip-flop, triggering dff_a and dff_b. This results in the generation of the USID1 and USID2 signals, which are consistent with the VIO_SEL signal and ground, respectively. USID1 is generated by a_latch and b_ LATCHN through a logical and operation, and USID2 is generated by b_latch and a_ LATCHN. As long as signal A remains powered on, the POR signal will remain high, stabilizing the USID_SEL signal.

The MIPI module 112 then generates different PIDs and USIDs based on the different combined responses of the USID_SEL signals. As shown in fig. 7, when USID1 is 0 and USID2 is 1, MIPI module 112 responds to a set of PID and USID; and vice versa. For example, if the PID consists of 6-bit base encoding and two bits USID1, USID2, then different PIDs and USIDs may be obtained depending on the different USID1 and USID2 states.

In one embodiment of the invention, it is assumed that the PID consists of 6-bit base encoding and 2-bit USID status bits. In the initial state, neither USID1 nor USID2 is active, at which point MIPI module 112 will respond to this particular USID combination if USID1 becomes 0 and USID2 becomes 1. For example, if the base encoding is 100011, then in combination with usid1=0 and usid2=1, the final PID may be represented as 8'b100011, while the USID may be represented as 4' b00 (assuming the first two bits of the USID are fixed). If the states of USID1 and USID2 are interchanged, i.e., USID1 becomes 1 and USID2 becomes 0, MIPI module 112 will recognize a different combination and respond to the other set of PID and USID. In this case, the basic code 100011 combines usid1=1 and usid2=0, the final PID may become 8'b100111, and the USID may become 4' b01.

In another application scenario, if more detailed distinction is required between multiple rf front-end chips, more code bits may be used. For example, if the PID consists of 8-bit codes, where 6 bits are the base code and the remaining 2 bits are the USID status bits. When USID1 and USID2 are both 1, the pid may be denoted 8'b1010101 and the USID may be denoted 4' b11 in combination with the basic code 101010, which is suitable for a specific configuration of the radio frequency front end chip. For radio frequency front end chips with different hardware versions, different PID encodings may be required to distinguish. Assuming a base encoding of 110100, when USID1 is 0 and USID2 is 1, one hardware version may be assigned PID 8'b1101000 and USID 4' b01; while when USID1 is 1 and USID2 is 0, the other hardware version may be assigned PID 8'b1101100 and USID 4' b10.

The working principle of the bus interface circuit with the variable chip identifier and the implementation method thereof provided by the invention is described in detail above. Based on the bus interface circuit with the variable chip identifier, the embodiment of the invention further provides electronic equipment, which comprises the bus interface circuit with the variable chip identifier. The bus interface circuit is used as an important component of a radio frequency communication assembly for realizing communication control in a transmitting and/or receiving related assembly. The electronic device as referred to herein refers to a computer device that can be used in a mobile environment and supports multiple communication systems such as GSM, EDGE, CDMA, TD _ SCDMA, WCDMA, TDD _lte, fdd_lte, NR, and the like, including a mobile phone, a notebook computer, a tablet computer, a vehicle-mounted computer, and the like. In addition, the technical scheme provided by the invention is also suitable for other occasions of bus interface circuit application, such as a communication base station, an intelligent network car and the like.

As shown in fig. 9, the electronic device at least includes a processor, a memory, a communication module, and further includes a sensor module, a power module, a multimedia module, and an input/output interface according to actual needs. The memory, the communication component, the sensor component, the power component, the multimedia component and the input/output interface are all connected with the processor. The memory may be a Static Random Access Memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc., and the processor may be a Central Processing Unit (CPU), a Graphics Processor (GPU), a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a Digital Signal Processing (DSP) chip, etc. Other communication components, sensor components, power components, multimedia components, etc. may be implemented using common components and are not specifically described herein.

It should be noted that, any combination of the technical features of the above embodiments may be used, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

The bus interface circuit with changeable chip identifier and the implementation method thereof provided by the invention are described in detail. Any obvious modifications to the present invention, without departing from the spirit thereof, would constitute an infringement of the patent rights of the invention and would take on corresponding legal liabilities.

Claims (12)

1. The utility model provides a bus interface circuit of chip identifier variable, includes master radio frequency front end chip and from radio frequency front end chip, its characterized in that:

The slave radio frequency front end chip comprises a VIO detection module and an MIPI module; the device comprises a VIO detection module, a MIPI module, a data signal generation module and a data signal generation module, wherein the VIO detection module and the main radio frequency front-end chip are connected and exchanged with each other in a positive mode, and the VIO detection module generates a corresponding VIO_SEL signal according to the power signal and the data signal and inputs the corresponding VIO_SEL signal into the MIPI module;

when a chip default identifier needs to be changed, utilizing the VIO_SEL signal to trigger the exchange between the power supply signal and the data signal, generating a USID_SEL signal by the VIO_SEL signal, and inputting the USID_SEL signal into the MIPI module; the MIPI module generates a different chip default identifier in response to the USID_SEL signal.

2. The bus interface circuit of claim 1, wherein the VIO detection module generates the vio_sel signal using a vio_sel signal generation circuit therein;

The vio_sel signal generating circuit includes two transistors; wherein the drain of each transistor is connected to one of the power signal and the data signal, respectively; the grid electrodes are respectively grounded through pull-down resistors on one hand and connected with USID_SEL signals on the other hand; and the sources are connected in parallel and then output the VIO_SEL signal.

3. The bus interface circuit as set forth in claim 2, wherein:

In an initial state, the grid electrode of the transistor is pulled to a low level through a pull-down resistor; when the voltage of the power signal or the data signal exceeds the threshold voltage of a transistor, the corresponding transistor is turned on, generating a corresponding usid_sel signal, thereby allowing the power signal or the data signal to be identified and responded to.

4. The bus interface circuit of claim 1, wherein the VIO detection module generates the usid_sel signal using a usid_sel signal generation circuit therein;

The USID_SEL signal generation circuit comprises two D triggers and two AND gate circuits; the VIO_SEL signal generates a POR signal through a power-on reset circuit to trigger the D trigger, so that the state of the zero clearing signal is changed; the clear signal generates a corresponding usid_sel signal by a logical and operation.

5. The bus interface circuit as set forth in claim 4, wherein:

The usid_sel signal includes a first signal (USID 1) and a second signal (USID 2); the first signal (USID 1) is generated by a logical AND operation of a zero clearing signal (A_LATCH) of the first D trigger and an inverse zero clearing signal (B_ LATCHN) of the second D trigger, and the second signal (USID 2) is generated by a logical AND operation of a zero clearing signal (B_LATCH) of the second D trigger and an inverse zero clearing signal (A_ LATCHN) of the first D trigger.

6. The bus interface circuit as set forth in claim 4, wherein:

the D flip-flop is replaced by a latch, SR flip-flop or JK flip-flop.

7. The bus interface circuit as set forth in claim 1, wherein:

For the radio frequency front end chip with the read-back function, when the MIPI bus executes write operation, the Sdata_i signal is processed by the shaping circuit and then is transmitted to the slave radio frequency front end chip, and meanwhile, the Sdata_oen signal is set high to be used as write enabling; when the MIPI bus performs a write operation, the Sdata_oen signal is set low, the path of the Sdata_i signal is closed, and the output path of the Sdata_o signal is activated to allow data to be directly transmitted from the RF front-end chip to the main RF front-end chip through the read-back circuit.

8. The bus interface circuit as set forth in claim 1, wherein:

For the radio frequency front end chip which does not need the readback function, a Sdata_o signal line and a Sdata_oen signal control logic are omitted, and Sdata_i is used as a unidirectional input signal and is directly output to the slave radio frequency front end chip.

9. A method of implementing a change to a default identifier of a chip using the bus interface circuit of any one of claims 1 to 8, comprising the steps of:

(1) The system is started, and the power supply signal and the data signal are initialized to be in a low level;

(2) The VIO detection module starts to monitor the power supply signal and the data signal which are input from outside and generates a corresponding VIO_SEL signal;

(3) Triggering an exchange between the power signal and the data signal with the vio_sel signal if a change in a chip default identifier is required; the VIO_SEL signal generates a POR signal through a power-on reset circuit, triggers a D trigger and generates a USID_SEL signal;

(4) The MIPI module generates different chip default identifiers in response to different combinations of the USID_SEL signals.

10. The implementation method according to claim 9, characterized in that:

In the step (3), the usid_sel signal is dynamically generated by a D flip-flop and an and circuit according to the vio_sel signal, the POR signal, and the inverted signal PORN thereof, and is divided into a first signal (USID 1) and a second signal (USID 2).

11. The implementation method according to claim 10, characterized in that:

in the step (4), the MIPI module generates corresponding product identifiers and subordinate identifiers in response to different combinations of the first signal (USID 1) and the second signal (USID 2).

12. An electronic device comprising a bus interface circuit of variable chip identifier as claimed in any one of claims 1 to 8.