CN112765061B - Data transmission interface circuit and data transmission method thereof - Google Patents

Data transmission interface circuit and data transmission method thereof Download PDF

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Publication number
CN112765061B
CN112765061B CN202110067622.6A CN202110067622A CN112765061B CN 112765061 B CN112765061 B CN 112765061B CN 202110067622 A CN202110067622 A CN 202110067622A CN 112765061 B CN112765061 B CN 112765061B
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data
port
unit
transceiver unit
channel
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CN112765061A (en
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孙振亚
刘栋斌
赵越
李巍
李哲
刘衍峰
王小朋
高志良
张达
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)

Abstract

The invention provides a data transmission interface circuit, comprising: the circuit comprises a programmable logic unit, a first resistor, a second resistor, a third resistor, a fourth resistor, a bus transceiving unit and a data transceiving unit, wherein the bus transceiving unit comprises a first channel and a second channel; when the data port of the data transceiver unit is in a transmitting state or the data transmitting port of the programmable logic unit is in a working state, setting the data receiving port of the programmable logic unit to be in a high-impedance state; and when the data port of the data transceiving unit is in a receiving state or the data receiving port of the programmable logic unit is in a working state, setting the data sending port of the programmable logic unit to be in a high-impedance state. In addition, the invention also provides a data transmission method. The invention can simplify the complexity of hardware circuit design and save element resources.

Description

Data transmission interface circuit and data transmission method thereof
Technical Field
The invention relates to the technical field of data transmission interface circuit design, in particular to an interface circuit for multichannel asynchronous bidirectional data transmission and a data transmission method thereof.
Background
The currently commonly used bus transceiver usually includes two independent power rails, such as an SN74ALVC164245 chip of TI corporation, belonging to a 16-bit (dual octal) in-phase bus transceiver. The a-port of the transceiver has a supply voltage VCCA, which is set to operate at 2.5V and 3.3V, allowing conversion from 2.5V to 3.3V and vice versa. The B-port of the transceiver has a supply voltage VCCB set to operate at 3.3V and 5V, allowing conversion from 3.3V to 5V and vice versa. The transceiver is designed primarily for communication between asynchronous data buses, with its control pins (1DIR, 2DIR,1OE and 2 OE) powered by a supply voltage VCCA, ensuring that the Output Enable (OE) input is connected to the supply voltage VCC through a pull-up resistor during high impedance state of power-up initialization or power-down.
The communication between the transceiver and the asynchronous data bus is most suitable for the transmission of unidirectional signals, and can also be used for the transmission of bidirectional signals. However, when multi-channel bidirectional signal transmission is performed, there are problems caused by the problem that the directions of signals transmitted are not consistent (for example, the signals cannot be transmitted by the same channel). The common approach to this problem is primarily to use multi-chip bus transceivers, with only one signal per unit being transmitted. In this way, more bus transceivers are occupied, and the actually used bus transceivers can cause the condition of channel resource waste. In addition, the design has high requirements on hardware, and the complexity of the circuit is increased.
Disclosure of Invention
In view of this, the present invention provides a data transmission interface circuit and a data transmission method thereof.
In a first aspect, the present invention provides a data transmission interface circuit, including:
the circuit comprises a programmable logic unit, a first resistor, a second resistor, a third resistor, a fourth resistor, a bus transceiving unit and a data transceiving unit, wherein the bus transceiving unit comprises a first channel and a second channel;
the first end of the first resistor is connected with the first enabling control port of the programmable logic unit and the enabling control port of the first channel of the bus transceiver unit, and the second end of the first resistor is connected to a power supply;
the first end of the second resistor is connected with the direction control port of the first channel of the bus transceiver unit, and the second end of the second resistor is connected to a power supply;
a first end of the third resistor is connected with a second enabling control port of the programmable logic unit and an enabling control port of a second channel of the bus transceiver unit, and a second end of the third resistor is connected to a power supply;
a first end of the fourth resistor is connected with a direction control port of a second channel of the bus transceiver unit, and a second end of the fourth resistor is connected to a ground wire;
a data sending port at the side A of the first channel of the bus transceiving unit is connected with a data sending port of the programmable logic unit, and a data sending port at the side B of the first channel of the bus transceiving unit is connected with a data port of the data transceiving unit; and
and the data receiving port at the side A of the second channel of the bus transceiver unit is connected with the data receiving port of the programmable logic unit, and the data receiving port at the side B of the second channel of the bus transceiver unit is connected with the data port of the data transceiver unit.
Preferably, when the bus transceiver unit receives a data transmission signal from the data transceiver unit, the first enable control port of the programmable logic unit transmits a low level signal to the enable control port of the first channel of the bus transceiver unit.
Preferably, when the data port of the data transceiver unit is in a transmitting state or the data transmitting port of the programmable logic unit is in a working state, the data receiving port of the programmable logic unit is in a high impedance state.
Preferably, when the bus transceiver unit receives a data receiving signal of the data transceiver unit, the second enable control port of the programmable logic unit sends a low level signal to the enable control port of the second channel of the bus transceiver unit.
Preferably, when the data port of the data transceiver unit is in a receiving state or the data receiving port of the programmable logic unit is in a working state, the data sending port of the programmable logic unit is in a high impedance state.
Preferably, the programmable logic unit is a field programmable gate array, the bus transceiver unit is an in-phase bus transceiver, and the data transceiver unit is an analog-to-digital converter.
In a second aspect, the present invention provides a data transmission method applied to the data transmission interface circuit, where the method includes the steps of:
when the bus transceiver unit receives a data transmission signal of the data transceiver unit, the bus transceiver unit controls an enabling control port of a first channel of the bus transceiver unit to be pulled up to a power supply through the first resistor, so that the bus transceiver unit is in a high-impedance state in a power-on initialization process;
controlling a first enabling control port of the programmable logic unit to send a low-level signal to an enabling control port of a first channel of the bus transceiver unit, so that the first channel of the bus transceiver unit is in an effective state; and
and controlling a direction control port of the first channel of the bus transceiving unit to be pulled up to a power supply through the second resistor, so that the signal direction of the first channel of the bus transceiving unit is transmitted to the A-side data transmitting port from the B-side data transmitting port of the first channel of the bus transceiving unit in a unidirectional manner, and is transmitted to the data transmitting port of the programmable logic unit from the A-side data transmitting port.
Preferably, the method further comprises the steps of: and when the data port of the data transceiver unit is in a transmitting state or the data transmitting port of the programmable logic unit is in a working state, setting the data receiving port of the programmable logic unit to be in a high-impedance state.
In a third aspect, the present invention provides a data transmission method applied to the data transmission interface circuit, where the method includes the steps of:
when the bus transceiver unit receives a data receiving signal of the data transceiver unit, the bus transceiver unit controls an enabling control port of a second channel of the bus transceiver unit to be pulled up to a power supply through the third resistor, so that the bus transceiver unit is in a high-impedance state in a power-on initialization process;
controlling a second enabling control port of the programmable logic unit to send a low-level signal to an enabling control port of a second channel of the bus transceiver unit, so that the second channel of the bus transceiver unit is in an effective state; and
and controlling a direction control port of the second channel of the bus transceiver unit to be pulled down to a ground wire through the fourth resistor, so that the signal direction of the second channel of the bus transceiver unit is transmitted to a data receiving port on the side B in a unidirectional manner from a data receiving port on the side A of the second channel of the bus transceiver unit, and is transmitted to a data port of the data transceiver unit from the data receiving port on the side B.
Preferably, the method further comprises the steps of: and when the data port of the data transceiver unit is in a receiving state or the data receiving port of the programmable logic unit is in a working state, setting the data sending port of the programmable logic unit to be in a high-impedance state.
Compared with the prior art, the data transmission interface circuit and the data transmission method thereof provided by the embodiment of the invention utilize hardware VHDL language programming to complete asynchronous bidirectional signal transmission (programs in the programmable logic unit are written in VHDL language) through the FPGA-based programmable gate array, and realize multi-channel asynchronous bidirectional signal transmission under a single bus transceiver. Compared with the prior art, the embodiment of the invention has the following beneficial effects: (1) The FPGA software resource is directly utilized to realize multi-path asynchronous bidirectional signal transmission, and the using quantity of electronic components (bus transceivers) is greatly reduced; (2) And the single bus transceiver is used for completing multi-channel asynchronous bidirectional signal transmission, so that the complexity of hardware circuit design is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required to be used in the embodiments of the present invention or the description of the prior art will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a data transmission interface circuit according to embodiment 1 of the present invention;
fig. 2 is a data transmission flow chart of a data transmission method according to embodiment 2 of the present invention;
fig. 3 is a data receiving flow chart of the data transmission method according to embodiment 3 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the description relating to "first", "second", etc. in the present invention is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
It is further noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
Example 1
Fig. 1 is a schematic diagram of a data transmission interface circuit according to embodiment 1 of the present invention. In this implementation, the data transmission interface circuit includes: the circuit comprises a programmable logic unit 1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a bus transceiving unit 2 and a data transceiving unit 3, wherein the bus transceiving unit 2 comprises a first channel 21 and a second channel 22. In some embodiments, the Programmable logic unit 1 is a Field Programmable Gate Array (FPGA), the bus transceiver unit is an in-phase bus transceiver (e.g., an SN74ALVC164245 chip), and the data transceiver unit is an analog-to-digital converter (e.g., an AD7712 chip).
In some embodiments, through the programmable gate array based on the FPGA, the asynchronous bidirectional signal transmission can be programmed by using a hardware VHDL language (programs inside the programmable logic units are written in the VHDL language), so that the multichannel asynchronous bidirectional signal transmission under the single bus transceiver is realized.
Further, a first end of the first resistor R1 is connected to a first enable control port (FOE 1) of the programmable logic unit 1 and an enable control port (OE 1) of the first channel 21 of the bus transceiver unit 2, and a second end of the first resistor R1 is connected to a power supply VDD (for providing a working voltage).
Further, a first end of the second resistor R2 is connected to the direction control port (DIR 1) of the first channel 21 of the bus transceiver unit 2, and a second end of the second resistor R2 is connected to a power supply VDD (for providing a working voltage).
Further, a first end of the third resistor R3 is connected to a second enable control port (FOE 2) of the programmable logic unit 1 and an enable control port (OE 2) of the second channel 22 of the bus transceiver unit 2, and a second end of the third resistor R3 is connected to a power supply VDD (for providing a working voltage).
Further, a first end of the fourth resistor R4 is connected to the direction control port (DIR 2) of the second channel 22 of the bus transceiver unit 2, and a second end of the fourth resistor R4 is connected to the ground GND.
In some embodiments, the a-side data transmission port (SIG _ TX _ a [0:7 ]) of the first channel 21 of the bus transceiving unit 2 is connected to the data transmission port (SIGF _ TX _ a [0:7], such as the a-side data transmission port) of the programmable logic unit 1, and the B-side data transmission port (SIG _ TX _ B [0:7 ]) of the first channel 21 of the bus transceiving unit 2 is connected to the data port (SIG [0:7 ]) of the data transceiving unit 3.
In some embodiments, the a-side data receiving port (SIG _ RX _ a [0:7 ]) of the second channel 22 of the bus transceiving unit 2 is connected to the data receiving port (SIGF _ RX _ a [0:7], such as the a-side data receiving port) of the programmable logic unit 1, and the B-side data receiving port (SIG _ RX _ B [0:7 ]) of the second channel 22 of the bus transceiving unit 2 is connected to the data port (SIG [0:7 ]) of the data transceiving unit 3.
Further, in some embodiments, when the bus transceiver unit 2 receives the data transmission signal of the data transceiver unit 3, the first enable control port (FOE 1) of the programmable logic unit 1 transmits a low-level signal to the enable control port (OE 1) of the first channel 21 of the bus transceiver unit 2.
Further, in some embodiments, when the data port (SIG [0:7 ]) of the data transceiving unit 3 is in a transmission state or the data transmission port (SIGF _ TX _ a [0:7 ]) of the programmable logic unit 1 is in an operating state, the data reception port (SIGF _ RX _ a [0:7 ]) of the programmable logic unit 1 is in a high impedance state.
Further, in some embodiments, when the bus transceiver unit 2 receives the data receiving signal of the data transceiver unit 3, the second enable control port (FOE 2) of the programmable logic unit 1 sends a low-level signal to the enable control port (OE 2) of the second channel 22 of the bus transceiver unit 2.
Further, in some embodiments, when the data port (SIG [0:7 ]) of the data transceiving unit 3 is in a receiving state or the data receiving port (SIGF _ RX _ a [0:7 ]) of the programmable logic unit 1 is in an operating state, the data transmitting port (SIGF _ TX _ a [0:7 ]) of the programmable logic unit 1 is in a high impedance state.
Example 2
Please refer to fig. 2, which is a data transmission flow chart of the data transmission method according to embodiment 2 of the present invention. In this embodiment, the execution order of the steps in the flowchart shown in fig. 2 may be changed and some steps may be omitted according to different requirements. The data transmission method shown in fig. 2 is applied to the data transmission interface circuit shown in fig. 1.
Step S10: when the bus transceiver unit 2 receives the data transmission signal of the data transceiver unit 3, the enable control port (OE 1) of the first channel 21 of the bus transceiver unit 2 is controlled to be pulled up to the power supply VDD through the first resistor R1, so that the bus transceiver unit 2 is in a high impedance state in the power-on initialization process, thereby reducing the power-on current of the bus transceiver unit 2.
Step S11: and controlling the first enable control port (FOE 1) of the programmable logic unit 1 to send a low-level signal to the enable control port (OE 1) of the first channel 21 of the bus transceiver unit 2, so that the first channel 21 of the bus transceiver unit 2 is in an active state (working state).
Step S12: and controlling a direction control port (DIR 1) of the first channel 21 of the bus transceiving unit 2 to be pulled up to a power supply VDD through the second resistor R2, so that the signal direction of the first channel 21 of the bus transceiving unit 2 is unidirectionally transmitted to an A-side data transmission port (SIG _ TX _ A [0:7 ]) from a B-side data transmission port (SIG _ TX _ B [0:7 ]) of the first channel 21 of the bus transceiving unit 2, and is transmitted to a data transmission port (SIG _ TX _ A [0:7 ]) of the programmable logic unit 1 from an A-side data transmission port.
Further, in some embodiments, the data transmission method further includes the steps of: when the data port (SIG [0:7 ]) of the data transceiver unit 3 is in a transmission state or the data transmission port (SIGF _ TX _ a [0:7 ]) of the programmable logic unit 1 is in an operating state, the data reception port (SIGF _ RX _ a [0:7 ]) of the programmable logic unit 1 is set to a high impedance state.
A specific flow of data transmission using the data transmission interface circuit shown in fig. 1 is illustrated below by way of an example. Taking the data port SIG [0] of the data transceiving unit 3 as an example, when the data transceiving unit 3 transmits data to the programmable logic unit 1, the data transceiving unit 3 transfers the data to be transmitted from the data port SIG [0] to the B-side data transmission port SIG _ TX _ B [0] of the first channel 21 of the bus transceiving unit 2, and then from the B-side data transmission port SIG _ TX _ B [0] of the first channel 21 to the a-side data transmission port SIG _ TX _ a [0] of the first channel 21. Finally, the data is transmitted from the side a data transmission port SIG _ TX _ a [0] of the first channel 21 to the data transmission port SIGF _ TX _ a [0] of the programmable logic unit 1. When the data transmission port SIGF _ TX _ A [0] of the programmable logic unit 1 works (data transmission process), the data reception port SIGF _ RX _ A [0] of the programmable logic unit 1 is set to a high-impedance state to prevent the programmable logic unit 1 from sending signals outwards.
It should be noted that the data transmission flow of the other 7 groups of data ports (SIG [1] to SIG [7 ]) of the data transceiver unit 3 is similar to that of the SIG [0] port. Since the high impedance setting of the programmable logic unit 1 can be accurate to every signal, simultaneous transmission can be achieved even if all data is asynchronous. The data transmission interface circuit adopted by the invention reduces the complexity of hardware circuit design and saves the element resources of the circuit design.
Example 3
Please refer to fig. 3, which is a data receiving flow chart of the data transmission method according to embodiment 3 of the present invention. In this embodiment, the execution order of the steps in the flowchart shown in fig. 3 may be changed and some steps may be omitted according to different requirements. The data transmission method shown in fig. 3 is applied to the data transmission interface circuit shown in fig. 1.
Step S20: when the bus transceiver unit 2 receives the data transmission signal of the data transceiver unit 3, the enable control port (OE 2) of the second channel 22 of the bus transceiver unit 2 is controlled to be pulled up to the power supply VDD through the third resistor R3, so that the bus transceiver unit 2 is in a high impedance state in the power-on initialization process, thereby reducing the power-on current of the bus transceiver unit 2.
Step S21: and controlling the second enable control port (FOE 2) of the programmable logic unit 1 to send a low-level signal to the enable control port (OE 2) of the second channel 22 of the bus transceiver unit 2, so that the second channel 22 of the bus transceiver unit 2 is in an active state (working state).
Step S22: the direction control port (DIR 2) of the second channel 22 of the bus transceiving unit 2 is controlled to be pulled down to the ground GND through the fourth resistor R4, so that the signal direction of the second channel 22 of the bus transceiving unit 2 is unidirectionally transmitted from the a-side data receiving port (SIG _ RX _ a [0:7 ]) of the second channel 22 of the bus transceiving unit 2 to the B-side data receiving port (SIG _ RX _ B [0:7 ]) and is transmitted from the B-side data receiving port to the data port (SIG [0:7 ]) of the data transceiving unit 3.
Further, in some embodiments, the data transmission method further includes the steps of: when the data port (SIG [0:7 ]) of the data transceiver unit 3 is in a reception state or the data reception port (SIGF _ RX _ a [0:7 ]) of the programmable logic unit 1 is in an operating state, the data transmission port (SIGF _ TX _ a [0:7 ]) of the programmable logic unit 1 is set to a high impedance state.
The following describes a specific process of receiving data by using the data transmission interface circuit shown in fig. 1 by way of an example. Also taking the data port SIG [0] of the data transceiving unit 3 as an example, when the data transceiving unit 3 receives data from the programmable logic unit 1, the data to be received is transmitted from the data receiving port SIGF _ RX _ a [0] of the programmable logic unit 1 to the a-side data receiving port SIG _ RX _ a [0] of the second channel 22 of the bus transceiving unit 2, and then is transmitted from the a-side data receiving port SIG _ RX _ a [0] of the second channel 22 to the B-side data receiving port SIG _ RX _ B [0] of the second channel 22. Finally, the data is transmitted from the B-side data receiving port SIG _ RX _ B [0] of the second channel 22 to the data port SIG [0] of the data transceiver unit 3. When the data receiving port SIGF _ RX _ a [0] of the programmable logic unit 1 operates (data receiving process), the data transmitting port SIGF _ TX _ a [0] of the programmable logic unit 1 is set to a high impedance state to prevent the programmable logic unit 1 from receiving signals from the outside.
It should be noted that the data receiving flow of the other 7 groups of data ports (SIG [1] to SIG [7 ]) of the data transceiving unit 3 is similar to that of the SIG [0] port. Since the high impedance setting of the programmable logic unit 1 can be accurate to every signal, simultaneous transmission can be achieved even if all data is unsynchronized. The data transmission interface circuit adopted by the invention reduces the complexity of the hardware circuit design and saves the element resources of the circuit design.
According to the data transmission interface circuit and the data transmission method thereof, through the FPGA based programmable gate array, asynchronous bidirectional signal transmission (programs in the programmable logic units are written in the VHDL language) is completed by utilizing hardware VHDL language programming, and multi-channel asynchronous bidirectional signal transmission under a single bus transceiver is realized. The invention utilizes the characteristic that the multiple paths of the FPGA are accurately controllable to simultaneously control the transmission of the multiple paths of asynchronous bidirectional signals. When a certain signal in the data transceiver unit 3 is in a transmitting state, the data receiving port of the corresponding programmable logic unit 1 is switched to a high-impedance state; conversely, when a certain signal in the data transceiver unit 3 is in a receiving state, the data transmission port of the corresponding programmable logic unit 1 is switched to a high impedance state. Compared with the prior art, the embodiment of the invention at least has the following beneficial effects: (1) The FPGA software resources are directly utilized to realize multi-path asynchronous bidirectional signal transmission, so that the use number of electronic components (bus transceivers) is greatly reduced; (2) And the single bus transceiver is used for completing multi-channel asynchronous bidirectional signal transmission, so that the complexity of hardware circuit design is reduced.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments. In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present invention, it should be understood that the disclosed technical contents can be implemented in other manners. The above-described embodiments of the data transmission interface circuit are merely illustrative, and for example, the division of the unit may be a logical function division, and in actual implementation, there may be another division, for example, multiple units or components may be combined or may be integrated into another circuit, or some features may be omitted, or may not be executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present invention.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The foregoing is considered as illustrative only of the preferred embodiments of the invention, and is not to be construed in any way as limiting the scope of the invention. Any modifications, equivalents and improvements made within the spirit and principles of the invention and other embodiments of the invention without the creative effort of those skilled in the art are included in the protection scope of the invention based on the explanation here.

Claims (8)

1. A data transmission interface circuit, the data transmission interface circuit comprising:
the circuit comprises a programmable logic unit, a first resistor, a second resistor, a third resistor, a fourth resistor, a bus transceiving unit and a data transceiving unit, wherein the bus transceiving unit comprises a first channel and a second channel;
the first end of the first resistor is connected with the first enabling control port of the programmable logic unit and the enabling control port of the first channel of the bus transceiver unit, and the second end of the first resistor is connected to a power supply;
the first end of the second resistor is connected with the direction control port of the first channel of the bus transceiver unit, and the second end of the second resistor is connected to a power supply;
a first end of the third resistor is connected with a second enabling control port of the programmable logic unit and an enabling control port of a second channel of the bus transceiver unit, and a second end of the third resistor is connected to a power supply;
a first end of the fourth resistor is connected with a direction control port of a second channel of the bus transceiver unit, and a second end of the fourth resistor is connected to a ground wire;
a side A data sending port of the first channel of the bus transceiver unit is connected with a data sending port of the programmable logic unit, and a side B data sending port of the first channel of the bus transceiver unit is connected with a data port of the data transceiver unit; and
a data receiving port at the side A of the second channel of the bus transceiver unit is connected with a data receiving port of the programmable logic unit, and a data receiving port at the side B of the second channel of the bus transceiver unit is connected with a data port of the data transceiver unit;
when the data port of the data transceiver unit is in a transmitting state or the data transmitting port of the programmable logic unit is in a working state, the data receiving port of the programmable logic unit is in a high-impedance state;
and when the data port of the data transceiver unit is in a receiving state or the data receiving port of the programmable logic unit is in a working state, the data transmitting port of the programmable logic unit is in a high-impedance state.
2. The data transmission interface circuit according to claim 1, wherein when the bus transceiver unit receives a data transmission signal from the data transceiver unit, the first enable control port of the programmable logic unit transmits a low level signal to the enable control port of the first channel of the bus transceiver unit.
3. The data transmission interface circuit according to claim 1, wherein when the bus transceiver unit receives a data reception signal from the data transceiver unit, the second enable control port of the programmable logic unit sends a low level signal to the enable control port of the second channel of the bus transceiver unit.
4. The data transmission interface circuit of claim 1, wherein the programmable logic unit is a field programmable gate array, the bus transceiver unit is a non-inverting bus transceiver, and the data transceiver unit is an analog-to-digital converter.
5. A data transmission method applied to the data transmission interface circuit of claim 1, the method comprising the steps of:
when the bus transceiver unit receives a data transmission signal of the data transceiver unit, the bus transceiver unit controls an enabling control port of a first channel of the bus transceiver unit to be pulled up to a power supply through the first resistor, so that the bus transceiver unit is in a high-impedance state in a power-on initialization process;
controlling a first enabling control port of the programmable logic unit to send a low-level signal to an enabling control port of a first channel of the bus transceiver unit, so that the first channel of the bus transceiver unit is in an effective state; and
and controlling a direction control port of the first channel of the bus transceiver unit to be pulled up to a power supply through the second resistor, so that the signal direction of the first channel of the bus transceiver unit is transmitted to the A-side data transmission port from the B-side data transmission port of the first channel of the bus transceiver unit in a unidirectional mode, and is transmitted to the data transmission port of the programmable logic unit from the A-side data transmission port.
6. The data transmission method of claim 5, wherein the method further comprises the steps of: and when the data port of the data transceiver unit is in a transmitting state or the data transmitting port of the programmable logic unit is in a working state, setting the data receiving port of the programmable logic unit to be in a high-impedance state.
7. A data transmission method applied to the data transmission interface circuit of claim 1, the method comprising the steps of:
when the bus transceiver unit receives a data receiving signal of the data transceiver unit, the bus transceiver unit controls an enabling control port of a second channel of the bus transceiver unit to be pulled up to a power supply through the third resistor, so that the bus transceiver unit is in a high-impedance state in a power-on initialization process;
controlling a second enabling control port of the programmable logic unit to send a low-level signal to an enabling control port of a second channel of the bus transceiver unit, so that the second channel of the bus transceiver unit is in an effective state; and
and controlling a direction control port of the second channel of the bus transceiving unit to be pulled down to a ground wire through the fourth resistor, so that the signal direction of the second channel of the bus transceiving unit is transmitted to a data receiving port at the side B in a unidirectional manner from a data receiving port at the side A of the second channel of the bus transceiving unit, and is transmitted to a data port of the data transceiving unit from the data receiving port at the side B.
8. The data transmission method of claim 7, wherein the method further comprises the steps of: and when the data port of the data transceiver unit is in a receiving state or the data receiving port of the programmable logic unit is in a working state, setting the data sending port of the programmable logic unit to be in a high-impedance state.
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