CN115408321A

CN115408321A - Interface circuit, control method thereof, signal transmission system and electronic device

Info

Publication number: CN115408321A
Application number: CN202211038971.6A
Authority: CN
Inventors: 熊建才
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2022-08-29
Filing date: 2022-08-29
Publication date: 2022-11-29

Abstract

An interface circuit is configured with two signal ports, one of which is used to transmit a sequence start signal and a data signal and the other is used to transmit a clock signal, the interface circuit including: a data module to support processing of the data signal; a clock module for supporting processing of the clock signal; the two first ends of the switch module are respectively and correspondingly connected with the two signal ports, the two second ends of the switch module are respectively and correspondingly connected with the data module and the clock module, when the interface circuit receives the data signal and the clock signal, the switch module is used for conducting a target port to the data module and conducting the other signal port to the clock module, and the target port is one of the two signal ports for transmitting the sequence starting signal.

Description

Interface circuit, control method thereof, signal transmission system and electronic device

Technical Field

The embodiment of the application relates to the technical field of communication interfaces, in particular to an interface circuit, a control method thereof, a signal transmission system and electronic equipment.

Background

A Mobile Industry Processor Interface (MIPI) is an open standard developed by the MIPI alliance and established for a Mobile application Processor, and is used for standardizing interfaces inside a Mobile phone, such as a camera, a display screen Interface, a radio frequency/baseband Interface and the like, so that the complexity of Mobile phone design is reduced and the design flexibility is increased. The MIPI interface has a data port and a clock port, but there is a risk that the two signal ports are connected in reverse when the MIPI interface is connected, so that communication abnormality of the MIPI port is caused.

Disclosure of Invention

In view of the above, it is necessary to provide an interface circuit, a control method thereof, a signal transmission system, and an electronic device.

In a first aspect, the present application provides an interface circuit configured with two signal ports, one of the two signal ports being used for transmitting a sequence start signal and a data signal, and the other being used for transmitting a clock signal, the interface circuit comprising:

a data module to support processing of the data signal;

a clock module for supporting processing of the clock signal;

the switch module is provided with two first ends and two second ends, wherein one first end is used for switching and conducting to one of the two second ends, the other first end is used for switching and conducting to the other of the two second ends, the two first ends of the switch module are respectively correspondingly connected with the two signal ports, the two second ends of the switch module are respectively correspondingly connected with the data module and the clock module, when the interface circuit receives the data signal and the clock signal, the switch module is used for conducting a target port to the data module and conducting the other signal port to the clock module, and the target port is one of the two signal ports for transmitting the sequence starting signal.

In a second aspect, the present application provides a control method for an interface circuit, the interface circuit is configured with two signal ports, one of the two signal ports is used for transmitting a sequence start signal and a data signal, and the other is used for transmitting a clock signal, the interface circuit includes a data module, a clock module and a switch module, the data module is used for supporting processing of the data signal, the clock module is used for supporting processing of the clock signal, the switch module has two first ends and two second ends, one first end is used for switching on to one of the two second ends, the other first end is used for switching on to the other of the two second ends, the two first ends of the switch module are respectively connected to the two signal ports, and the two second ends of the switch module are respectively connected to the data module and the clock module, the control method includes:

acquiring a trigger signal output by the data module and/or the clock module in response to the sequence starting signal;

determining a target port according to the trigger signal and an initial conduction state, wherein the initial conduction state is a conduction state when the switch module transmits the sequence starting signal, and the target port is one of two signal ports of an interface circuit for transmitting the sequence starting signal;

and controlling the switch module to conduct the target port to the data module and conduct the other signal port to the clock module.

In a third aspect, the present application provides a signal transmission system, comprising:

a slave device including, for example, an interface circuit including the interface circuit as described above or a controller for executing a control method of the interface circuit as described above;

the master device is configured with a data port for sequentially transmitting a sequence starting signal and a data signal and a clock port for transmitting a clock signal, and the data port and the clock port are respectively connected with the two signal ports of the slave device in a one-to-one correspondence manner.

In a fourth aspect, the present application provides an electronic device comprising a signal transmission system as described above.

The interface circuit is arranged in the slave device, and the data module and the clock module can be switchably connected to the two signal ports by arranging the switch module. Therefore, when the interface circuit of the slave device is reversely connected with the external master device, the controller can switch the conducting state of the switch module, so that the clock signal is transmitted to the clock module, and the data signal is transmitted to the data module at the same time. Based on the structure, correct communication between the interface circuit and the external main equipment can be realized on the premise of not adjusting the external connection mode of the interface circuit.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or related technologies of the present application, the drawings needed to be used in the description of the embodiments or related technologies are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a hardware diagram of an interface circuit according to an embodiment;

FIG. 2 is a schematic diagram of a positive connection of an interface circuit according to an embodiment;

FIG. 3 is a schematic diagram of the reverse connection of the interface circuit according to one embodiment;

FIG. 4 is a timing diagram of signals on signal lines according to one embodiment;

FIG. 5 is a second hardware schematic of an interface circuit according to an embodiment;

FIG. 6 is a flowchart illustrating a control method of the interface circuit according to an embodiment;

FIG. 7 is a flowchart of one embodiment for determining a destination port based on the trigger signal and an initial on state;

FIG. 8 is a second flowchart illustrating a control method of the interface circuit according to an embodiment;

FIG. 9 is a hardware diagram of a signal transmission system according to an embodiment;

FIG. 10 is a schematic diagram of the switch modules of the two slave devices of the embodiment of FIG. 9 in an initial conducting state;

FIG. 11 is a schematic diagram of the switch modules of the two slave devices of the embodiment of FIG. 9 in a target conducting state;

fig. 12 is a second hardware schematic diagram of a signal transmission system according to an embodiment;

FIG. 13 is a schematic diagram of the switch modules of the two slave devices of the embodiment of FIG. 12 being in a target conduction state;

fig. 14 is a third hardware schematic diagram of a signal transmission system according to an embodiment;

FIG. 15 is a timing diagram of the signals for the interference on the control line SCLK;

FIG. 16 is a signal timing diagram illustrating the presence of an impedance floating state of a signal port;

fig. 17 is an internal structural diagram of an electronic device according to an embodiment.

Element number description:

the slave device: 10; a data module: 100; a data receiving unit: 110; a data transmission unit: 120 of a solvent; a clock module: 200; a switch module: 300, respectively; a master device: 20.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

The embodiment of the present application provides an interface circuit, which may be applied to multiple communication scenarios such as display and radio frequency, and the embodiments of the present application take the example of applying the interface circuit to a radio frequency communication scenario as an example for explanation. Specifically, the interface circuit of the embodiment of the present application is provided in a Slave Device (Slave Device). The slave Device refers to a Device or a Device controlled by a Master Device (Master Device). In radio frequency communication scenarios, the primary device is typically a Radio Frequency Integrated Circuit (RFIC) in an electronic device, which may also be referred to as a radio frequency transceiver. In a general electronic device system, a single MIPI system can support 4 primary devices at most. The slave devices are usually rf front-end modules, which include, for example, power amplifiers, low noise amplifiers, rf switches, and the like. The radio frequency Front end module adopting the MIPI control may be referred to as a MIPI radio frequency Front-end (MIPI RF Front-end, MIPI RFFE), which is a control interface standard for the radio frequency Front end control of the mobile terminal proposed by the MIPI alliance RFFE working group. Before MIPI RFFE is released, the control solution of a radio frequency front-end module is complex, if parallel GPIO ports are used for control, too many interfaces are needed, and the system cost cannot be borne. Some manufacturers start to customize serial port control, but complex software control and time sequence control need to be considered due to complex communication protocols, so that the realization is difficult, and the customized serial port is not beneficial to the communication of devices of different manufacturers. In 2010, the MIPI alliance introduced the MIPI RFFE protocol for radio frequency front end control. The MIPI RFFE protocol bus is composed of a power line (VIO) and two control lines (SCLK and SDATA), is simple to implement and easy to deploy, and can implement near real-time control within the requirement of a time sequence range.

Fig. 1 is a hardware schematic diagram of an interface circuit according to an embodiment, and referring to fig. 1, the interface circuit is configured with two signal ports, and the two signal ports are used for being respectively connected with two control lines in a one-to-one correspondence manner. That is, one signal port is for connection with the SCLK control line and the other signal port is for connection with the SDATA control line. The SCLK control line is used to provide clock signal and synchronization function, and the SDATA control line is used to provide control signal and transmit data. Accordingly, one of the two signal ports of the interface circuit is used to connect the SDATA control line to sequentially transmit signals such as a sequence start signal and a data signal. The Sequence Start Condition (SSC) is used by the master Device to inform the Slave Device (Slave Device) that data transmission is about to Start, and the data signal is used to carry data written by the master Device into a register of the Slave Device or carry data read from the register of the Slave Device to the master Device. Since the sequence start signal and the data signal are transmitted through the same control line, the sequence start signal and the data signal are transmitted through the same signal port of the interface circuit. It is understood that what signal is used for each signal port is determined by the connection relationship between the two signal ports of the interface circuit and the host device. That is, if a certain signal port is connected to a data port of the master device for outputting a data signal, the signal port is used for transmitting the data signal; if a signal port is connected to a clock port of the master device for outputting a clock signal, the signal port is used for transmitting the clock signal.

The interface circuit includes a data module 100, a clock module 200, and a switch module 300. The data module 100 is configured to support processing of a data signal from a master device to obtain data carried in the data signal, so as to implement data writing to a register of a slave device. The data module 100 is further configured to generate a corresponding data signal according to the data of the register of the slave device, so as to transmit the generated data signal to the master device, thereby implementing data reading of the register of the slave device. The clock module 200 is used to support the processing of the clock signal from the master device. It can be understood that, the specific manner of the data module 100 reading and writing the data in the data signal according to the clock signal processed by the clock module 200 may refer to the implementation manners in the related art, and the embodiment is not limited thereto.

The switch module 300 has two first terminals and two second terminals, wherein one first terminal is used for switching conduction to one of the two second terminals, and the other first terminal is used for switching conduction to the other of the two second terminals. That is, at the same time, the two first terminals of the switch module 300 are respectively conducted to different second terminals. Illustratively, the switch module 300 may be a DPDT switch. Two first ends of the switch module 300 are respectively connected to the two signal ports, and two second ends of the switch module 300 are respectively connected to the data module 100 and the clock module 200. That is, two first terminals of the switch module 300 are respectively connected to different signal ports of the interface circuit, one second terminal of the switch module 300 is connected to the data module 100, and the other second terminal is connected to the clock module 200. Wherein, one of the two signal ports for transmitting the sequence start signal is the target port. It is understood that the switch module 300 may also be configured with a greater number of first terminals or second terminals to implement the expansion of the switching function, and the embodiment is not limited thereto.

Specifically, fig. 2 is a schematic diagram illustrating a normal connection of an interface circuit according to an embodiment, and referring to fig. 2, if the interface circuit is connected to an external host device 20 in a conventional connection manner (i.e., in a normal connection manner), when the switch module 300 does not switch a signal transmission path, the data module 100 may be connected to the data port SDATA of the host device 20 through a correct control line, and the clock module 200 may also be connected to the clock port SCLK of the host device 20 through a correct control line. Referring to fig. 3, if the interface circuit is connected to the external master device 20 in an irregular connection manner (i.e. in reverse connection), when the switch module 300 does not switch the signal transmission path, the data module 100 is connected to the clock port SCLK of the master device 20 through a control line, and the clock module 200 is connected to the data port SDATA of the master device 20 through a control line, thereby causing abnormal communication between the master device 20 and the slave device 10. However, the present embodiment can change the signal transmission path through the switching function of the switching module 300 by providing the switching module 300, so that the switching module 300 can conduct a destination port to the data module 100 and another signal port to the clock module 200 when transmitting a data signal and a clock signal. Based on the above structure, the data module 100 and the clock module 200 can be switchably connected to the two signal ports, and when the interface circuit of the slave device 10 is reversely connected to the external master device 20, the controller can switch the on state of the switch module 300, so that correct communication between the interface circuit and the external master device 20 can be realized without adjusting the external connection mode of the interface circuit. That is, no matter the connection mode of the forward connection or the reverse connection is adopted, the signals can be ensured to be accurately transmitted to the corresponding data module 100 or the clock module 200, so that the reliability and the preparation yield of the signal transmission system are improved.

In one embodiment, the switch module 300 is configured to transmit the sequence start signal to the data module 100 or the clock module 200 when the interface circuit receives the sequence start signal. That is, when one signal port transmits a sequence start signal, the other signal port is not transmitting a sequence start signal. In particular, the switch module 300 may be configured with an initial conductive state in which the switch module 300 is in when the interface circuit receives the sequence start signal. The initial on state may be, for example, the on state shown in fig. 2, and this embodiment is not limited to this, and only needs to obtain the on mode of the initial on state from the controller of the device 10. The data module 100 and the clock module 200 are configured to respectively identify whether a sequence start signal is received, so as to determine a target port according to the identification result. When the initial conduction state and the module receiving the sequence start signal are known, the controller may determine the signal port receiving the sequence start signal, thereby determining the connection relationship between the signal port of the interface circuit and the main device 20, and thus determining whether the interface circuit and the main device 20 are in forward connection or reverse connection, thereby implementing accurate control of the target conduction state of the switch module 300.

In one embodiment, the sequence start signal has characteristic information to be identified. That is, when one signal port transmits a sequence start signal having characteristic information to be recognized, the other signal port is not transmitting a signal, or the transmitted signal does not have the characteristic information to be recognized. Therefore, the module that recognizes the feature information to be recognized in this period is necessarily the module that receives the sequence start signal. The characteristic information to be recognized may be level state information to be recognized, where the sequence start signal has a preset length, such as high level state information or low level state information greater than or equal to one clock cycle length. The characteristic information to be recognized may be that the sequence start signal has waveform information to be recognized, including, for example, a pulse signal waveform information. The characteristic information to be recognized may also be that the sequence start signal has edge information to be recognized, for example comprising a rising edge information or a falling edge information. Moreover, the feature information to be recognized may also be a combination of the above examples, and this embodiment is not limited, and for example, high-level state information of one clock cycle length may be transmitted first, and then pulse signal waveform information may be transmitted.

In one embodiment, the transmission duration of the sequence start signal is one clock cycle, and the characteristic information to be identified is rising edge information or falling edge information of the clock cycle. Fig. 4 is a timing diagram of signals on signal lines according to an embodiment, and the embodiment takes the feature information to be identified as the rising edge information as an example for description. Referring to fig. 4, power line VIO is powered up before control line SDATA and control line SCLK transmit signals, i.e., the voltage rises to the power voltage, which is, for example, 1.8V. The first transmission sequence start signal SSC at the control line SDATA always continues SCLK for one cycle, and is switched from the low state to the high state and back to the low state again during the clock cycle, so as to generate a rising edge message and a falling edge message, so that the data module 100 and the clock module 200 can determine whether the sequence start signal is received by recognizing the rising edge message (or the falling edge message). The data signal is the data signal as D6-D0 transmitted on control line SDATA. The level state on line SDATA is controlled one clock cycle prior to the transfer of the data signal, indicating whether the data signal to be transferred is read data or write data. For example, 1 (high state) in fig. 4 refers to writing data. In this embodiment, by setting the length and switching manner of the sequence start signal, the rising edge information or the falling edge information serving as the feature information to be identified can be accurately generated, so that the port receiving the sequence start signal can be accurately judged.

With continued reference to fig. 4, the control line SDATA is also used to transmit an identity match signal (Slave Address) after transmission of the sequence start signal SSC and before transmission of the DATA signal DATA. The identity matching signal is used for carrying identity authentication information, and SA3-SA0 in the time sequence represents the identity authentication information. Specifically, the master device 20 is generally connected with a plurality of slave devices 10, and the plurality of slave devices 10 are connected to the same signal port of the master device 20. Therefore, before transmitting the data signal, the master device 20 needs to inform each slave device 10 of the receiving object of the data signal to be transmitted, so as to avoid an erroneous response of the slave device 10. By matching the authentication information with the ID information of the slave device 10, it is ensured that the slave device 10 responding to the data signal is the correct receiving object, and the reliability of the communication process is improved.

Further, after sending the DATA signal, the control line SDATA is further configured to transmit a Parity signal (Parity signal), where the Parity signal carries the identity matching Signal (SA), the read-write identification signal, and Parity information of the DATA signal (DATA) that are transmitted previously, so as to verify the accuracy of the transmitted DATA. Illustratively, odd check, i.e. adding parity bits, may be used in RFFE, and the number of 1's included in a frame is odd. After transmission of the Parity signal Parity, the control line SDATA is also used to transmit a Bus Park command, which is used to mark the end of the frame command, similarly to the start of the sequence start signal SSC as frame command. Alternatively, the end of frame command may be represented by a combination of control line SCLK and control line SDATA. After sending the parity signal for one frame, the control line SDATA is pulled low and held for half SCLK period, and then the master device 20 gives the data line authority, and then sends a clock signal for one clock period again from the control line SCLK. Where control line SDATA is a bidirectional line. When the master device 20 writes data to the slave device 10, the master device 20 takes over the authority of the control line SDATA. When the write operation is complete, the host device 20 releases the authority of control line SDATA, which can be implemented by a tri-state gate. By the mode, interference of unauthorized equipment on signals transmitted on the control line SDATA can be avoided, and therefore reliability of the signals in the communication process is guaranteed.

Fig. 5 is a second hardware schematic diagram of the interface circuit according to an embodiment, and referring to fig. 5, in one embodiment, the data module 100 includes a data receiving unit 110 and a data sending unit 120. The DATA receiving unit 110 is used to recognize whether the received signal includes the feature information to be recognized when the interface circuit receives the sequence start signal, and supports the processing of the received DATA signal (RX DATA) under the control of the receive ENABLE signal (SDATA IN ENABLE) output from the external controller. The DATA transmission unit 120 serves to support processing of a transmitted DATA signal (TX DATA) under the control of a transmission ENABLE signal (SDATA OUT ENABLE) output from the external controller. Wherein, the data receiving unit 110 and the data transmitting unit 120 are connected to the same second end of the switch module 300. Through the above connection manner, the number of connection lines between the data module 100 and the switch module 300 can be simplified, and the control logic of the switch module 300 can be simplified.

The embodiment of the present application further provides a control method of an interface circuit, and the control method of the present embodiment may be used to control the interface circuit of any one of the foregoing embodiments. Fig. 6 is a flowchart illustrating a control method of the interface circuit according to an embodiment, and referring to fig. 6, the control method includes steps 602 to 606.

In step 602, a trigger signal output by the data module and/or the clock module in response to the sequence start signal is obtained.

And the trigger signal is output by the data module and/or the clock module according to the identification result. In particular, the trigger signal may be output by the module that receives the sequence start signal. For example, if the data module receives a sequence start signal, the data module outputs a trigger signal, and the clock module does not output any signal. If the clock module receives the sequence start signal, the clock module outputs a trigger signal, and the data module does not output any signal. The trigger signal can also be output by both the data module and the clock module, but the signal contents output by the two modules are different. For example, if the data module receives the sequence start signal, the data module outputs a trigger signal in a high level state, and the clock module outputs a trigger signal in a low level state. The embodiment does not limit the specific form of the trigger signal, as long as the outputs of the data module and the clock module are different.

Step 604, determining a target port according to the trigger signal and the initial conducting state.

The initial conduction state is a conduction state when the switch module transmits a sequence start signal, and the target port is one of two signal ports of the interface circuit. Specifically, the initial on state may be determined by the controller before receiving the sequence start signal and controlling the switching of the switch module, and based on the above manner, the operation of acquiring the target port may be simplified. The initial conducting state may also be read by the controller into a register that stores the current conducting state of the switch module when determining the target port, and based on the above manner, the number of times of switching the switch module may be reduced.

Step 606, the switch module is controlled to conduct the target port to the data module and conduct the other signal port to the clock module.

In this embodiment, the data module and the clock module are controlled to be switchably connected to the two signal ports, so that when the interface circuit of the slave device is reversely connected to the external master device, the on state of the switch module is switched to transmit the clock signal to the clock module and simultaneously transmit the data signal to the data module. Based on the method, correct communication between the interface circuit and the external main equipment can be realized on the premise of not adjusting the external connection mode of the interface circuit.

In one embodiment, the sequence start signal includes feature information to be identified, fig. 7 is a flowchart of determining a target port according to a trigger signal and an initial on-state according to an embodiment, and with reference to fig. 7, the above steps include step 702 and include at least one of step 704 and step 706.

Step 702, determining whether the signal received by the data module includes the feature information to be identified according to the trigger signal.

It will be appreciated that during normal use, the interface circuit is typically terminated. Therefore, if the initial on state of the switch module is the conventional manner shown in fig. 2, the probability of transmitting the sequence start signal to the data module is higher than the probability of transmitting the sequence start signal to the clock module. Therefore, whether the signal received by the data module comprises the characteristic information to be identified or not is judged firstly, the module receiving the sequence starting signal can be determined more quickly, and the control speed of the control method is improved.

Step 704, when the signal received by the data module includes the feature information to be identified, determining the signal port connected to the data module as the target port according to the initial conducting state.

Step 706, when the signal received by the data module does not include the feature information to be identified, judging whether the signal received by the clock module includes the feature information to be identified according to the trigger signal; and when the signal received by the clock module comprises the characteristic information to be identified, determining the signal port connected with the clock module as a target port according to the initial conduction state.

In this embodiment, when the initial conducting state and the module receiving the sequence start signal are known, the controller may determine the signal port receiving the sequence start signal, so as to determine the connection relationship between the signal port of the interface circuit and the host device, that is, determine whether the interface circuit and the host device are in forward connection or reverse connection, thereby implementing accurate and fast control of the target conducting state of the switch module.

In one embodiment, the data acquisition module and/or the clock module responds to a trigger signal output by the sequence start signal, and the method comprises the following steps. Acquiring a power supply voltage of an interface circuit; and when the power supply voltage is the target voltage, acquiring a trigger signal output by the data module and/or the clock module in response to the sequence starting signal. The target voltage is, for example, 1.8V. Specifically, when the power supply voltage of the interface circuit is the target voltage, it indicates that the interface circuit has been powered on, and therefore, the operation of identifying the sequence start signal may be continuously performed to implement a timely response to the control of the master device. Correspondingly, the control method also comprises the step of repeatedly executing the step of obtaining the power supply voltage of the interface circuit when the signals received by the data module and the clock module do not comprise the characteristic information to be identified. It can be understood that if the signal received by any module does not include the feature information to be identified, it indicates that neither the data module nor the clock module receives the sequence start signal, and the response does not need to communicate with the master device. Therefore, only the power supply voltage of the interface circuit needs to be continuously monitored, and when the power supply voltage is the target voltage, whether the sequence starting signal is received or not is judged again; and when the power supply voltage is lower than the target voltage, judging that the interface circuit is powered off, and stopping recognizing the sequence starting signal so as to reduce the power consumption of the interface circuit.

In one embodiment, when the interface circuit is applied to a slave device, the slave device where the interface circuit is located is configured with target identity information. Fig. 8 is a second flowchart of a control method of the interface circuit according to an embodiment, and referring to fig. 8, the control method includes steps 802 to 812. Steps 802 to 806 are similar to the previous embodiments, and are not repeated here.

In step 802, a trigger signal output by the data module and/or the clock module in response to the sequence start signal is obtained.

And step 804, determining a target port according to the trigger signal and the initial conduction state.

In step 806, the switch module is controlled to connect the target port to the data module and connect the other signal port to the clock module.

And 808, acquiring the identity authentication information carried by the identity matching signal received by the data module.

Step 810, target identity information of the slave device is obtained.

And step 812, enabling the slave device corresponding to the interface circuit to support the processing of the data signal and support the processing of the clock signal when the target identity information is matched with the identity verification information.

Specifically, a master device is generally connected with a plurality of slave devices, and the plurality of slave devices are connected to the same signal port of the master device, while different slave devices connected to the same master device are respectively configured with different target identity information. Therefore, before sending the data signal, the slave device can determine whether the slave device is a sending object of the data signal and the clock signal to be transmitted subsequently or not by acquiring the authentication information sent by the master device and matching the authentication information with the target identity information of the slave device, so that the error response of the slave device is avoided, and the reliability of the communication process is improved.

In one embodiment, the slave device is configured with initial identity information. The initial identity information is preset when the slave device leaves a factory, and different types of slave devices generally have different initial identity information. However, fig. 9 is one of the hardware schematic diagrams of the signal transmission system of an embodiment, and referring to fig. 9, in some usage scenarios, two

slave devices

10A and 10B have the same initial identity information. For example, the two slave devices 10 having the same initial identity information may be two pamids (PA modules integrated with duplexers) in the same rf system, where the pamids refer to an rf front end Module that integrates a PA, an rf switch and a filter. In the related art, it is required that these slave devices 10 must support the USID identification bit, and identify different USIDs by pulling up or pulling down different level states in hardware, so as to solve the problem of collision of two slave devices 10 with the same initial identity information. However, if the slave device 10 does not support USID identification, there is no solution. In addition, even if the slave device 10 supports USID identification, the hardware cost and the device area of the slave device 10 increase. In this case, the control method of the present embodiment may reconfigure the identity information of the slave devices 10 based on the foregoing structure, that is, configure new target identity information for each slave device 10, respectively, to ensure the accuracy of the communication process. Moreover, based on the control method of the embodiment, the conflict problem can be overcome without the support of a complex hardware structure, so that the hardware cost can be greatly reduced, and the area of the device can be reduced.

Accordingly, the following steps are further included before acquiring the authentication information carried in the identity matching signal received by the data module 100. When the initial conducting state is different from the target conducting state, determining corresponding target identity information according to the initial identity information of the slave device 10, wherein the target identity information is different from the initial identity information; when the initial on state is the same as the target on state, the initial identity information of the slave device 10 is taken as the target identity information. The target connection state is a connection state when the switch module 300 connects the target port to the data module 100 and connects the other signal port to the clock module 200.

Specifically, fig. 10 is a schematic diagram of the switch modules 300 of the two slave devices 10 in the embodiment of fig. 9 being in the initial conducting state, and fig. 11 is a schematic diagram of the switch modules 300 of the two slave devices 10 in the embodiment of fig. 9 being in the target conducting state. Referring to fig. 10 and 11 in combination, two slaves 10 having the same initial identity information may be connected to the master 20 in a forward connection and a reverse connection, respectively, the slave 10A located on the left side is forward connected, the slave 10B located on the right side is reverse connected, and the initial conducting states of the switch modules 300 of the two slaves 10 are the same. Therefore, upon receiving the sequence start signal, the slave device 10B located on the right side may find itself to be reversely connected, determine that the target on-state is different from the initial on-state, and reconfigure target identity information different from the initial identity information, the target identity information of the slave device 10B being, for example, 0X0B. The target on state of the slave device 10A on the left side is the same as the initial on state, and the reconfigured target identity information is the same as the initial identity information, and the target identity information of the slave device 10A is, for example, 0X0A. Based on the above manner, different target identity information can be configured for two slave devices 10 with the same initial identity information, so that the master device 20 can accurately transmit the data signal and the clock signal to the required slave device 10. It is understood that after the slave devices 10 reconfigure the target identity information, the master device 20 may respectively acquire the target identity information of each slave device 10 via the control line DATA and generate an identity matching signal carrying authentication information.

As another example, when the initial on-state is different from the target on-state, the initial identity information of the slave device 10 is taken as the target identity information; when the initial on-state is the same as the target on-state, corresponding target identity information is determined according to the initial identity information of the slave device 10, and the target identity information is different from the initial identity information. Specifically, fig. 12 is a second hardware schematic diagram of the signal transmission system according to the embodiment, and fig. 13 is a schematic diagram of the switch modules 300 of the two slave devices 10 according to the embodiment of fig. 12 being in the target on state. Referring to fig. 13, two slaves 10 having the same initial identity information may be connected to the master 20 in a forward and backward connection, respectively, the slave 10A located on the left side is in a backward connection, the slave 10B located on the right side is in a forward connection, and the initial on-states of the switch modules 300 of the two slaves 10 are the same. Therefore, upon receiving the sequence start signal, the slave device 10A located on the left side can find itself reversely connected, determine that the target on state is different from the initial on state, and reconfigure the target identity information identical to the initial identity information, the target identity information of the slave device 10A being, for example, 0X0A. The target on state of the slave device 10B on the right side is the same as the initial on state, and the reconfigured target identity information is different from the initial identity information, and the target identity information of the slave device 10B is, for example, 0X0B. Based on the above manner, different target identity information can be configured for two slave devices 10 with the same initial identity information, so that the master device 20 can accurately transmit the data signal and the clock signal to the required slave device 10. It is understood that after the slave devices 10 reconfigure the target identity information, the master device 20 may respectively acquire the target identity information of each slave device 10 via the control line DATA and sequentially generate the identity matching signal carrying the authentication information.

It should be understood that, although the steps in the flowcharts are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not limited to being performed in the exact order illustrated and, unless explicitly stated herein, may be performed in other orders. Moreover, at least a portion of the steps in each flowchart may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

With continued reference to fig. 2, an embodiment of the present application further provides a signal transmission system, which includes a slave device 10 and a master device 20. The slave device 10 includes, for example, an interface circuit including the interface circuit as described above or a controller for executing the control method of the interface circuit as described above, and a controller. The master device 20 is configured with a data port SDATA for sequentially transmitting a sequence start signal and a data signal and a clock port SCLK for transmitting a clock signal, which are connected to two signal ports of the slave device 10 in a one-to-one correspondence, respectively. With continued reference to fig. 9 and 12, in some embodiments, the signal transmission system includes a plurality of slave devices 10, and the initial identity information of at most two slave devices 10 in the plurality of slave devices 10 may be the same.

Fig. 14 is a third hardware schematic diagram of the signal transmission system according to an embodiment, referring to fig. 14, in which the signal transmission system further includes a pull-down resistor according to an embodiment. The pull-down resistor is connected to the clock port SCLK of the master device 20 to ground the clock port SCLK. Specifically, fig. 15 is a signal timing diagram of interference existing on the control line SCLK, referring to fig. 15, in the case of interference, for example, after the VIO is powered on, before a sequence start signal arrives, the control line SCLK connected to the master device 20 has an interference pulse signal, and may cause the slave device 10 to receive a high level triggered on the control line SCLK, so as to affect the judgment of the slave device 10 on the feature information to be recognized, and thus, target identity information collision of two slave devices 10 occurs, and communication of the signal transmission system is affected. In this case, the electronic device needs to be restarted to recover, which seriously affects the user experience. In addition, fig. 16 is a signal timing diagram showing an impedance floating state of a signal port, referring to fig. 16, the MIPI interface of the host device 20 performs MIPI initialization during a power-on process, when initialization is performed, the power supply voltage VIO is first powered on, and the impedance of the MIPI signal port of the host device 20 is in a floating state between the power supply voltage VIO is powered on and a start of a first communication sequence, where the floating state may cause unstable levels on the control lines SCLK and SDATA, and may easily form an interference signal triggered by rising edge information. Wherein if a jamming signal occurs on the control line SDATA, the recognition is not affected because it is on the same link as the sequence start signal SSC. However, if this interference signal occurs on the control line SCLK, the above-described situation shown in fig. 15 occurs, resulting in a failure of MIPI communication. Therefore, in the present embodiment, by setting the pull-down resistor, the problem that the level of the main device 20 is unstable in the floating process can be solved, so as to ensure that the level of the MIPI signal port of the main device 20 is always at a low level in the floating process, thereby solving the problem of interference and improving the reliability of the communication process. Alternatively, the pull-down resistor may have a resistance of 100K.

In one embodiment, an electronic device is provided, which comprises the signal transmission system.

In one embodiment, an electronic device is provided, and the electronic device may be a terminal, and fig. 17 is an internal structure diagram of the electronic device of an embodiment. The electronic device comprises a processor, a memory, a communication interface, a display screen and an input device which are connected through a system bus. Wherein the processor of the electronic device is configured to provide computing and control capabilities. The memory of the electronic equipment comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the electronic device is used for communicating with an external terminal in a wired or wireless manner, and the wireless manner can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement a control method of an interface circuit. The display screen of the electronic equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the electronic equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the electronic equipment, an external keyboard, a touch pad or a mouse and the like.

Those skilled in the art will appreciate that the structure shown in fig. 17 is a block diagram of only a portion of the structure relevant to the present application, and does not constitute a limitation on the electronic device to which the present application is applied, and a particular electronic device may include more or less components than those shown in the drawings, or combine certain components, or have a different arrangement of components.

In one embodiment, an electronic device is provided, which includes a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method embodiments when executing the computer program.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.

In one embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, performs the steps of the above-described method embodiments.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above may be implemented by hardware instructions of a computer program, which may be stored in a non-volatile computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. Any reference to memory, databases, or other media used in the embodiments provided herein can include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), magnetic Random Access Memory (MRAM), ferroelectric Random Access Memory (FRAM), phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), for example. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above embodiments only express several implementation manners of the embodiments of the present application, and the descriptions are specific and detailed, but should not be construed as limiting the scope of the invention. It should be noted that, for those skilled in the art, variations and modifications can be made without departing from the concept of the embodiments of the present application, and these embodiments are within the scope of the present application. Therefore, the protection scope of the patent of the embodiment of the application shall be subject to the appended claims.

Claims

1. An interface circuit configured with two signal ports, one of the two signal ports being used for transmitting a sequence start signal and a data signal, and the other being used for transmitting a clock signal, the interface circuit comprising:

a data module to support processing of the data signal;

a clock module for supporting processing of the clock signal;

2. The interface circuit of claim 1, wherein the switch module is configured to transmit the sequence start signal to the data module or the clock module when the interface circuit receives the sequence start signal;

the data module and the clock module are used for respectively identifying whether the sequence starting signal is received or not so as to determine the target port according to the identification result.

3. The interface circuit of claim 2, wherein the sequence start signal has feature information to be identified;

the data module or the clock module is used for judging that the sequence starting signal is received when the characteristic information to be identified is identified.

4. The interface circuit according to claim 3, wherein the transmission duration of the sequence start signal is one clock cycle, and the characteristic information to be identified is rising edge information or falling edge information of the clock cycle.

5. Interface circuit according to any of claims 3 to 4, wherein the data module comprises:

a data receiving unit, configured to, when the interface circuit receives the sequence start signal, identify whether the received signal includes the feature information to be identified, and support processing of the received data signal under control of a reception enable signal output by an external controller;

a data transmission unit for supporting processing of the transmitted data signal under control of a transmission enable signal output by the external controller;

wherein the data receiving unit and the data transmitting unit are connected to the same second end of the switch module.

6. A control method of an interface circuit, wherein the interface circuit is configured with two signal ports, one of the two signal ports is used for sequentially transmitting a sequence start signal and a data signal, and the other is used for transmitting a clock signal, the interface circuit includes a data module, a clock module and a switch module, the data module is used for supporting processing of the data signal, the clock module is used for supporting processing of the clock signal, the switch module has two first ends and two second ends, one first end is used for switching on to one of the two second ends, the other first end is used for switching on to the other of the two second ends, the two first ends of the switch module are respectively connected to the two signal ports, and the two second ends of the switch module are respectively connected to the data module and the clock module, the control method includes:

acquiring a trigger signal output by the data module and/or the clock module in response to a sequence starting signal;

determining a target port according to the trigger signal and an initial conduction state, wherein the initial conduction state is a conduction state when the switch module transmits the sequence start signal, and the target port is one of the two signal ports of the interface circuit for transmitting the sequence start signal;

7. The control method according to claim 6, wherein the sequence start signal includes feature information to be identified, and the determining a target port according to the trigger signal and an initial on state includes:

judging whether the signal received by the data module comprises the characteristic information to be identified or not according to the trigger signal;

when the signal received by the data module comprises the characteristic information to be identified, determining the signal port connected with the data module as the target port according to the initial conduction state; and/or

When the signal received by the data module does not comprise the characteristic information to be identified, judging whether the signal received by the clock module comprises the characteristic information to be identified or not according to the trigger signal; and when the signal received by the clock module comprises the characteristic information to be identified, determining the signal port connected with the clock module as the target port according to the initial conduction state.

8. The control method according to claim 7, wherein the acquiring data module and/or the clock module responds to a trigger signal output by a sequence start signal, and comprises the following steps:

acquiring a power supply voltage of the interface circuit;

when the power supply voltage is a target voltage, acquiring a trigger signal output by the data module and/or the clock module in response to a sequence starting signal;

the control method further comprises the following steps:

and when the signals received by the data module and the clock module do not comprise the characteristic information to be identified, the step of obtaining the power supply voltage of the interface circuit is repeatedly executed.

9. The control method according to claim 6, wherein when the interface circuit is applied to a slave device, the slave device in which the interface circuit is located is configured with target identity information, the control method further comprising:

acquiring identity verification information carried by the identity matching signal received by the data module;

acquiring the target identity information of the slave equipment;

and when the target identity information is matched with the identity verification information, enabling the slave equipment corresponding to the interface circuit to support the processing of the data signal and support the processing of the clock signal.

10. The control method according to claim 9, wherein the slave device is configured with initial identity information, and before obtaining the authentication information carried in the identity matching signal received by the data module, the method further comprises:

when the initial conduction state is different from the target conduction state, determining corresponding target identity information according to the initial identity information of the slave equipment, wherein the target identity information is different from the initial identity information; when the initial conduction state is the same as the target conduction state, taking the initial identity information of the slave equipment as target identity information; or

When the initial conducting state is different from the target conducting state, taking the initial identity information of the slave equipment as target identity information; when the initial conduction state is the same as the target conduction state, determining corresponding target identity information according to initial identity information of the slave equipment, wherein the target identity information is different from the initial identity information;

the target conduction state is a conduction state when the switch module conducts the target port to the data module and conducts the other signal port to the clock module.

11. A signal transmission system, comprising:

a slave device comprising an interface circuit and a controller, the interface circuit comprising the interface circuit of any one of claims 1 to 5 or the controller being configured to perform the control method of the interface circuit of any one of claims 6 to 10;

the master device is configured with a data port for sequentially transmitting a sequence start signal and a data signal and a clock port for transmitting a clock signal, and the data port and the clock port are respectively connected with the two signal ports of the slave device in a one-to-one correspondence manner.

12. The signal transmission system of claim 11, further comprising:

a pull-down resistor connected with the clock port to ground the clock port.

13. An electronic device, characterized in that it comprises a signal transmission system according to any one of claims 11 to 12.