CN118353424B - Triangle wave generator irrelevant to VDD - Google Patents
Triangle wave generator irrelevant to VDD Download PDFInfo
- Publication number
- CN118353424B CN118353424B CN202410764043.0A CN202410764043A CN118353424B CN 118353424 B CN118353424 B CN 118353424B CN 202410764043 A CN202410764043 A CN 202410764043A CN 118353424 B CN118353424 B CN 118353424B
- Authority
- CN
- China
- Prior art keywords
- switch
- circuit
- current mirror
- wave generator
- vdd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 8
- 239000003990 capacitor Substances 0.000 claims description 20
- 230000008859 change Effects 0.000 description 9
- 230000008901 benefit Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
Landscapes
- Control Of Electrical Variables (AREA)
Abstract
The application discloses a triangle wave generator irrelevant to VDD, which comprises a voltage-current conversion circuit, a charge pump circuit and a digital feedback circuit, wherein the voltage-current conversion circuit comprises a PNP triode Q1 and an NPN triode Q2, the base electrode of the PNP triode Q1 is connected with 1/4 power supply voltage VDD, the collector electrode is grounded, the emitter electrode is connected with one end of a resistor R5, and the common end of an emitter stage and the resistor R5 is connected with the base electrode of the NPN triode Q2; the emitter of the NPN triode Q2 is grounded through a resistor R4, the collector is connected with one side of the first current mirror, the other side of the first current mirror is connected with the first side of the second current mirror circuit, the second side of the second current mirror circuit is connected with the first side of the third current mirror circuit, the second side of the third current mirror circuit is connected with the third side of the second current mirror circuit, and the triangular wave generator designed by the circuit is high in precision and is not influenced by power supply voltage.
Description
Technical Field
The application relates to the technical field of electronic device testing, in particular to a triangle wave generator irrelevant to VDD.
Background
The triangular wave generator is a simple circuit that can generate a triangular wave signal. The principle is that a variable capacitor is controlled by an oscillator to generate a triangular wave signal. The output signal of the oscillator controls the capacitance value of the variable capacitor, thereby changing the oscillation frequency of the circuit. When the capacitance value of the capacitor changes, the output signal of the oscillator also changes, so that a triangular wave signal is generated;
the circuit of the early triangular wave generator has great limitation, the output amplitude is influenced by three factors such as frequency, current and capacitance, and the central point of the output amplitude is easily asymmetric and is easily deviated up and down as long as a point deviation exists.
Therefore, some improved structures are obtained, and the triangular wave generator with a feedback loop is provided; the change of the output triangular wave signal is limited between VDD/4 and 3 x VDD/4 through the cyclical change of the switching frequency, and the output amplitude of the output triangular wave signal is formed by negative feedback, so that the output amplitude of the output triangular wave signal cannot be changed along with the influence of frequency and resistance capacitance.
After improvement, the triangular wave generator structure with the feedback loop has the advantages that: the amplitude of the CLK signal can be controlled to deviate without being influenced by factors such as frequency, and the CLK signal can be independently generated to provide the switching frequency for the CLK signal. However, the disadvantage that cannot be overcome is that when the power supply voltage changes, the frequency deviation is particularly large, and the frequency cannot be constant along with the change of the power supply voltage;
In view of this, there is a need for a triangle wave generator independent of VDD, which is capable of maintaining the output triangle wave frequency as a whole constant when the power supply voltage is varied.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present application proposes a triangle wave generator independent of VDD, which solves the problem that the frequency deviation is particularly large when the power supply voltage is changed, and the frequency cannot be constant along with the change of the power supply voltage in the prior art.
The application adopts the following technical scheme for realizing the purposes:
The triangle wave generator irrelevant to VDD comprises a voltage-current conversion circuit, a charge pump circuit and a digital feedback circuit, wherein the voltage-current conversion circuit comprises a PNP triode Q1 and an NPN triode Q2, the base electrode of the PNP triode Q1 is connected with 1/4 power supply voltage VDD, the collector electrode is grounded, the emitter electrode is connected with one end of a resistor R5, and the common end of an emitter stage and the resistor R5 is connected with the base electrode of the NPN triode Q2;
the emitter of the NPN triode Q2 is grounded through a resistor R4, the collector is connected with one side of the first current mirror, the other side of the first current mirror is connected with the first side of the second current mirror circuit, the second side of the second current mirror circuit is connected with the first side of the third current mirror circuit, and the second side of the third current mirror circuit is connected with the third side of the second current mirror circuit;
Wherein, the mirror image proportion of the first current mirror circuit and the third current mirror circuit is 1:1, the mirror proportion of the second current mirror circuit is 1:1:1, a step of;
The charge pump circuit includes a PMOS transistor M8 and an NMOS transistor M9, the PMOS transistor M8 being configured to: the drain electrode is connected with the power supply voltage VDD, the source electrode is grounded through a switch S1N01 and is connected with the output end of the triangular wave generator through a switch S101, and the common end of the switch S101 and the output end of the triangular wave generator is grounded through a capacitor C1;
The NMOS transistor M9 is configured to: the source electrode is grounded, the drain electrode is connected with the power supply voltage VDD through a switch S102, the drain electrode is connected with the output end of the triangular wave generator through a switch S1N02, and the common end of the switch S101 and the output end of the triangular wave generator is grounded through a capacitor C1;
The common end of the capacitor C1 and the output end of the triangular wave generator is connected with a digital feedback circuit, and when the digital feedback circuit controls the switch S1N01 and the switch S1N02 to be opened, the switch S101 and the switch S102 are closed; when the digital feedback circuit controls the switch S1N01 and the switch S1N02 to be closed, the switch S101 and the switch S102 are opened.
As an alternative solution, the first current mirror circuit is formed by PMOS transistors M1, M2, M3, M4, wherein:
The PMOS transistor M1 is configured to: the grid electrode is connected with the common end of the source electrode of the PMOS transistor M2 and the drain electrode of the PMOS transistor M4, and is in common grid with the PMOS transistor M2, the source electrode is connected with the power supply voltage VDD, and the drain electrode is connected with the source electrode of the PMOS transistor M3;
the PMOS transistor M2 is configured to: the drain electrode is connected with the power supply voltage VDD;
the PMOS transistor M3 is configured to: the drain electrode is connected with the common end of the grid electrodes of the PMOS transistors M3 and M4 and the collector electrode of the NPN triode Q2;
the PMOS transistor M4 is configured to: the source electrode is connected with the first side of the second current mirror circuit.
As an optional solution, the aspect ratios of the PMOS transistors M1, M2, M3, and M4 are the same.
As an alternative solution, the second current mirror circuit is formed by NMOS transistors M5, M6, M9 with their gates connected to each other, wherein:
the NMOS transistor M5 is configured to: the source electrode is connected with the source electrode of the PMOS transistor M4 and the grid electrode of the NMOS transistor M5, and the drain electrode is grounded;
the NMOS transistor M6 is configured to: the source electrode is grounded, and the drain electrode is connected with one side of the second current mirror circuit.
As an alternative solution, the width-to-length ratios of the NMOS transistors M5, M6, M9 are the same.
As an alternative solution, the third current mirror circuit is formed by PMOS transistors M7, M8 with their gates connected to each other, wherein:
the PMOS transistor M7 is configured to: the source electrode is connected with the power supply voltage VDD, and the drain electrode is connected with the drain electrode of the NMOS transistor M6 and the gate electrode of the PMOS transistor M7.
As an alternative solution, the width-to-length ratios of the PMOS transistors M7 and M8 are the same
As an optional solution, the digital feedback circuit includes a first comparator and a second comparator, where:
The first comparator is configured to: the reverse input end is connected with the common end of the capacitor C1 and the output end of the triangular wave generator, the forward input end is connected with 1/4 power supply voltage VDD, the output end is connected with one input end of the first NOR gate circuit, and the output end of the first NOR gate circuit is connected with one input end of the second NOR gate circuit;
The second comparator is configured to: the reverse input end is connected with the common end of the capacitor C1 and the output end of the triangular wave generator, the forward input end is connected with the 3/4 power supply voltage VDD, the output end is connected with the other input end of the second NOR gate circuit through the first inverter, and the output end of the second NOR gate circuit is sequentially connected with the other input end of the first NOR gate circuit and the second inverter;
When the output end of the second inverter is at a high level, the switch S1N01 and the switch S1N02 are opened, and the switch S101 and the switch S102 are closed; when the output end of the second inverter is at the low level, the switches S1N01 and S1N02 are closed, and the switches S101 and S102 are opened.
The beneficial effects of the application include:
The triangular wave generator has the advantages that the frequency of the triangular wave can be stably output and does not change along with the change of the power supply voltage, the frequency change is only related to the resistance and the capacitance, and the problem that the accuracy comparison of power modules such as a subsequent driving circuit is affected due to too large frequency change when the triangular wave generator works in a wide power supply voltage range can be effectively prevented;
the triangular wave generator designed by the circuit has high precision, is not influenced by the power supply voltage, is only related to RC constant in parameters, and is suitable for the design of triangular waves in a wide power supply voltage system.
Other benefits or advantages of the application will be described in detail with reference to specific structures in the detailed description.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the application, and that other drawings can be obtained from these drawings without inventive faculty for a person skilled in the art. Furthermore, it should be understood that the scale of each component in the drawings in this specification is not represented by the scale of actual material selection, but is merely a schematic diagram of structures or positions, in which:
Fig. 1 is a schematic diagram of a triangular wave generator circuit according to the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In the description of the present application, it should be noted that terms such as "top" and "bottom" are used to refer to the present application in which the portion near the upper side is the top and the portion near the lower side is the bottom in the use state; the use of terms such as "first" and "second" is for the purpose of distinguishing between similar elements and not necessarily for the purpose of indicating or implying any particular importance or order of such elements; terms such as "inner", "outer" and "inner and outer" are used to refer to specific contours. The above terms are used only for the convenience of clearly and simply describing the technical solution of the present application and are not to be construed as limiting the present application.
Example 1:
the invention discloses a triangle wave generator irrelevant to VDD, which comprises a voltage-current conversion circuit, a charge pump circuit and a digital feedback circuit, wherein the voltage-current conversion circuit comprises a PNP triode Q1 and an NPN triode Q2, the base electrode of the PNP triode Q1 is connected with 1/4 power supply voltage VDD, the collector electrode is grounded, the emitter electrode is connected with one end of a resistor R5, and the common end of an emitter stage and the resistor R5 is connected with the base electrode of the NPN triode Q2; the emitter of the NPN triode Q2 is grounded through a resistor R4, the collector is connected with one side of the first current mirror, the other side of the first current mirror is connected with the first side of the second current mirror circuit, the second side of the second current mirror circuit is connected with the first side of the third current mirror circuit, and the second side of the third current mirror circuit is connected with the third side of the second current mirror circuit;
Wherein, the mirror image proportion of the first current mirror circuit and the third current mirror circuit is 1:1, the mirror proportion of the second current mirror circuit is 1:1:1, a step of; the charge pump circuit includes a PMOS transistor M8 and an NMOS transistor M9, the PMOS transistor M8 being configured to: the drain electrode is connected with the power supply voltage VDD, the source electrode is grounded through a switch S1N01 and is connected with the output end of the triangular wave generator through a switch S101, and the common end of the switch S101 and the output end of the triangular wave generator is grounded through a capacitor C1;
The NMOS transistor M9 is configured to: the source electrode is grounded, the drain electrode is connected with the power supply voltage VDD through a switch S102, the drain electrode is connected with the output end of the triangular wave generator through a switch S1N02, and the common end of the switch S101 and the output end of the triangular wave generator is grounded through a capacitor C1; the common end of the capacitor C1 and the output end of the triangular wave generator is connected with a digital feedback circuit, and when the digital feedback circuit controls the switch S1N01 and the switch S1N02 to be opened, the switch S101 and the switch S102 are closed; when the digital feedback circuit controls the switch S1N01 and the switch S1N02 to be closed, the switch S101 and the switch S102 are opened.
Specifically, as shown in fig. 1, the basic principle of the present invention is as follows:
Since the conventional triode with a voltage difference of 0.7V at the PN junction is adopted in this embodiment, in this solution, the potential of the emitter of the PNP triode Q1 is 0.7v+vdd/4, and then the potential difference between the base and the emitter of the NPN triode Q2 is 0.7V, so that the voltage vr=vdd/4+0.7v-0.7v=vdd/4 at the common end of the emitter of the NPN triode Q2 and the resistor R4, then the current i R4 =vdd/4R 4 flowing through the R4, the sizes of the PMOS transistors M1, M2, M3, and M4 are mirror images of the same size, and the currents flowing through the PMOS transistors M7 and M8 are the same, and the tube currents 1 of the PMOS transistor M8 are the same: 1 mirror PMOS transistor M7, NMOS transistors M5 and M6, M9 are also current source mirrors, thus i1=i2.
The output voltage amplitude of the output signal Vsaw is:
；
The charge-discharge formula of the output signal Vsaw is:
wherein, An output frequency of the output signal Vsaw, Q represents an amount of charge, t represents time, i1 represents a current on the i1 path, and i2 represents a current on the i2 path;
from the formula we can see that the frequency of the triangular wave is irrelevant to the power supply voltage and is only relevant to the resistors R4 and C1;
as an alternative solution, the first current mirror circuit is formed by PMOS transistors M1, M2, M3, M4, wherein:
The PMOS transistor M1 is configured to: the grid electrode is connected with the common end of the source electrode of the PMOS transistor M2 and the drain electrode of the PMOS transistor M4, and is in common grid with the PMOS transistor M2, the source electrode is connected with the power supply voltage VDD, and the drain electrode is connected with the source electrode of the PMOS transistor M3; the PMOS transistor M2 is configured to: the drain electrode is connected with the power supply voltage VDD; the PMOS transistor M3 is configured to: the drain electrode is connected with the common end of the grid electrodes of the PMOS transistors M3 and M4 and the collector electrode of the NPN triode Q2; the PMOS transistor M4 is configured to: the source electrode is connected with the first side of the second current mirror circuit. The width-to-length ratios of the PMOS transistors M1, M2, M3 and M4 are the same.
The second current mirror circuit is composed of NMOS transistors M5, M6, M9 whose gates are connected to each other, wherein:
the NMOS transistor M5 is configured to: the source electrode is connected with the source electrode of the PMOS transistor M4 and the grid electrode of the NMOS transistor M5, and the drain electrode is grounded;
The NMOS transistor M6 is configured to: the source electrode is grounded, and the drain electrode is connected with one side of the second current mirror circuit. The width-to-length ratios of the NMOS transistors M5, M6 and M9 are the same.
The third current mirror circuit is composed of PMOS transistors M7, M8 with their gates connected to each other, wherein:
The PMOS transistor M7 is configured to: the source electrode is connected with the power supply voltage VDD, and the drain electrode is connected with the drain electrode of the NMOS transistor M6 and the gate electrode of the PMOS transistor M7. The width-to-length ratio of the PMOS transistors M7 and M8 is the same
The digital feedback circuit includes a first comparator and a second comparator, wherein: the first comparator is configured to: the reverse input end is connected with the common end of the capacitor C1 and the output end of the triangular wave generator, the forward input end is connected with 1/4 power supply voltage VDD, the output end is connected with one input end of the first NOR gate circuit, and the output end of the first NOR gate circuit is connected with one input end of the second NOR gate circuit; the second comparator is configured to: the reverse input end is connected with the common end of the capacitor C1 and the output end of the triangular wave generator, the forward input end is connected with the 3/4 power supply voltage VDD, the output end is connected with the other input end of the second NOR gate circuit through the first inverter, and the output end of the second NOR gate circuit is sequentially connected with the other input end of the first NOR gate circuit and the second inverter;
When the output end of the second inverter is at a high level, the switch S1N01 and the switch S1N02 are opened, and the switch S101 and the switch S102 are closed; when the output end of the second inverter is at the low level, the switches S1N01 and S1N02 are closed, and the switches S101 and S102 are opened.
The working principle is as follows:
First charging operation state: when the output end of the second inverter is at a low level, the switches S1N01 and S1N02 are closed, the switches S101 and S102 are opened, the i1 path is formed, the capacitor C1 is charged through the tube of the mirror current source PMOS transistor M8, the voltage of the output signal Vsaw slowly rises from 0, when the voltage of the output signal Vsaw exceeds VDD/4 for the first time, the output voltage V1 of the first comparator is at a low level, and the low level is transferred to one input of the first nor gate, and the low level is transferred to one input of the second nor gate through the first nor gate; at this time, the output voltage V2 of the second comparator is high level and passes low level to the other input of the second nor gate through the first inverter, so that the output of the second nor gate is high level, and the output end of the second inverter is low level;
When the voltage of the output signal Vsaw continues to rise and exceeds 3VDD/4, the output voltage V2 of the second comparator (becomes low, and a high level is transferred to the other input of the second nor gate through the first inverter, so that the output of the second nor gate is low, and the output terminal of the second inverter is high, the switches S1N01 and S1N02 are turned on, and the switches S101 and S102 are turned off, so as to perform the next discharging process.
Second discharge operating state: when the output end of the second inverter is at a high level, the switches S1N01 and S1N02 are turned on, the switches S101 and S102 are turned off, the i2 path is formed, the capacitor C1 is discharged through the tube of the mirror current source NMOS transistor M9, the voltage of the output signal Vsaw is slowly reduced, when the voltage of the output signal Vsaw is reduced below VDD/4, the output voltage V1 is turned over by the first comparator, the level originally existing in the first nor gate is low, the low level is output through the first nor gate, the second nor gate is used for transmitting the high level of the input end of the second inverter, and when the output end is at a low level, the switches S1N01 and S1N02 are turned off, and the switches S101 and S102 are turned on.
The specific description is as follows: as shown in fig. 1, the paths of the switch S101 and the switch S102 opened are i1 paths, and the paths of the switch S1N01 and the switch S1N02 opened are i2 paths, and the scheme includes a voltage dividing path, and a resistor R1, a resistor R2, and a resistor R3 are connected in series between a power supply voltage VDD and a ground GND, wherein the common terminal voltage of the resistor R1 and the resistor R2 is 3 VDD/4, and the common terminal voltage of the resistor R3 and the resistor R2 is VDD/4.
The circuit can realize that triangular waves can still stably output fixed frequency under a wide power supply voltage range, the overall performance index is not influenced by the change of VDD, and the circuit is only related to resistance and capacitance, and the parameter performance of the circuit is compared as follows.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (8)
1. The triangle wave generator irrelevant to VDD is characterized by comprising a voltage-current conversion circuit, a charge pump circuit and a digital feedback circuit, wherein the voltage-current conversion circuit comprises a PNP triode Q1 and an NPN triode Q2, the base electrode of the PNP triode Q1 is connected with 1/4 power supply voltage VDD, the collector electrode is grounded, the emitter electrode is connected with one end of a resistor R5, and the common end of the emitter stage and the resistor R5 is connected with the base electrode of the NPN triode Q2;
the emitter of the NPN triode Q2 is grounded through a resistor R4, the collector is connected with one side of the first current mirror, the other side of the first current mirror is connected with the first side of the second current mirror circuit, the second side of the second current mirror circuit is connected with the first side of the third current mirror circuit, and the second side of the third current mirror circuit is connected with the third side of the second current mirror circuit;
Wherein, the mirror image proportion of the first current mirror circuit and the third current mirror circuit is 1:1, the mirror proportion of the second current mirror circuit is 1:1:1, a step of;
The charge pump circuit includes a PMOS transistor M8 and an NMOS transistor M9, the PMOS transistor M8 being configured to: the drain electrode is connected with the power supply voltage VDD, the source electrode is grounded through a switch S1N01 and is connected with the output end of the triangular wave generator through a switch S101, and the common end of the switch S101 and the output end of the triangular wave generator is grounded through a capacitor C1;
The NMOS transistor M9 is configured to: the source electrode is grounded, the drain electrode is connected with the power supply voltage VDD through a switch S102, the drain electrode is connected with the output end of the triangular wave generator through a switch S1N02, and the common end of the switch S101 and the output end of the triangular wave generator is grounded through a capacitor C1;
The common end of the capacitor C1 and the output end of the triangular wave generator is connected with a digital feedback circuit, and when the digital feedback circuit controls the switch S1N01 and the switch S1N02 to be opened, the switch S101 and the switch S102 are closed; when the digital feedback circuit controls the switch S1N01 and the switch S1N02 to be closed, the switch S101 and the switch S102 are opened.
2. A triangle wave generator independent of VDD as claimed in claim 1 wherein the first current mirror circuit is comprised of PMOS transistors M1, M2, M3, M4 wherein:
The PMOS transistor M1 is configured to: the grid electrode is connected with the common end of the source electrode of the PMOS transistor M2 and the drain electrode of the PMOS transistor M4, and is in common grid with the PMOS transistor M2, the source electrode is connected with the power supply voltage VDD, and the drain electrode is connected with the source electrode of the PMOS transistor M3;
the PMOS transistor M2 is configured to: the drain electrode is connected with the power supply voltage VDD;
the PMOS transistor M3 is configured to: the drain electrode is connected with the common end of the grid electrodes of the PMOS transistors M3 and M4 and the collector electrode of the NPN triode Q2;
the PMOS transistor M4 is configured to: the source electrode is connected with the first side of the second current mirror circuit.
3. A triangle wave generator independent of VDD as claimed in claim 2 wherein the PMOS transistors M1, M2, M3, M4 have the same aspect ratio.
4. A triangle wave generator independent of VDD as claimed in claim 1 wherein the second current mirror circuit is formed by NMOS transistors M5, M6, M9 with their gates connected to each other, wherein:
the NMOS transistor M5 is configured to: the source electrode is connected with the source electrode of the PMOS transistor M4 and the grid electrode of the NMOS transistor M5, and the drain electrode is grounded;
the NMOS transistor M6 is configured to: the source electrode is grounded, and the drain electrode is connected with one side of the second current mirror circuit.
5. The triangle wave generator independent of VDD as set forth in claim 4 wherein said NMOS transistors M5, M6, M9 have the same aspect ratio.
6. A triangle wave generator independent of VDD as claimed in claim 1 wherein the third current mirror circuit is formed by PMOS transistors M7, M8 with their gates connected to each other, wherein:
the PMOS transistor M7 is configured to: the source electrode is connected with the power supply voltage VDD, and the drain electrode is connected with the drain electrode of the NMOS transistor M6 and the gate electrode of the PMOS transistor M7.
7. The triangle wave generator independent of VDD as set forth in claim 6 wherein said PMOS transistors M7, M8 have the same aspect ratio.
8. The VDD independent triangle wave generator of claim 1 wherein said digital feedback circuit comprises a first comparator and a second comparator wherein:
The first comparator is configured to: the reverse input end is connected with the common end of the capacitor C1 and the output end of the triangular wave generator, the forward input end is connected with 1/4 power supply voltage VDD, the output end is connected with one input end of the first NOR gate circuit, and the output end of the first NOR gate circuit is connected with one input end of the second NOR gate circuit;
The second comparator is configured to: the reverse input end is connected with the common end of the capacitor C1 and the output end of the triangular wave generator, the forward input end is connected with the 3/4 power supply voltage VDD, the output end is connected with the other input end of the second NOR gate circuit through the first inverter, and the output end of the second NOR gate circuit is sequentially connected with the other input end of the first NOR gate circuit and the second inverter;
When the output end of the second inverter is at a high level, the switch S1N01 and the switch S1N02 are opened, and the switch S101 and the switch S102 are closed; when the output end of the second inverter is at the low level, the switches S1N01 and S1N02 are closed, and the switches S101 and S102 are opened.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410764043.0A CN118353424B (en) | 2024-06-14 | 2024-06-14 | Triangle wave generator irrelevant to VDD |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410764043.0A CN118353424B (en) | 2024-06-14 | 2024-06-14 | Triangle wave generator irrelevant to VDD |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118353424A CN118353424A (en) | 2024-07-16 |
| CN118353424B true CN118353424B (en) | 2024-08-13 |
Family
ID=91824991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410764043.0A Active CN118353424B (en) | 2024-06-14 | 2024-06-14 | Triangle wave generator irrelevant to VDD |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118353424B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101087105A (en) * | 2006-06-09 | 2007-12-12 | 富士通株式会社 | DC-DC converter and control for DC-DC converter |
| CN102904305A (en) * | 2011-12-15 | 2013-01-30 | 无锡中星微电子有限公司 | Charging management circuit in constant current charging mode |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103956905B (en) * | 2014-04-18 | 2018-09-18 | 昂宝电子（上海）有限公司 | System and method for the output current for adjusting power converting system |
| CN107623521B (en) * | 2017-09-29 | 2020-10-20 | 中国科学院半导体研究所 | Phase-locked loop clock generator |
| CN117748954B (en) * | 2024-02-19 | 2024-04-16 | 成都芯正微电子科技有限公司 | Triangular wave longitudinally adjustable Buck regulation and control circuit |
-
2024
- 2024-06-14 CN CN202410764043.0A patent/CN118353424B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101087105A (en) * | 2006-06-09 | 2007-12-12 | 富士通株式会社 | DC-DC converter and control for DC-DC converter |
| CN102904305A (en) * | 2011-12-15 | 2013-01-30 | 无锡中星微电子有限公司 | Charging management circuit in constant current charging mode |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118353424A (en) | 2024-07-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6362697B1 (en) | Low supply voltage relaxation oscillator having current mirror transistors supply for capacitors | |
| CN112234957B (en) | Analog oscillator circuit with negative feedback regulation function | |
| CN107040210B (en) | RC oscillator and DC-DC power chip | |
| CN106788338A (en) | RC oscillating circuits | |
| CN106230385B (en) | Clock generation circuit with adjustable oscillation frequency | |
| CN118353424B (en) | Triangle wave generator irrelevant to VDD | |
| CN206432966U (en) | RC oscillating circuits | |
| CN105897168A (en) | Rc oscillator | |
| CN115102384A (en) | Soft start control circuit, control method thereof and power supply circuit | |
| US3916343A (en) | Frequency stabilized relaxation oscillator | |
| CN111510114B (en) | Clock generator circuit | |
| CN114388017A (en) | Oscillation circuit and memory | |
| CN109474260B (en) | Digital adjustable oscillator | |
| US5852387A (en) | Voltage-controlled oscillator that operates over a wide frequency range | |
| CN118316396B (en) | Low temperature sensitivity oscillator based on band gap reference | |
| CN111682865A (en) | Relaxation oscillator and on-chip | |
| JPH05226984A (en) | Triangle wave oscillation circuit | |
| CN113691220B (en) | On-chip low frequency oscillator | |
| CN110752826B (en) | External RC frequency adjustable oscillator | |
| CN115395890B (en) | Temperature compensation RC oscillator circuit and application chip thereof | |
| CN217406494U (en) | Sawtooth wave clock generator circuit | |
| CN210807188U (en) | Oscillator with simple structure | |
| CN110995160B (en) | High-performance oscillator | |
| KR102287916B1 (en) | Low frequency oscillator by use of back-to-back coupling | |
| JP2543725Y2 (en) | Oscillation circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |