CN118315419A

CN118315419A - Grid reinforcing structure of III-nitride-based enhanced HEMT and manufacturing method thereof

Info

Publication number: CN118315419A
Application number: CN202211715553.6A
Authority: CN
Inventors: 陈昕; 孙钱; 钟耀宗; 张书明; 郭小路; 孙秀建; 李倩; 杨辉
Original assignee: Jiangxi Yuhongjin Material Technology Co ltd
Current assignee: Jiangxi Yuhongjin Material Technology Co ltd
Filing date: 2022-12-29
Publication date: 2024-07-09

Abstract

The invention discloses a gate reinforcing structure of a III-nitride-based enhanced HEMT and a manufacturing method thereof. The enhancement HEMT comprises a source, a drain, a gate and a group III nitride semiconductor structure; the grid reinforcing structure further comprises a cathode of a Schottky diode, and the Schottky diode and the enhanced HEMT are monolithically integrated and electrically isolated from each other; the cathode of the schottky diode forms an ohmic contact with the group III nitride semiconductor structure and is electrically connected to the gate, and the anode of the schottky diode forms a schottky contact with the group III nitride semiconductor structure. The III-nitride-based enhanced HEMT device with high gate reliability and stability can be realized.

Description

Grid reinforcing structure of III-nitride-based enhanced HEMT and manufacturing method thereof

Technical Field

The invention relates to a High Electron Mobility Transistor (HEMT), in particular to a III-nitride semiconductor enhanced HEMT with high gate reliability and stability and a manufacturing method thereof, belonging to the field of semiconductor electronic devices.

Background

As one of typical representatives of group III nitride semiconductor materials, gaN has advantages of a wide forbidden band, high breakdown field strength, high operating temperature, and the like. The High Electron Mobility Transistor (HEMT) formed by the AlGaN/GaN heterojunction also has the characteristics of high electron concentration and high mobility, is excellent in high voltage resistance, low on-resistance, high frequency and the like, can be used as a core device of various power conversion systems, and has wide prospect in the power application fields of consumer electronics, 5G base stations, servers and the like. In practice, the enhanced HEMT device is the preferred solution in power electronics system applications because it provides more fail-safe operation and simpler gate drive circuitry.

At present, a grid electrode of a monolithic GaN enhanced HEMT mostly adopts a metal/p-GaN/AlGaN/GaN composite stack structure, wherein a p-GaN layer is doped with a high-concentration Mg acceptor and is used for raising the energy band of the AlGaN/GaN layer so as to exhaust two-dimensional electron gas (2 DEG) to achieve the purpose of enhancement; the gate metal contacts mostly adopt schottky type to reduce gate leakage and increase gate swing, and such devices can be generally called p-GaN gate enhancement HEMTs (p-GaN E-HEMTs).

The conventional p-GaN E-HEMT mostly adopts a grid electrode with a metal/p-GaN/AlGaN/GaN stack structure, as shown in FIG. 1A. Wherein the p-GaN/AlGaN/GaN lamination is mostly grown by MOCVD epitaxy, and the p-GaN layer 006 has a single-layer structure with Mg doping concentration of 1-3×10 ¹⁹/cm³ and thickness of 70-150 nm. The AlGaN layer 005 has a single-layer structure with an Al component of 10-30% and a thickness of 10-30 nm. The GaN channel layer 004 has a single-layer structure with a thickness of 50 to 500 nm. The grid 007 is deposited by evaporation, sputtering and other processing methods, and has work function in the range of 4-6 eV, such as Ti, ni, pd and the like, and is prepared into Schottky contact for controlling the switching of the device; the source 008 and drain 009 use ohmic contacts with low contact resistance. In addition, the device can also comprise a substrate 001, a transition layer 002, a high-resistance pressure-resistant layer 003 and other conventional structural layers. The metal/p-GaN/AlGaN/GaN stack structure in fig. 1A may be equivalently a "schottky junction" (JS) of metal/p-GaN in series with a "double-sided hetero-PN junction" (JP) of p-GaN/AlGaN/GaN. When the gate is forward biased, the schottky junction JS is in a reverse biased state, assuming most of the voltage, and the gate leakage current is determined by the schottky junction, as shown in fig. 1B.

In practical application, on one hand, a certain voltage is required to be applied to the p-GaN E-HEMT gate to open a channel below, so that low on-resistance and high transconductance are realized; on the other hand, according to the safe working requirement of the grid, the p-GaN E-HEMT should keep lower leakage current, the forward voltage of the grid cannot be too high, because the acceptors of the p-GaN surface layer are almost ionized when the high voltage is biased, a higher electric field exists in the depletion region of J _S, firstly, carriers can be injected into the p-GaN layer from metal in a tunneling mode and drift under the action of the electric field, so that the grid leakage level is increased, even grid breakdown occurs, secondly, the carriers are accelerated under the high electric field, the original defects in the p-GaN region are activated, and even new defects are generated. The greatly increased gate current and defect state density can cause the schottky junction J _S to fail, thereby causing the problems of degradation of the reliability of the gate, and the like. Therefore, the breakdown voltage of the existing p-GaN E-HEMT is basically very low, generally around 12V, while the forward operating voltage is generally not more than 6V and only around 8V at maximum, which presents considerable challenges for gate driving.

Therefore, how to effectively solve the defects of low breakdown voltage, poor reliability under the forward bias of the gate and the like of the existing p-GaN E-HEMT has become a problem which needs to be solved by researchers in the field.

Disclosure of Invention

The invention mainly aims to provide a grid reinforcing structure of a III-nitride-based enhanced HEMT and a manufacturing method thereof, which are used for overcoming the defects in the prior art.

In order to achieve the purpose of the invention, the technical scheme adopted by the invention comprises the following steps:

One aspect of the present invention provides a gate reinforcement structure of a group III nitride based enhanced HEMT (E-HEMT) comprising a source, a drain, a gate, and a group III nitride semiconductor structure, the source and drain being electrically connected by a carrier channel formed within the group III nitride semiconductor structure; the grid reinforcing structure further comprises a cathode of a Schottky diode, and the Schottky diode and the enhanced HEMT are monolithically integrated and electrically isolated from each other; and the cathode of the Schottky diode forms ohmic contact with the III-nitride semiconductor structure and is electrically connected with the grid electrode, and the anode of the Schottky diode forms Schottky contact with the III-nitride semiconductor structure.

Another aspect of the present invention provides a method of fabricating a gate reinforcement structure of a group III nitride based enhanced HEMT, comprising the steps of fabricating an enhanced HEMT comprising a source, a drain, a gate, and a group III nitride semiconductor structure, the source and drain being electrically connected by a carrier channel formed within the group III nitride semiconductor structure; the manufacturing method further comprises the step of manufacturing a Schottky diode monolithically integrated with the enhanced HEMT, wherein the Schottky diode and the enhanced HEMT are electrically isolated from each other; the schottky diode has an anode and a cathode, the cathode forming an ohmic contact with the group III nitride semiconductor structure and being electrically connected to the gate, the anode forming a schottky contact with the group III nitride semiconductor structure.

Still another aspect of the present invention provides a group III nitride based enhanced HEMT comprising: monolithically integrated enhancement HEMTs and schottky diodes, and gate reinforcement structures for the group III nitride based enhancement HEMTs.

Compared with the prior art, the invention has the advantages that:

First, the gate breakdown voltage of the III-nitride-based enhanced HEMT, particularly the p-type gate E-HEMT, can be greatly improved, and the redundancy of the gate driving voltage can be increased. The p-type gate E-HEMT gate metal is prepared into ohmic contact, so that the formation of a high electric field in a depletion region on the surface of a p-type layer caused by reverse bias of a Schottky junction can be avoided, and further, the increase of gate leakage caused by carrier tunneling is avoided; while the schottky diode integrated in the chip itself has a very high withstand voltage. Therefore, the gate breakdown voltage of the p-type gate E-HEMT will be greatly improved.

Secondly, the reliability and stability of the grid electrode of the p-type grid E-HEMT can be effectively improved, because the metal/p-type layer is in ohmic contact, a Schottky barrier and a depletion region with high electric field intensity do not exist, and the grid electrode degradation problem caused by the activation of a defect state hardly exists in the p-type layer; meanwhile, the Schottky diode with the serially connected grid electrode has high reverse bias reliability and stability. Therefore, the gate reliability and stability of the p-type gate E-HEMT will also be effectively improved.

Drawings

Fig. 1A is a diagram showing the structure and gate equivalent of an enhanced HEMT according to the prior art.

Fig. 1B is a schematic diagram of an energy band structure under a positive gate voltage of an enhanced HEMT according to the prior art.

FIG. 2 is a schematic diagram of an epitaxial structure of a group III nitride based enhanced HEMT with an on-chip integrated diode according to one embodiment of the invention;

FIG. 3 is a schematic illustration of the fabrication of a p-type gate on the epitaxial structure of FIG. 2;

FIG. 4 is a schematic diagram of a group III nitride based enhanced HEMT of an on-chip integrated diode fabricated based on the epitaxial structure shown in FIG. 2;

Fig. 5 is a schematic structural diagram of a group III nitride based enhancement HEMT of an on-chip integrated diode according to embodiment 2 of the present invention;

Fig. 6 is a schematic structural diagram of a group III nitride based enhancement HEMT of an on-chip integrated diode according to embodiment 3 of the present invention;

Fig. 7 is a schematic structural diagram of a group III nitride based enhancement HEMT of an on-chip integrated diode according to embodiment 4 of the present invention;

Fig. 8 is a schematic structural diagram of a group III nitride based enhancement HEMT of an on-chip integrated diode according to embodiment 5 of the present invention;

Fig. 9 is a schematic structural diagram of a group III nitride based enhancement HEMT of an on-chip integrated diode according to embodiment 6 of the present invention.

Detailed Description

As described above, in the conventional p-GaN E-HEMT, under the forward gate, the gate schottky junction is in the reverse bias state, the acceptor on the surface of the p-GaN layer is almost completely ionized, the depletion region generates a high electric field, the carriers are easy to generate direct tunneling or defect-assisted tunneling, the gate leakage is greatly improved, the gate is easy to break down, and the problems of degradation at the metal/p-GaN interface, failure of the schottky junction and the like may be caused. On the other hand, in the MOCVD epitaxial growth, in order to obtain a p-GaN layer doped with high Mg, point defects such as C, H impurities and vacancies with higher density are unintentionally introduced, and the defect states are easily activated or expanded under a high electric field to form new defects, so that the problems of gate reliability degradation and the like are caused. The existence of these problems greatly limits the application of p-GaN E-HEMTs in high-end markets of industrial electronics, automotive electronics and the like.

Aiming at a plurality of defects in the prior art, the inventor provides a technical scheme of the invention through long-term research and a large number of practices, which mainly integrates a Schottky diode (SBD) with stable electric leakage under high reverse bias voltage and an ohmic contact grid of a p-type grid E-HEMT (high-Electron mobility transistor), namely, a metal/p-type layer junction of the p-type grid E-HEMT power device is prepared into ohmic contact, one or a group of Schottky diodes are prepared in the chip, and the Schottky diodes are connected in series with a grid of the p-type grid E-HEMT power device in a matching way so as to limit the electric leakage of the grid, improve the forward breakdown voltage, prolong the service life and stability of the grid and the like, and finally realize the III-nitride semiconductor enhanced HEMT with high reliability and stability.

The technical scheme, implementation process, principle and the like are further explained as follows. It is to be understood that within the scope of the present invention, the above-described features of the present invention and those specifically described in the following (embodiments) may be combined with each other to constitute new or preferred embodiments. Is limited to a space and will not be described in detail herein.

Some embodiments of the present invention provide a gate reinforcement structure of a group III nitride based enhanced HEMT comprising a source, a drain, a gate, and a group III nitride semiconductor structure, the source and drain being electrically connected by a carrier channel formed within the group III nitride semiconductor structure; the grid reinforcing structure further comprises a cathode of a Schottky diode, and the Schottky diode and the enhanced HEMT are monolithically integrated and electrically isolated from each other; and the cathode of the Schottky diode forms ohmic contact with the III-nitride semiconductor structure and is electrically connected with the grid electrode, and the anode of the Schottky diode forms Schottky contact with the III-nitride semiconductor structure.

In one embodiment, the group III nitride semiconductor structure includes a first semiconductor, a second semiconductor, and a third semiconductor stacked in order along a first direction, the first semiconductor and the second semiconductor having different bandgaps, and the carrier channel is formed by a junction between the first semiconductor and the second semiconductor, the third semiconductor being capable of depleting carriers within a corresponding region of the junction.

In some cases, the source, drain, and cathode may be considered to form ohmic contacts with the carrier channel.

In some cases, the anode forms a schottky contact with the carrier channel.

In one embodiment, the third semiconductor is disposed between the gate and the second semiconductor, and the gate forms an ohmic contact with the third semiconductor.

In one embodiment, the gate region of the second semiconductor is formed with a first groove, a partial region of a third semiconductor located between the gate and the second semiconductor is filled into the first groove, and a depth of the first groove in the first direction is smaller than a thickness of the second semiconductor, that is, a distance between the first groove and the first semiconductor is greater than 0. The first direction may be a growth direction of the group III nitride semiconductor structure or may be considered a thickness direction of the group III nitride semiconductor structure. If the third semiconductor is a P-GaN layer and the second semiconductor is an AlGaN barrier layer, a P-type recessed gate structure is actually formed in this embodiment, and since the AlGaN barrier layer below the P-GaN layer is thinner than the non-gate region, the channel electron concentration is relatively lower, so that an enhancement device is more easily formed, and the threshold voltage is increased; and the channel electron concentration of the non-grid region is higher, so that the relatively lower on-resistance of the device can be ensured.

In one embodiment, the anode comprises a first anode and a second anode, and the second anode is located between the first anode and the cathode in the second direction, the first anode being electrically connected to the second anode, the second direction being perpendicular to the first direction.

In one embodiment, the third semiconductor is disposed between the second anode and the second semiconductor. On one hand, the structure can realize the rectifying function of the Schottky diode, and on the other hand, in the epitaxial growth and technological preparation process, the structure is consistent with that of the p-GaN HEMT, so that the operation steps are simpler and more convenient.

In one embodiment, a second groove is further formed on the second semiconductor, and a local area of the third semiconductor located between the second anode and the second semiconductor is filled into the second groove. The device structure can further improve the threshold voltage of the device while ensuring the lower on-resistance of the device.

In one embodiment, a third groove is further formed on the second semiconductor, and a local area of the second anode is filled into the third groove. The design can make the leakage current of the diode smaller, and is more beneficial to exerting the rectification characteristic of the diode.

The depths of the second groove and the third groove in the first direction are smaller than the thickness of the second semiconductor, namely, the distances between the second groove and the third groove and the first semiconductor are larger than 0.

In one embodiment, the schottky diode and the enhancement HEMT are electrically isolated from each other by an isolation region that is distributed within the ill-nitride semiconductor structure. The isolation region may be formed by ion implantation or the like, or may be formed by mechanical etching, dry etching, wet etching or the like, and is not limited thereto.

Preferably, the isolation region is a high-resistance region formed by performing ion implantation treatment on a selected region of the group III nitride semiconductor structure. The depth of the ion implantation preferably reaches below the bottom end surface of the first semiconductor, and the type, energy, dosage and the like of the adopted ions can be determined according to actual requirements. For example, suitable ions may be selected from ions of elements such as helium, nitrogen, fluorine, magnesium, aluminum, argon, and the like, and are not limited thereto.

Some embodiments of the present invention also provide a method for fabricating a gate reinforcement structure of a group III nitride based enhanced HEMT, comprising the steps of fabricating an enhanced HEMT comprising a source, a drain, a gate, and a group III nitride semiconductor structure, the source and drain being electrically connected by a carrier channel formed within the group III nitride semiconductor structure; the manufacturing method further comprises the step of manufacturing a Schottky diode monolithically integrated with the enhanced HEMT, wherein the Schottky diode and the enhanced HEMT are electrically isolated from each other; the schottky diode has an anode and a cathode, the cathode forming an ohmic contact with the group III nitride semiconductor structure and being electrically connected to the gate, the anode forming a schottky contact with the group III nitride semiconductor structure.

In one embodiment, the step of fabricating an enhanced HEMT comprises:

Sequentially growing a first semiconductor, a second semiconductor and a third semiconductor on a substrate to obtain the III-nitride semiconductor structure, wherein the first semiconductor and the second semiconductor have different band gaps, the carrier channel is formed by a junction between the first semiconductor and the second semiconductor, and the third semiconductor can deplete carriers in a corresponding region of the junction;

And manufacturing a source electrode, a drain electrode and a grid electrode, wherein the source electrode, the drain electrode and the grid electrode all form ohmic contact with the III-nitride semiconductor structure, the third semiconductor is arranged between the grid electrode and the second semiconductor, and the grid electrode and the third semiconductor form ohmic contact.

In one embodiment, the step of fabricating the enhanced HEMT further comprises:

Forming a first groove in a gate region of the second semiconductor, growing a third semiconductor on the gate region of the second semiconductor, filling a local area of the third semiconductor into the first groove, and manufacturing the grid on the third semiconductor, wherein the depth of the first groove is smaller than the thickness of the second semiconductor.

In one embodiment, the step of fabricating the schottky diode further includes:

forming a second groove on the second semiconductor, growing a third semiconductor on the area of the second semiconductor surface distributed with the second groove, filling the local area of the third semiconductor into the second groove, then manufacturing a second anode on the third semiconductor,

Or forming a third groove on the second semiconductor, manufacturing a second anode on the area of the second semiconductor surface, in which the third groove is distributed, and filling a local area of the second anode into the third groove;

and manufacturing a first anode and a cathode on the III-nitride semiconductor structure, and electrically connecting at least the first anode and the second anode to form the anode, wherein the depth of the second groove and the depth of the third groove are smaller than the thickness of the second semiconductor, and the second anode is positioned between the first anode and the cathode in the direction perpendicular to the thickness direction of the III-nitride semiconductor structure.

In one embodiment, the manufacturing method specifically includes: the anode is brought into schottky contact with the carrier channel.

In one embodiment, the manufacturing method specifically includes: and forming an isolation region in the III-nitride semiconductor structure at least through an ion implantation mode, so that the Schottky diode and the enhanced HEMT are electrically isolated.

Some embodiments of the present invention also provide a group III nitride based enhanced HEMT comprising: monolithically integrated enhancement HEMTs and schottky diodes; and a gate reinforcing structure of the III-nitride-based enhanced HEMT.

In the above embodiments of the present invention, the first semiconductor may be selected from group III nitride materials having a smaller forbidden band width, such as GaN, etc., and the second semiconductor may be selected from group III nitride materials having a larger forbidden band width, such as AlGaN, alInN, alInGaN, etc. In some cases, the first semiconductor and the second semiconductor are also defined as a channel layer and a barrier layer, respectively, and both can form a heterojunction, in which a two-dimensional electron gas (2 DEG) is formed, i.e., the carrier channel.

In the above embodiments of the present invention, the third semiconductor may be a P-type semiconductor material, such as P-InGaN, P-AlGaN, P-AlInN, P-AlInGaN, etc., and is not limited thereto.

In the above embodiments of the present invention, the group III nitride semiconductor structure may be grown using HVPE (hydride vapor phase epitaxy), MOCVD (metal organic chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), or the like, without being limited thereto.

In the above embodiments of the present invention, the source electrode, the drain electrode, the gate electrode, the anode electrode, the cathode electrode, etc. may be made of a metal or an alloy thereof, evaporation, sputtering, etc. as is common in the art.

In the above embodiments of the present invention, the group III nitride semiconductor structure may include other structural layers such as a transition layer, a buffer layer, a high-resistance layer, a space layer, etc., which are conventional in the art, in addition to the aforementioned first, second, and third semiconductors, and is not limited thereto.

In the above embodiments of the present invention, the substrate includes, but is not limited to, any one or a combination of a silicon substrate, a sapphire substrate, a silicon carbide substrate, a GaN substrate, an AlN substrate, such as a composite substrate thereof.

It should be noted that, in the present invention, the method for manufacturing the group III nitride-based enhanced HEMT and the gate reinforcement structure thereof may further include other pre-process and post-device processing processes that are conventional in the art, such as epitaxial wafer cleaning, surface treatment, etc. in the pre-process, and mesa etching in the post-process, etc., and is not limited thereto.

Referring to fig. 2-4, in one embodiment of the present invention, a method for fabricating a group III nitride based enhanced HEMT of an on-chip integrated diode may include the steps of:

S1, an epitaxial structure of a group III nitride based enhancement HEMT is grown on a substrate 101, and specifically includes a transition layer 102, a high-resistance buffer layer 103, a channel layer 104, a barrier layer 105, and a p-type (A1) GaN layer 106, as shown in fig. 2. Note that the epitaxial substrate 101 may be a silicon substrate, a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, an aluminum nitride substrate, or a composite substrate or the like. The epitaxial growth method can be selected from Metal Organic Chemical Vapor Deposition (MOCVD), molecular Beam Epitaxy (MBE), hydride Vapor Phase Epitaxy (HVPE), etc. The channel layer 104 may be GaN or the like. The barrier layer 105 may be AlGaN, alInN, alInGaN, or the like. The p-type (A1) GaN layer 106 may be p-GaN, p-InGaN, p-AlGaN, p-AlInN, or p-AlInGaN, etc. The p-type (A1) GaN layer 106 may be directly epitaxial on the AlGaN/GaN heterostructure or secondarily epitaxial on the gate trench patterned AlGaN/GaN heterostructure.

S2, after the step S1 is completed, the grid region of the p-type (A1) GaN layer 106 is subjected to photoetching patterning, the p-type (A1) GaN in the non-grid region is removed by adopting a dry etching method and the like, and etching is stopped on the surface of the AlGaN barrier layer 105, so that a p-type grid is prepared, and the p-type grid is shown in FIG. 3. The non-gate region of the AlGaN barrier layer 105 surface may then be subjected to a surface treatment in a conventional manner to remove the surface oxide and damage layers.

And S3, after the step S2 is completed, depositing metal in the corresponding areas of the source electrode 108 and the drain electrode 109 of the p-GaN E-HEMT and the corresponding area of the cathode 110 of the Schottky diode SBD, and annealing to prepare ohmic contact. And respectively depositing metal in a region corresponding to a grid electrode 107 of the p-GaN E-HEMT and a region corresponding to an anode 111 of the Schottky diode SBD, preparing an ohmic contact by a grid electrode contact of the p-GaN E-HEMT after annealing, and preparing a Schottky contact by an anode contact of the SBD. Then, an interconnection metal is deposited, and the gate 107 of the p-GaN E-HEMT is in contact and communication with the cathode 110 of the SBD, so that a series relationship is formed between the SBD and the gate of the p-GaN E-HEMT. Further, an isolation region 112 may be formed between the SBD and the p-GaN E-HEMT structure by ion implantation or the like, forming an on-chip integrated structure, as shown in FIG. 4.

It should be noted that the above solution may further include further subsequent device processing technologies, such as performing a surface passivation layer on the AlGaN barrier layer 105, and further depositing a metal preparation field plate structure on the source electrode 108, which are well known to those skilled in the art and are not described herein.

In the above embodiment of the invention, the gate metal of the p-GaN E-HEMT is prepared into ohmic contact, so that no potential barrier exists between the metal and the p-GaN, the formation of a high electric field in a p-GaN surface depletion region caused by reverse bias of a Schottky junction can be avoided, and the activation of a defect state of a gate region and a new defect state generated by acceleration of collision ionization of the high electric field are reduced. Meanwhile, a Schottky diode (or a group of Schottky diodes) with stable electric leakage under reverse bias voltage and the electric leakage level matched with the grid electrode of the p-GaN E-HEMT power device is prepared in a chip. SBD reverse bias under the positive grid voltage, the electric leakage still keeps a lower level but is enough to open the 2DEG in the channel below, and the grid voltage resistance of the device is improved while high-performance grid control is realized.

Regarding the aspect of static reliability, firstly, since metal and unintentional doped AlGaN form Schottky contact, the crystal quality of the AlGaN epitaxial layer is much higher than that of the doped p-GaN layer, and the Schottky junction (or the hybrid anode diode with equivalent structure) formed by metal/AlGaN/GaN has higher stability and reliability; secondly, because the schottky junction formed by metal/AlGaN/GaN essentially belongs to n-type schottky contact, majority carriers are electrons, the effective mass is lighter, and the problem of grid degradation caused by activation and generation of defect states can be avoided in the process of high-speed movement, so that the service life of a grid of the device and the stability of the grid can be further enhanced.

The technical scheme of the invention is further described in detail below through examples and with reference to the accompanying drawings. However, the examples are chosen to illustrate the invention only and are not intended to limit the scope of the invention.

Embodiment 1 the structure of the group III nitride based enhanced HEMT of the on-chip integrated diode provided in this embodiment can refer to fig. 4, and the manufacturing method thereof includes the following steps:

S1, a metal organic vapor deposition (MOCVD) method is adopted to deposit a C-doped Al _0.07Ga_0.93 N high-resistance voltage-resistant layer 103 with the thickness of about 300nmAlN/GaN transition layer structure 102 on a Si <111> substrate 101, then the C-doped Al _0.07Ga_0.93 N high-resistance voltage-resistant layer 103 with the thickness of about 4 mu m, an unintentionally doped GaN channel layer 104 with the thickness of about 150nm and the low electron concentration, an Al _0.25Ga_0.75 N barrier layer 105 with the thickness of about 20nm and a p-GaN layer 106 with the Mg doping concentration of 2-3 multiplied by 10 ¹⁹/cm³ with the thickness of about 100nm are epitaxially deposited.

S2, after the step S1 is completed, photoresist is used as a mask, the p-GaN layer 106 of the non-grid region is removed by utilizing an Inductively Coupled Plasma (ICP) etching method after photoetching and patterning, and etching is stopped at the AlGaN barrier layer 105.

And S3, removing the photoresist by using an organic cleaning method such as acetone after the step S2 is completed, and testing to obtain the gate with the height of 100nm. And then removing the surface oxide layer of the AlGaN barrier layer by using hydrofluoric acid (HF) and the like, and rapidly annealing for a period of time in an N ₂ atmosphere at the temperature of about 500 ℃ to recover the two-dimensional electron gas at the AlGaN/GaN heterojunction. And depositing Ti/Al/Ti/Au (thickness is about 20/130/50/150 nm) in the corresponding areas of the source electrode 108 and the drain electrode 109 of the p-GaN E-HEMT and the corresponding area of the cathode 110 of the SBD, and annealing in inert atmosphere at about 890 ℃ to prepare ohmic contact. Ni/Au (thickness about 50/150 nm) is deposited on the corresponding region of the gate 107 of the p-GaN E-HEMT and the corresponding region of the anode 111 of the SBD, respectively, and after annealing, the gate 107 of the p-GaN E-HEMT forms ohmic contact, and the anode 111 of the SBD forms Schottky contact. The gate 107 of the p-GaN E-HEMT and the cathode 110 of the SBD are contacted and connected in series with metal in the chip. An isolation region 112 is formed by ion implantation to isolate the p-GaN E-HEMT from the active region of the Schottky diode.

The device finally prepared by the embodiment is tested for gate leakage current, gate life, gate failure and the like by adopting methods such as I-V, I-t and the like. Test results show that in this embodiment, after the diode is integrated in the enhancement mode HEMT chip, the gate breakdown voltage is increased to 40V, the operating voltage (V _OP) of 0.1% of the devices in 10 years of operation can reach 20V, and V _OP of the existing p-GaN E-HEMT is only <8V. From this, it can be demonstrated that the group III nitride-based enhanced HEMT prepared in this embodiment has very high gate reliability and stability.

Embodiment 2 the structure of a group III nitride based enhanced HEMT of an on-chip integrated diode provided in this embodiment can be referred to as fig. 5, which includes a group III nitride semiconductor structure, a source 208, a drain 209 and a gate 207 that cooperate with the group III nitride semiconductor structure to form a p-GaN E-HEMT, and an anode 211 and a cathode 210 that cooperate with the group III nitride semiconductor structure to form a schottky diode. I.e., the p-GaN E-HEMT is monolithically integrated with the schottky diode. The III-nitride semiconductor structure includes a transition layer 202, a high-resistance voltage-resistant layer 203, a channel layer 204, and a barrier layer 205, which are sequentially grown on a substrate 201. A recess is etched under the gate region of the barrier layer 205, and a secondary epitaxial p-GaN layer 206 fills in the recess. The source 208, drain 209, and SBD cathode 210 of the p-GaN E-HEMT are fabricated as ohmic contacts. The gate 207 of the p-GaN E-HEMT forms an ohmic contact, and the anode 211 of the SBD forms a Schottky contact. The gate is electrically connected to the cathode, the p-GaN E-HEMT is connected in series with the Schottky diode chip, and an isolation region 212 of the p-GaN E-HEMT and the Schottky diode is formed in the III-nitride semiconductor structure by ion implantation.

A method for manufacturing the III-nitride-based enhanced HEMT comprises the following steps:

S1, an AlN/GaN transition layer 202 with the thickness of about 300nm is grown on a Si <111> substrate 201 by adopting a metal organic vapor deposition (MOCVD) method, and then an Al0.07Ga0.93N high-resistance pressure-resistant layer 203 with the thickness of about 4 mu m C doped, an unintentionally doped GaN channel layer 204 with the thickness of about 150nm and an Al _0.25Ga_0.75 N barrier layer 205 with the thickness of about 50nm are sequentially grown.

S2, after the step S1 is completed, photoresist is used as a mask, the gate region of the barrier layer is partially removed by utilizing an ICP etching method after photoetching and patterning, a groove with the depth of about 35nm is formed, and after wet surface treatment and MOCVD high-temperature heat treatment, the p-type GaN layer 206 with the Mg doping concentration of 2-3 multiplied by 1019/cm ³ is subjected to secondary epitaxy with the thickness of about 100 nm.

And S3, removing the photoresist by adopting an organic cleaning method such as acetone after the step S2 is completed, and testing to obtain the gate with the height of 100nm. And then removing the surface oxide layer of the barrier layer by using hydrofluoric acid (HF) and the like, and rapidly annealing for a period of time in an atmosphere of N ₂ at the temperature of about 500 ℃ to recover the two-dimensional electron gas at the AlGaN/GaN heterojunction. Ti/Al/Ti/Au (about 20/130/50/150nm thick) is deposited in the corresponding regions of the source electrode 208 and the drain electrode 209 of the p-GaN E-HEMT and the corresponding region of the cathode 210 of the SBD, and the ohmic contact is prepared after annealing in an inert atmosphere at about 890 ℃. Ni/Au (about 50/150nm thick) is deposited on the gate 207 of the p-GaN E-HEMT and the corresponding region of the anode 211 of the SBD, respectively, and after annealing, the gate 207 of the p-GaN E-HEMT forms an ohmic contact, while the anode 211 of the SBD forms a Schottky contact. The gate 207 of the p-GaN E-HEMT and the cathode 210 of the SBD are connected in series with interconnect metal in the chip. And carrying out active region isolation on the p-GaN E-HEMT and the Schottky diode by utilizing ion implantation.

The test of gate leakage current, gate service life, gate failure and the like is carried out on the prepared device by adopting the method of I-V, I-t and the like, and the result proves that the III-nitride-based enhanced HEMT prepared by the embodiment also has high gate reliability and stability.

Embodiment 3 the structure of a group III nitride based enhanced HEMT of an on-chip integrated diode provided in this embodiment can be referred to as fig. 6, which includes a group III nitride semiconductor structure, a source 308, a drain 309 and a gate 307 of a p-GaN E-HEMT formed in cooperation with the group III nitride semiconductor structure, and an anode and a cathode 310 of a schottky diode formed in cooperation with the group III nitride semiconductor structure. The p-GaN E-HEMT is monolithically integrated with the Schottky diode. The anode is a combined anode formed by electrically connecting the second anode 311A and the first anode 311B through the interconnection metal 311C, and the anodes 311A and 311B are also respectively used as the source electrode and the gate electrode of the other p-GaN E-HEMT, so the schottky diode can also be called as a hybrid anode diode. The group III nitride semiconductor structure includes a transition layer 302, a high-resistance voltage-resistant layer 303, a channel layer 304, a barrier layer 305, and a p-GaN layer, which are sequentially grown on a substrate 301. The p-GaN layer includes a first portion 306A and a second portion 306B, the first portion 306A being located under the gate 307, the second portion 306B being located under the second anode 311A. The first anode 311B forms a schottky contact with the 2DEG formed at the interface of the channel layer 404 and the barrier layer 405. The gate is electrically connected to the cathode, the p-GaN E-HEMT is connected in series with the schottky diode, and an isolation region 312 between the p-GaN E-HEMT and the schottky diode is formed in the group III nitride semiconductor structure by ion implantation.

S1, growing an AlN/GaN transition layer 302 with the thickness of about 300nm on a Si <111 > substrate 301 by adopting a metal organic vapor deposition (MOCVD) method, then sequentially growing a C-doped Al _0.07Ga_0.93 N high-resistance voltage-resistant layer 303 with the thickness of about 4 mu m, a high-quality low-electron-concentration unintended doped GaN channel layer 304 with the thickness of about 150nm, an Al _0.25Ga_0.75 N barrier layer 305 with the thickness of about 20nm and a p-GaN layer with the Mg doping concentration of 2-3 multiplied by 101 ⁹/cm³ with the thickness of about 100 nm.

S2, after the step S1 is completed, photoresist is used as a mask, and after photoetching and patterning, an Inductively Coupled Plasma (ICP) etching method is used for removing the p-GaN layer in the non-grid region, so that etching is stopped at the AlGaN barrier layer 305.

And S3, removing the photoresist by adopting an organic cleaning method such as acetone after the step S2 is completed, and testing to obtain the gate with the height of 100nm. And then removing the surface oxide layer of the AlGaN barrier layer by using hydrofluoric acid (HF) and the like, and rapidly annealing for a period of time in an N ₂ atmosphere at the temperature of about 500 ℃ to recover the two-dimensional electron gas at the AlGaN/GaN heterojunction. Ti/Al/Ti/Au (about 20/130/50/150nm thick) is deposited on the corresponding regions of the source 308 and drain 309 of the p-GaN E-HEMT and the corresponding regions of the cathode 310 and first anode 311B of the Schottky diode, and the ohmic contact is formed after annealing in an inert atmosphere at about 890 ℃. Ni/Au (with the thickness of about 50/150 nm) is respectively deposited in a corresponding region of the grid 307 of the p-GaN E-HEMT and a corresponding region of the second anode 311A of the Schottky diode, the grid 307 forms ohmic contact after annealing, and the second anode 311A is prepared into Schottky contact. The second anode 311A and the first anode 311B are connected using a Ni/Au interconnection metal 311C to form an anode of a hybrid anode diode. The gate 307 of the p-GaN E-HEMT is contacted with the cathode 310 of the hybrid anode diode, and is connected in series with metal in the chip. And carrying out active region isolation on the p-GaN E-HEMT and the mixed anode diode by utilizing ion implantation.

Embodiment 4 the structure of a group III nitride based enhanced HEMT of an on-chip integrated diode provided in this embodiment can be referred to as fig. 7, which includes a group III nitride semiconductor structure, a source 408, a drain 409 and a gate 407 of a p-GaN E-HEMT formed in cooperation with the group III nitride semiconductor structure, and an anode 411 and a cathode 410 of a schottky diode formed in cooperation with the group III nitride semiconductor structure. The p-GaN E-HEMT is monolithically integrated with the Schottky diode. The group III nitride semiconductor structure includes a transition layer 402, a high-resistance voltage-resistant layer 403, a gan channel layer 404, and an AlGaN barrier layer 405, which are sequentially grown on a substrate 401. A recess is etched under the gate region of the barrier layer 405 and a secondary epitaxial p-GaN layer 406 fills the recess. The source 408, drain 409, and SBD cathode 410 of the p-GaN E-HEMT are fabricated as ohmic contacts. The p-GaN E-HEMT gate 407 forms an ohmic contact, and the SBD anode 411 forms a Schottky contact with the 2DEG formed at the interface of the channel layer 404 and the barrier layer 405. The gate is electrically connected to the cathode, the p-GaN E-HEMT is connected in series with the Schottky diode, and an isolation region 412 of the p-GaN E-HEMT and the Schottky diode is formed in the III-nitride semiconductor structure by ion implantation.

The group III nitride-based enhanced HEMT can be manufactured by the method of example 2 and example 3.

Embodiment 5 the structure of a group III nitride based enhanced HEMT of an on-chip integrated diode provided in this embodiment can be referred to as fig. 8, which includes a group III nitride semiconductor structure, a source 508, a drain 509 and a gate 507 that cooperate with the group III nitride semiconductor structure to form a p-GaN E-HEMT, and an anode and a cathode 510 that cooperate with the group III nitride semiconductor structure to form a schottky diode. The p-GaN E-HEMT is monolithically integrated with the Schottky diode. The schottky diode may also be referred to as a hybrid anode diode in which the anode is a combined anode formed by electrically connecting the second anode 511A and the first anode 511B through the interconnection metal 511C. The group III nitride semiconductor structure includes a transition layer 502, a high-resistance voltage-resistant layer 503, a GaN channel layer 504, an AlGaN barrier layer 505, and a p-GaN layer 506, which are sequentially grown on a substrate 501. The barrier layer 505 is further etched in a region under the second anode 511A to form a groove in which the second anode 511A is filled. The source 508, drain 509, SBD cathode 510 of the p-GaN E-HEMT are fabricated as ohmic contacts. The p-GaN E-HEMT gate 507 forms an ohmic contact and the first anode 511B forms a schottky contact with the 2DEG formed at the interface of the channel layer 504 and the barrier layer 505. The gate is electrically connected to the cathode, the p-GaN E-HEMT is connected in series with the Schottky diode, and an isolation region 512 of the p-GaN E-HEMT and the Schottky diode is formed in the III-nitride semiconductor structure by ion implantation.

The group III nitride-based enhanced HEMT can be manufactured by the method of example 2 or example 3.

Embodiment 6 the structure of a group III nitride based enhanced HEMT of an on-chip integrated diode provided in this embodiment can be referred to as fig. 9, which includes a group III nitride semiconductor structure, a source 608, a drain 609 and a gate 607 that cooperate with the group III nitride semiconductor structure to form a p-GaN E-HEMT, and an anode and a cathode 610 that cooperate with the group III nitride semiconductor structure to form a schottky diode. The p-GaN E-HEMT is monolithically integrated with the Schottky diode. The schottky diode may also be referred to as a hybrid anode diode in which the anode is a combined anode formed by electrically connecting the second anode 611A and the first anode 611B through the interconnect metal 611C. The group III nitride semiconductor structure includes a transition layer 602, a high-resistance voltage-resistant layer 603, a gan channel layer 604, and an AlGaN barrier layer 605 grown in this order on a substrate 601. The barrier layer 605 is etched at two portions to form a recess, and a p-GaN layer is secondarily epitaxially grown, wherein the p-GaN layer first portion 606A and the second portion 606B are respectively filled in the corresponding recesses. The source 608, drain 609 and cathode 610 of the p-GaN E-HEMT and SBD are fabricated as ohmic contacts. The gate 607 of the p-GaN E-HEMT forms an ohmic contact and the first anode 611B forms a schottky contact with the 2DEG formed at the interface of the channel layer 604 and the barrier layer 605. The gate is electrically connected to the cathode, the p-GaN E-HEMT is connected in series with the schottky diode, and an isolation region 612 of the p-GaN E-HEMT and the schottky diode is formed in the group III nitride semiconductor structure by ion implantation.

The group III nitride-based enhanced HEMT can be manufactured by the methods of examples 2,3, and 4.

Referring to the mode of examples 1-3, tests such as gate leakage current, gate service life and gate failure are performed on the group III nitride based enhanced HEMT devices prepared in examples 4-6 by adopting methods such as I-V, I-t, and the results also show that the devices have very high gate reliability and stability.

According to the embodiment of the invention, the ohmic contact type p-GaN grid is connected with the Schottky diode with controllable leakage level, high withstand voltage and high reliability in series, firstly, the ohmic contact can be utilized to avoid the high electric field formed on the p-GaN surface layer, the problems of low breakdown voltage caused by carrier tunneling, unstable grid caused by defect activation and the like are avoided, the junction degradation formed by grid metal and the p-GaN layer is effectively prevented, secondly, the Schottky diode is connected in series at the grid, and the inhibition effect of the reverse bias Schottky junction on grid leakage under positive grid voltage can be kept, so that the reverse bias Schottky junction is in a stable leakage level in a very high voltage range. The high-reliability metal/p-GaN ohmic contact is connected in series with the high-withstand voltage high-reliability on-chip Schottky diode, so that the problems of low breakdown voltage, short service life of a grid electrode and the like caused by a metal/p-GaN Schottky junction can be effectively avoided, and finally, the reliability of the device under forward bias is obviously improved.

It should be understood that the above embodiments are merely for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the present invention and implement the same according to the present invention without limiting the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.

Claims

1. A gate reinforcement structure of a group III nitride based enhanced HEMT, the enhanced HEMT comprising a source, a drain, a gate, and a group III nitride semiconductor structure, the source and drain being electrically connected by a carrier channel formed within the group III nitride semiconductor structure; the method is characterized in that: the grid reinforcing structure further comprises a cathode of a Schottky diode, and the Schottky diode and the enhanced HEMT are monolithically integrated and electrically isolated from each other; and the cathode of the Schottky diode forms ohmic contact with the III-nitride semiconductor structure and is electrically connected with the grid electrode, and the anode of the Schottky diode forms Schottky contact with the III-nitride semiconductor structure.

2. The gate reinforcing structure of the group III nitride based enhanced HEMT of claim 1, wherein: the group III nitride semiconductor structure includes a first semiconductor, a second semiconductor, and a third semiconductor stacked in order along a first direction, the first semiconductor and the second semiconductor having different band gaps, and the carrier channel being formed by a junction between the first semiconductor and the second semiconductor, the third semiconductor being capable of depleting carriers within a corresponding region of the junction.

3. The gate reinforcing structure of the group III nitride based enhanced HEMT of claim 2, wherein:

the third semiconductor is arranged between the grid electrode and the second semiconductor, and ohmic contact is formed between the grid electrode and the third semiconductor;

And/or a gate region of the second semiconductor is formed with a first groove, a local region of a third semiconductor located between the gate and the second semiconductor is filled into the first groove, and a depth of the first groove is smaller than a thickness of the second semiconductor in the first direction;

and/or the anode forms a schottky contact with the carrier channel.

4. The gate reinforcing structure of the group III nitride based enhanced HEMT of claim 2, wherein: the anode comprises a first anode and a second anode, and the second anode is positioned between the first anode and the cathode in the second direction, the first anode is electrically connected with the second anode, and the second direction is perpendicular to the first direction;

And/or the third semiconductor is arranged between the second anode and the second semiconductor;

And/or a second groove is further formed on the second semiconductor, a local area of a third semiconductor located between the second anode and the second semiconductor is filled into the second groove, or a third groove is further formed on the second semiconductor, the local area of the second anode is filled into the third groove, and the depths of the second groove and the third groove in the first direction are smaller than the thickness of the second semiconductor.

5. The gate reinforcing structure of the group III nitride-based enhanced HEMT of any one of claims 1-4, wherein: the schottky diode and the enhanced HEMT are electrically isolated from each other by an isolation region that is distributed within the group III nitride semiconductor structure.

6. A manufacturing method of a gate reinforcement structure of a III nitride-based enhanced HEMT comprises the steps of manufacturing the enhanced HEMT, wherein the enhanced HEMT comprises a source electrode, a drain electrode, a gate electrode and a III nitride semiconductor structure, and the source electrode and the drain electrode are electrically connected through a carrier channel formed in the III nitride semiconductor structure; the manufacturing method is characterized by further comprising the step of manufacturing a Schottky diode monolithically integrated with the enhanced HEMT, wherein the Schottky diode and the enhanced HEMT are electrically isolated from each other; the schottky diode has an anode and a cathode, the cathode forming an ohmic contact with the group III nitride semiconductor structure and being electrically connected to the gate, the anode forming a schottky contact with the group III nitride semiconductor structure.

7. The method of manufacturing according to claim 6, wherein the step of manufacturing the enhanced HEMT comprises:

8. The method of manufacturing according to claim 7, wherein the step of manufacturing the enhanced HEMT further comprises:

forming a first groove in a gate region of the second semiconductor, growing a third semiconductor on the gate region of the second semiconductor, filling a local area of the third semiconductor into the first groove, and manufacturing the gate on the third semiconductor, wherein the depth of the first groove is smaller than the thickness of the second semiconductor;

And/or, the step of manufacturing the schottky diode further comprises:

And manufacturing a first anode and a cathode on the III-nitride semiconductor structure, and electrically connecting at least the first anode and a second anode to form the anode, wherein the depth of each of the second groove and the third groove is smaller than the thickness of the second semiconductor, and the second anode is positioned between the first anode and the cathode in the direction perpendicular to the thickness direction of the III-nitride semiconductor structure;

Or forming the anode into schottky contact with the carrier channel.

9. The manufacturing method according to claim 6, characterized by comprising the following steps: and forming an isolation region in the III-nitride semiconductor structure at least through an ion implantation mode, so that the Schottky diode and the enhanced HEMT are electrically isolated.

10. A group III nitride based enhanced HEMT characterized by comprising: monolithically integrated enhancement HEMTs and schottky diodes; and, the gate reinforcing structure of the group III nitride-based enhanced HEMT of any one of claims 1-5.