CN118315381A

CN118315381A - Flexible gallium nitride power module and packaging method

Info

Publication number: CN118315381A
Application number: CN202410429282.0A
Authority: CN
Inventors: 王来利; 李大为; 孔航; 张虹
Original assignee: Shaoxing Tongyue Wideband Gap Semiconductor Research Institute; Xian Jiaotong University
Current assignee: Shaoxing Tongyue Wideband Gap Semiconductor Research Institute; Xian Jiaotong University
Priority date: 2024-04-10
Filing date: 2024-04-10
Publication date: 2024-07-09

Abstract

The invention belongs to the technical field of manufacturing of electric machinery and equipment and packaging of power devices, and particularly relates to a flexible gallium nitride power module and a packaging method thereof. The flexible gallium nitride power module comprises a substrate, a first conductive layer and a second conductive layer, wherein polyimide materials are filled between the first conductive layer and the second conductive layer to form a polyimide dielectric layer, and the first conductive layer is electrically connected with the second conductive layer through a plurality of welding spots; the GaN device is provided with at least two GaN devices, and is arranged on one side of the first conductive layer; the decoupling capacitor is provided with at least one and is arranged between two adjacent GaN devices; the first conductive layer is respectively connected with the GaN device and the decoupling capacitor through the interconnection welding layer; the decoupling capacitor forms a power loop with two GaN devices adjacent thereto. The invention mainly ensures the safe and efficient operation of the power module under high frequency and high power density from low packaging parasitic parameters and low chip stress, and solves the problem that the parasitic inductance is difficult to be further reduced in the existing packaging method.

Description

Flexible gallium nitride power module and packaging method

Technical Field

The invention belongs to the technical field of manufacturing of electric machinery and equipment and packaging of power devices, and particularly relates to a flexible gallium nitride power module and a packaging method thereof.

Background

Compared with silicon-based power semiconductors, the wide-bandgap power semiconductors represented by gallium nitride and silicon carbide have the advantages of high temperature resistance, high voltage resistance and high electron mobility, wherein the gallium nitride power device is particularly excellent in high-frequency electrical performance, and the improvement of the working frequency and the power density of a power electronic converter is greatly promoted. The higher switching speed of gallium nitride devices benefits from a smaller gate charge amount, but this also makes it more sensitive to parasitic parameters, which not only increase the switching losses of the device, but also cause serious electromagnetic interference problems. However, the existing packaging technology brings about larger parasitic parameters and stress problems, and limits the excellent characteristics of the wide bandgap power semiconductor, so that the gallium nitride power module packaging method with low parasitic parameters is very important for fully playing the excellent characteristics of the gallium nitride device.

Currently, gallium nitride power module packages mainly include packages based on conventional bonding wires, DBC/PCB hybrid packages, and gallium nitride chip embedded substrate packages. The bonding wire package introduces a larger parasitic inductance of the power circuit, so that a DBC/PCB hybrid package and a gallium nitride chip embedded substrate package are currently adopted. While DBC/PCB hybrid packages and embedded substrate type packages reduce parasitic inductance by reducing power loop area, it has been found in practical applications that both of these packaging methods are limited by copper layer spacing or ceramic substrate thickness, which parasitic inductance is difficult to further reduce.

Therefore, there is a need for a gallium nitride power module package structure that reduces parasitic parameters to very low levels to fully exploit the excellent high frequency performance of the device.

Disclosure of Invention

In order to solve the problem that the parasitic inductance of the conventional packaging method is difficult to reduce further due to the limitation of the copper layer spacing or the thickness of the ceramic substrate, the invention aims to provide a flexible gallium nitride power module with extremely low parasitic parameter and a packaging method thereof, which are suitable for but not limited to high-frequency high-power density application.

The invention mainly ensures the safe and efficient operation of the power module under high frequency and high power density from two aspects of low package parasitic parameters and low chip stress.

In order to achieve the above object, the technical scheme of the present invention is as follows.

A first aspect of the invention provides a flexible gallium nitride power module comprising:

The substrate comprises a first conductive layer and a second conductive layer, polyimide materials are filled between the first conductive layer and the second conductive layer to form a polyimide dielectric layer, and the first conductive layer is electrically connected with the second conductive layer through a plurality of welding spots 14;

a GaN device having at least two, disposed on one side of the first conductive layer;

A decoupling capacitor, having at least one, disposed between two adjacent GaN devices;

the first conductive layer is respectively connected with the GaN device and the decoupling capacitor through an interconnection welding layer; the decoupling capacitor forms a power loop with two adjacent GaN devices.

The power module of the invention improves the working performance and reliability of the power module mainly from two aspects of low package parasitic parameter and low chip thermal stress, thereby fully playing the excellent characteristics of high frequency, high temperature and high efficiency of the gallium nitride power semiconductor.

Compared with the packaging structure of the existing power module, the packaging structure of the power module greatly reduces the distance between the conducting layers, the thickness is far smaller than the thicknesses of the PCB FR4 and DBC substrates, the power circuit area is greatly reduced, parasitic inductance is reduced, and extremely low parasitic inductance packaging (< 0.1 nH) is realized, so that the excellent performance of the gallium nitride power device can be fully exerted.

From the aspect of low chip thermal stress, the flexible polyimide material adopted by the invention can play a role in stress release at high temperature, and can reduce the thermal stress on the gallium nitride chip.

In a preferred embodiment, the decoupling capacitors and the GaN devices are disposed on a first plane, the thickness direction of the substrate is perpendicular to the first plane, and the first plane is parallel to the plane of the first conductive layer.

The invention adopts a layout mode that the decoupling capacitor is arranged on the outer side of the substrate and the decoupling capacitor and the two GaN devices are positioned on the same horizontal plane, so the layout mode of the power loop of the power module mainly depends on the thickness of the substrate, and the thinner the substrate, the smaller the area of the power loop and the smaller the parasitic inductance of the power loop. Since the flexible material polyimide is adopted as the insulating medium between the conductive layers in the horizontal and vertical directions, the thickness of the polyimide is designed to be a thickness capable of ensuring the insulating property (generally in the range of 18-25 mu m, and the larger the thickness is, the more the insulating property can be ensured), and the thickness is far smaller than the thicknesses of the FR4 and DBC substrates of the PCB, thereby greatly reducing the area of a power loop, reducing parasitic inductance and realizing extremely low parasitic inductance packaging (< 0.1 nH).

In a preferred embodiment, the thickness of the polyimide dielectric layer between the first conductive layer and the second conductive layer is 18 to 25 μm. Examples thereof include 18 μm, 19 μm, 20 μm, 21 μm, 22 μm, 23 μm, 24 μm, 25 μm and the like. This thickness is related to its insulation and the parasitic inductance of the power loop. The invention adopts flexible polyimide as an insulating medium between two conductive layers, and the thickness is far smaller than that of a PCB FR4 and DBC substrate (for example, the thickness of a double-layer PCB board is 1.6 mm) because the thickness is 18-25 mu m, so that the thickness can be reduced to the parasitic inductance of a power loop under the condition of meeting the insulativity, and the extremely low parasitic inductance package (< 0.1 nH) is realized.

In a preferred embodiment, the first conductive layer and the second conductive layer are both made of copper. That is, both conductive layers are conductive copper layers.

In a preferred embodiment, a plurality of solder joints are disposed on the polyimide dielectric layer, each of the solder joints is configured as an interconnection solder ball, and the first conductive layer and the second conductive layer are electrically connected through a plurality of interconnection solder balls. For example, a plurality of through holes are distributed on the polyimide dielectric layer, and each through hole is filled with an interconnection solder ball so as to realize electrical connection between the first conductive layer and the second conductive layer. The interconnection solder balls play a role in electrical connection between the first conductive layer and the second conductive layer, and the material of the interconnection solder balls is solder.

In a preferred embodiment, the GaN device has two, and is denoted as a first GaN device and a second GaN device, respectively; the decoupling capacitance is configured between the first GaN device and the second GaN device.

In a preferred embodiment, the first conductive layer is partitioned by a polyimide material to form a first conductive unit, a second conductive unit, a third conductive unit and a fourth conductive unit, the second conductive unit is disposed inside the first conductive unit, and the fourth conductive unit is disposed inside the third conductive unit;

The second conductive layer is electrically connected with the second conductive unit and the fourth conductive unit which correspond to the second conductive layer through a plurality of welding spots respectively.

In a preferred embodiment, the first conductive unit and the third conductive unit are disposed in parallel at opposite side edges of the first conductive layer. Preferably, the first GaN device is disposed corresponding to the first conductive unit, and the second GaN device is disposed corresponding to the third conductive unit.

In a preferred embodiment, the second conductive unit has a plurality of; the fourth conductive unit has a plurality of. The second conductive unit and the fourth conductive unit are arranged in a staggered mode. Preferably, a second conductive unit is disposed between every two fourth conductive units.

In a preferred embodiment, the first source of the first GaN device is electrically connected to the first conductive unit through an interconnection solder layer, and the first drain of the first GaN device is electrically connected to the second conductive unit through an interconnection solder layer;

And a second source electrode of the second GaN device is electrically connected with the fourth conductive unit through an interconnection welding layer, and a second drain electrode of the second GaN device is electrically connected with the third conductive unit through an interconnection welding layer.

In a preferred embodiment, the decoupling capacitor is electrically connected to the first conductive unit and the third conductive unit respectively through an interconnection solder layer.

In a preferred embodiment, the flexible gallium nitride power module further includes an encapsulation housing, the encapsulation housing is disposed on the outer side of the first conductive layer, and forms a plurality of accommodating chambers with the first conductive layer, and the decoupling capacitors and the GaN devices are respectively disposed in the corresponding accommodating chambers.

In a preferred embodiment, the thickness of the package housing is greater than or equal to the thickness of the decoupling capacitance.

In a preferred embodiment, the material of the package housing is epoxy. The packaging shell is manufactured by an epoxy resin heating and curing process. The packaging shell is used for protecting the GaN device and providing mechanical support for the packaging structure, and the thickness of the packaging shell is consistent with that of the decoupling capacitor and can be larger than that of the decoupling capacitor so as to completely wrap the decoupling capacitor and the GaN device and provide better protection.

A second aspect of the present invention provides a packaging method of the flexible gallium nitride power module according to the first aspect, including the following steps:

arranging a welding spot array on one side of the second conductive layer facing the first conductive layer, then attaching the first conductive layer to the second conductive layer, and filling a polyimide dielectric layer between the first conductive layer and the second conductive layer to form a substrate;

And mounting a decoupling capacitor on the first conductive layer through an interconnection welding layer, and enabling the decoupling capacitor and two adjacent GaN devices to form a power loop.

In a preferred embodiment, further comprising: and forming a packaging shell on the surface of the first conductive layer by using a heat curing process so as to wrap the decoupling capacitor and the GaN device. Thereby playing a role in protecting GaN devices and circuits.

The invention has the beneficial effects that:

1. The packaging structure of the flexible gallium nitride power module mainly improves the working performance and reliability of the power module from two aspects of low packaging parasitic parameters and low chip thermal stress, thereby fully playing the excellent high-frequency, high-temperature and high-efficiency characteristics of the gallium nitride power semiconductor.

2. According to the invention, the decoupling capacitor is arranged on the outer side of the substrate and the decoupling capacitor and the two GaN devices are positioned on the same horizontal plane, meanwhile, polyimide which is a flexible material is used as an insulating medium between the conducting layers in the horizontal and vertical directions.

3. The flexible polyimide material adopted by the invention can play a role in releasing stress at high temperature, thereby reducing the thermo-mechanical stress of a GaN device, improving the working reliability and prolonging the service life of the flexible gallium nitride power module.

4. The flexible gallium nitride power module is a core device forming a power electronic converter, and the packaging method of the power module is suitable for all application occasions related to electric energy conversion, particularly in the field requiring higher switching frequency and power density of the device, can provide a bottom technical support for full electrochemical, miniaturization and high density of related devices or units, and promotes the development of national defense technology, data centers, new energy automobiles and other related field technologies.

Drawings

Fig. 1 is a schematic cross-sectional view of a flexible gallium nitride power module according to an embodiment of the invention.

Fig. 2 is a schematic diagram of a current commutation loop of a flexible gallium nitride power module according to an embodiment of the invention.

Fig. 3 is a schematic diagram of a flexible gallium nitride power module according to an embodiment of the invention.

Fig. 4 is a schematic diagram illustrating an overall structure of a flexible gan power module according to an embodiment of the invention.

Fig. 5 is a schematic top view of a first conductive layer according to an embodiment of the invention.

Fig. 6 is a schematic top view of a second conductive layer according to an embodiment of the invention.

In the figure: 1. a substrate; 11. a first conductive layer; 111. a first conductive unit; 112. a second conductive unit; 113. a third conductive unit; 114. a fourth conductive unit; 12. a second conductive layer; 121. a fifth conductive unit; 122. a sixth conductive unit; 123. a seventh conductive unit; 13. a polyimide dielectric layer; 14. welding spots;

2. a GaN device; 21. a first GaN device; 22. a second GaN device; 201. a first current; 202. a second current; 203. a third current;

3. decoupling the capacitor;

4. an interconnection welding layer; 41. a first interconnect layer; 42. a second interconnect layer; 43. a third interconnect layer; 44. a fourth interconnect layer; 45. a fifth interconnect layer; 46. a sixth interconnect layer;

5. a package housing; 6. and driving the pins.

Detailed Description

The present invention will be described in further detail with reference to the following examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It is noted that relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of a process or method comprising the element.

In the description of the present invention, the terms "mounted," "connected," "coupled," and "connected," as may be used broadly, and may be connected, for example, fixedly, detachably, or integrally, unless otherwise specifically defined and limited; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present invention can be understood by those skilled in the art in specific cases.

It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In addition, for numerical ranges in this disclosure, it is understood that each intermediate value between the upper and lower limits of the ranges is also specifically disclosed. Every smaller range between any stated value or stated range, and any other stated value or intermediate value within the stated range, is also encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range.

Since the adopted step method is the same as that of the embodiment, the invention describes a preferred embodiment for preventing redundancy. While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.

The technical solution of the present invention will be described in detail below for a clearer understanding of technical features, objects and advantageous effects of the present invention, but should not be construed as limiting the scope of the present invention.

The gallium nitride power device has high switching speed and is suitable for a high-frequency high-power density power electronic converter, however, the gallium nitride power device is more sensitive to parasitic parameters, and the existence of the parasitic parameters is very unfavorable for the normal operation of the device, influences the performance of the device, and even leads to the failure of the circuit to normally operate. For example, parasitic inductance and parasitic capacitance not only increase the switching losses of the device, but also cause serious electromagnetic interference problems. The prior packaging technology can bring about larger parasitic parameters and stress problems, and limits the excellent characteristics of the wide bandgap power semiconductor, so that the gallium nitride power module packaging method with extremely low parasitic parameters is very important for fully playing the excellent characteristics of the gallium nitride device.

Currently, gallium nitride power module packages mainly include packages based on conventional bonding wires, DBC/PCB hybrid packages, and gallium nitride chip embedded substrate packages. Bond wire packages introduce a large parasitic inductance of the power loop. DBC/PCB hybrid packages and embedded substrate type packages reduce parasitic inductance by reducing power loop area, but in practical applications it has been found that both packaging methods are limited by copper layer spacing or ceramic substrate thickness, which parasitic inductance is difficult to reduce further.

For example, the power loops embedded in the substrate-type package all employ a vertical structural layout, i.e., an inner conductive layer is employed as the power loop to reduce loop area and parasitic inductance. While vertical structure layout has proven to be an optimal loop layout, its limit of reducing parasitic inductance is limited by the copper layer spacing in the substrate, and the substrate employed by existing packaging methods generally has a larger copper layer spacing, so that it is difficult to further reduce the parasitic inductance.

In the DBC/PCB mixed packaging structure, because two sides of the gallium nitride chip are often welded on different materials, great difference of thermal expansion coefficients can generate great thermal mechanical stress on the chip, thereby influencing the reliability and service life of the chip. Meanwhile, the power loop area of the structure is limited by the thickness of the ceramic substrate, and parasitic inductance is difficult to continuously reduce.

Based on the above, the invention provides a gallium nitride power module packaging method, which can reduce parasitic parameters to an extremely low level and fully exert the excellent high-frequency performance of the device. The invention mainly ensures the safe and efficient operation of the power module under high frequency and high power density from two aspects of low package parasitic parameters and low chip stress.

Referring to fig. 1 and 4, an embodiment of the present invention provides a flexible gallium nitride power module, which includes a substrate 1, a GaN device 2, and a decoupling capacitor 3.

The substrate 1 comprises a first conductive layer 11 and a second conductive layer 12, a polyimide material is filled between the first conductive layer 11 and the second conductive layer 12 to form a polyimide dielectric layer 13, and the first conductive layer 11 is electrically connected with the second conductive layer 12 through a plurality of welding spots 14; the GaN device 2 has at least two and is disposed on one side of the first conductive layer 11; the decoupling capacitor 3 has at least one and is arranged between two adjacent GaN devices 2; the first conductive layer 11 is respectively connected with the GaN device 2 and the decoupling capacitor 3 through the interconnection welding layer 4; the decoupling capacitor 3 forms a power loop with its adjacent two GaN devices 2. Wherein at least one decoupling capacitor 3 is provided between two adjacent GaN devices 2.

Compared with the packaging structure of the existing power module, the packaging structure of the power module greatly reduces the distance between the conducting layers, the thickness is far smaller than the thicknesses of the PCB FR4 and the DBC substrate, the power circuit area is greatly reduced, parasitic inductance is reduced, and extremely low parasitic inductance packaging (< 0.1 nH) is realized, so that the excellent performance of the gallium nitride power device can be fully exerted.

In a preferred embodiment, the decoupling capacitors 3 and the GaN devices 2 are disposed on a first plane, the thickness direction of the substrate 1 is perpendicular to the first plane, and the first plane is parallel to the plane of the first conductive layer 11.

The invention adopts a layout mode that the decoupling capacitor 3 is arranged on the outer side of the substrate 1 and the decoupling capacitor 3 and the two GaN devices 2 are positioned on the same horizontal plane, so the layout mode of the power circuit of the power module mainly depends on the thickness of the substrate 1, and the thinner the thickness of the substrate 1, the smaller the area of the power circuit and the smaller the parasitic inductance of the power circuit. Since the flexible material polyimide is adopted as the insulating medium between the conductive layers in the horizontal and vertical directions, the thickness of the polyimide is designed to be a thickness capable of ensuring the insulating property (generally in the range of 18-25 mu m, and the larger the thickness is, the more the insulating property can be ensured), and the thickness is far smaller than the thicknesses of the FR4 and DBC substrates of the PCB, thereby greatly reducing the area of a power loop, reducing parasitic inductance and realizing extremely low parasitic inductance packaging (< 0.1 nH).

In a preferred embodiment, the polyimide dielectric layer between the first conductive layer 11 and the second conductive layer 12 has a thickness of 18 to 25 μm. Examples thereof include 18 μm, 19 μm, 20 μm, 21 μm, 22 μm, 23 μm, 24 μm, 25 μm and the like. This thickness is related to its insulation and the parasitic inductance of the power loop. The invention adopts flexible polyimide as an insulating medium between two conductive layers, and the thickness is far smaller than that of a PCB FR4 and DBC substrate (for example, the thickness of a double-layer PCB board is 1.6 mm) because the thickness is 18-25 mu m, so that the thickness can be reduced to the parasitic inductance of a power loop under the condition of meeting the insulativity, and the extremely low parasitic inductance package (< 0.1 nH) is realized.

In a preferred embodiment, the first conductive layer 11 and the second conductive layer 12 are both made of copper. That is, both conductive layers are conductive copper layers.

In a preferred embodiment, a plurality of solder joints 14 are disposed on the polyimide dielectric layer 13, each solder joint 14 being configured as an interconnection solder ball, and the first conductive layer 11 and the second conductive layer 12 being electrically connected by a plurality of interconnection solder balls. For example, a plurality of through holes are distributed on the polyimide dielectric layer 13, and each through hole is filled with an interconnection solder ball, so as to realize electrical connection between the first conductive layer 11 and the second conductive layer 12. The interconnect balls serve as electrical connections between the first conductive layer 11 and the second conductive layer 12, the material of the interconnect balls being solder.

For convenience in further explaining the power loop of the present invention, the following embodiments of the present invention enumerate specific connection relationships between two GaN devices and one decoupling capacitor to form the power loop, and describe the connection relationships of the power loop in detail.

In a preferred embodiment, as in fig. 1, gaN device 2 has two, and is denoted as first GaN device 21 and second GaN device 22, respectively; the decoupling capacitor 3 is arranged between the first GaN device 21 and the second GaN device 22.

In a preferred embodiment, the first conductive layer 11 is partitioned by a polyimide material to form a first conductive unit 111, a second conductive unit 112, a third conductive unit 113, and a fourth conductive unit 114, the second conductive unit 112 being disposed inside the first conductive unit 111, the fourth conductive unit 114 being disposed inside the third conductive unit 113; the second conductive layer 12 is electrically connected to the second conductive unit 112 and the fourth conductive unit 114 through a plurality of pads 14. Wherein the inner side of the first conductive unit 111, i.e., the side of the first conductive unit 111 near the third conductive unit 113, and the inner side of the third conductive unit 113, i.e., the side of the third conductive unit 113 near the first conductive unit 111. Thereby causing the second conductive unit 112 and the fourth conductive unit 114 to be disposed between the first conductive unit 111 and the third conductive unit 113.

In a preferred embodiment, the first conductive unit 111 and the third conductive unit 113 are disposed in parallel at opposite side edges of the first conductive layer 11. Preferably, the first GaN device 21 is disposed corresponding to the first conductive unit 111, and the second GaN device 22 is disposed corresponding to the third conductive unit 113.

In a preferred embodiment, the second conductive unit 112 has a plurality of; the fourth conductive unit 114 has a plurality of. Preferably, the second conductive unit 112 and the fourth conductive unit 114 are disposed in a staggered manner. Preferably, one second conductive unit 112 is disposed between every two fourth conductive units 114.

In a preferred embodiment, the interconnection solder layers 4 include a first interconnection solder layer 41, a second interconnection solder layer 42, a third interconnection solder layer 43, a fourth interconnection solder layer 44, a fifth interconnection solder layer 45, and a sixth interconnection solder layer 46. The first source of the first GaN device 21 is electrically connected to the first conductive unit 111 through the first interconnection solder layer 41, and the first drain of the first GaN device 21 is electrically connected to the second conductive unit 112 through the second interconnection solder layer 42; the second source of the second GaN device 22 is electrically connected to the fourth conductive unit 114 through the fourth interconnection solder layer 44, and the second drain of the second GaN device 22 is electrically connected to the third conductive unit 113 through the third interconnection solder layer 43.

In a preferred embodiment, the decoupling capacitor 3 is electrically connected to the first conductive element 111 and the third conductive element 113 respectively by the interconnect solder layer 4. Specifically, the decoupling capacitor 3 is electrically connected to the first conductive unit 111 through the fifth interconnection solder layer 45; the decoupling capacitor 3 is electrically connected to the third conductive element 113 through the sixth interconnect solder layer 46.

In one embodiment of the present invention, gaN device 2 is a gallium nitride chip. Of course, various power electronic converter topologies can be packaged, and the power electronic converter topology can be a half-bridge structure, a full-bridge structure and the like. The number of the gallium nitride chips to be packaged may be 2 or more. For example, 2,3, 4,5,6, etc. The number of gallium nitride chips packaged can be selected according to actual needs. In an embodiment of the present invention, 2 gan chips are taken as an example to describe the package structure of the present invention in detail, as shown in fig. 1 to 6.

In an embodiment of the present invention, the interconnection solder layer 4 is used for electrical connection and mechanical connection between the gallium nitride chip and the decoupling capacitor and the first conductive layer 11, and the material of the interconnection solder layer is solder. There are two horizontal conductive layers in the package structure, the horizontal conductive layer close to the gallium nitride chip is called a first conductive layer 11, and the horizontal conductive layer far from the gallium nitride chip is called a second conductive layer 12, and the top view is shown in fig. 5 and 6. In fig. 5, four driving pins 6 are provided and are respectively disposed on the polyimide material around the first conductive layer.

The first conductive layer 11 has therein a first conductive unit 111, a second conductive unit 112, a third conductive unit 113 and a fourth conductive unit 114, which are conductive copper layers separated by a polyimide material having an insulating effect.

The second conductive layer 12 has a fifth conductive element 121, a sixth conductive element 122, and a seventh conductive element 123, which are conductive copper layers that are also separated by a polyimide material that serves as an insulator. The distribution and relationship of these conductive copper layers and polyimide materials are shown in fig. 4-6.

The polyimide dielectric layer 13 is located between the first conductive layer 11 and the second conductive layer 12, and serves as an electrical insulator and a mechanical support. The polyimide dielectric layer 13 is provided with a plurality of through holes filled with an interconnection solder ball, which serves as an electrical connection between the first conductive layer 11 and the second conductive layer 12, and the solder ball is made of solder. Eight interconnect balls are shown in fig. 1 and 3. The distribution and relationship of the interconnect balls and polyimide dielectric layer 13 is shown in fig. 4. Wherein the first conductive unit 111 is electrically connected to the fifth conductive unit 121 through an interconnection solder ball; the fifth conductive unit 121 is electrically connected to its corresponding second conductive unit 112 through three interconnection solder balls; the sixth conductive element 122 is electrically connected to its corresponding second conductive element 112 through three interconnection solder balls; the sixth conductive element 122 is electrically connected to its corresponding fourth conductive element 114 through three interconnection solder balls; the seventh conductive unit 123 is electrically connected to its corresponding fourth conductive unit 114 through three interconnection solder balls; the third conductive unit 113 is electrically connected to the seventh conductive unit 123 through an interconnection solder ball.

The power module obtained by the packaging method according to an embodiment of the present invention integrates 3 decoupling capacitors, the distribution of which is shown in fig. 4, and the number of the decoupling capacitors may be 1 or more, depending on the packaging size and the application scenario requirement.

The layout of the power loop of the present package structure will now be described with reference to the cross-section shown in fig. 1, for example, fig. 2. The first current 201 flows from the decoupling capacitor 3, flows through the first conductive element 111 and the first GaN device 21 to form a second current 202, and the second current 202 flows through the second conductive element 112, the solder joint 14, the second conductive layer 12, the solder joint 14, the fourth conductive element 114, the second GaN device 22 and the third conductive element 113 to form a third current 203, and the third current 203 flows back to the decoupling capacitor 3 through the third conductive element 113. The whole shape of the current-converting circuit can be seen as a rectangle, and the thickness of the polyimide dielectric layer adopted by the packaging method is small, so that the current-converting circuit is small in area, the packaging with extremely low parasitic inductance is realized, and the excellent characteristic of high switching speed of the gallium nitride power device is exerted to the greatest extent.

In addition to the electrical insulation and mechanical support functions, the polyimide dielectric layer 13 has a certain stress release function due to a larger thermal expansion coefficient when the temperature of the module is increased due to the loss generated by the chip operation, so that the stress on the gallium nitride chip is reduced, the risk of chip damage is reduced, and the reliability of the power module is improved.

In a preferred embodiment, the flexible gallium nitride power module further includes an encapsulation housing 5, the encapsulation housing 5 is disposed outside the first conductive layer 11, and a plurality of accommodating chambers are formed by combining the encapsulation housing 5 and the first conductive layer 11, and the decoupling capacitor 3 and the GaN device 2 are respectively disposed in the corresponding accommodating chambers. In a preferred embodiment, the thickness of the encapsulation 5 is greater than or equal to the thickness of the decoupling capacitor 3. In a preferred embodiment, the material of the package housing 5 is epoxy. The package housing 5 is manufactured by an epoxy resin heating curing process. The packaging shell 5 is used for protecting the GaN device 2 and providing mechanical support for the packaging structure, and the thickness of the packaging shell 5 is consistent with that of the decoupling capacitor 3, and can be larger than that of the decoupling capacitor 3, so as to completely wrap the decoupling capacitor 3 and the GaN device 2, thereby providing better protection.

(1) Arranging an array of welding spots 14 on one side of the second conductive layer 12 facing the first conductive layer 11, then attaching the first conductive layer 11 to the second conductive layer 12, enabling the first conductive layer 11 to be electrically connected with the second conductive layer 12 through the array of welding spots 14, and enabling a polyimide dielectric layer 13 to be filled between the first conductive layer 11 and the second conductive layer 12 so as to form a substrate 1;

(2) The GaN devices 2 and the decoupling capacitors 3 are attached to the first conductive layer 11 through an interconnection welding layer, and the decoupling capacitors 3 and two adjacent GaN devices 2 form a power loop;

(3) Forming a package case 5 on the surface of the first conductive layer 11 using a thermal curing process to encapsulate the decoupling capacitor 3 and the GaN device 2; thereby functioning to protect the GaN device 2 and the commutation loop.

In a preferred embodiment, in step (1), the first conductive layer 11 is partitioned by a polyimide material to form a first conductive unit 111, a second conductive unit 112, a third conductive unit 113, and a fourth conductive unit 114, the second conductive unit 112 being disposed inside the first conductive unit 111, the fourth conductive unit 114 being disposed inside the third conductive unit 113; the second conductive layer 12 is electrically connected to the second conductive unit 112 and the fourth conductive unit 114 through a plurality of pads 14. Wherein the inner side of the first conductive unit 111, i.e., the side of the first conductive unit 111 near the third conductive unit 113, and the inner side of the third conductive unit 113, i.e., the side of the third conductive unit 113 near the first conductive unit 111. Thereby causing the second conductive unit 112 and the fourth conductive unit 114 to be disposed between the first conductive unit 111 and the third conductive unit 113.

In a preferred embodiment, in step (2), the interconnection solder layer 4 includes a first interconnection solder layer 41, a second interconnection solder layer 42, a third interconnection solder layer 43, a fourth interconnection solder layer 44, a fifth interconnection solder layer 45, and a sixth interconnection solder layer 46. The first source of the first GaN device 21 is electrically connected to the first conductive unit 111 through the first interconnection solder layer 41, and the first drain of the first GaN device 21 is electrically connected to the second conductive unit 112 through the second interconnection solder layer 42; the second source of the second GaN device 22 is electrically connected to the fourth conductive unit 114 through the fourth interconnection solder layer 44, and the second drain of the second GaN device 22 is electrically connected to the third conductive unit 113 through the third interconnection solder layer 43; the decoupling capacitor 3 is electrically connected to the first conductive unit 111 and the third conductive unit 113 through the interconnection solder layer 4, respectively. Specifically, the decoupling capacitor 3 is electrically connected to the first conductive unit 111 through the fifth interconnection solder layer 45; the decoupling capacitor 3 is electrically connected to the third conductive element 113 through the sixth interconnect solder layer 46.

Based on this, in one embodiment of the present invention, by arranging the decoupling capacitor 3 outside the substrate 1 and the layout of the decoupling capacitor 3 and the two GaN devices 2 on the same horizontal plane, a flexible polyimide material is used as an insulating medium between the conductive layers in the horizontal and vertical directions, and the thickness of the polyimide material in the vertical direction is only 18-25 μm, which is far smaller than the thicknesses (-1.6 mm) of the PCB FR4 substrate and the DBC substrate. Compared with the existing packaging structure of the power module, the packaging structure of the power module greatly reduces the distance between the conducting layers, greatly reduces the power loop area, reduces parasitic inductance, realizes the packaging of the extremely low parasitic inductance of <0.1nH, and can fully exert the excellent performance of the gallium nitride power device.

The cross section and the current-converting circuit of the packaging method are shown in fig. 1 and 2, in which the components, such as the third interconnection solder layer 43, the fourth interconnection solder layer 44, the solder joint 14 and the polyimide dielectric layer 13, which are close to the second GaN device 22 are located in the plane parallel to the cross section and shielded by the cross section, so that the area of the current-converting circuit is closely related to the thickness (the distance between the conductive layers in the vertical direction) of the substrate 1, and the smaller the thickness of the substrate is, the smaller the area of the current-converting circuit is. Therefore, the packaging method greatly reduces the area of the current-converting loop, thereby reducing the magnetic flux in the current-converting loop and further reducing parasitic inductance. Simulation verifies that the parasitic inductance is only 75pH, and the extremely low parasitic inductance package is realized.

The packaging method reduces the thermo-mechanical stress of the gallium nitride chip. In the packaging method, the flexible material polyimide and the conductive copper layer are combined to serve as the substrate of the chip, the thermal expansion coefficient of the polyimide material is larger than that of the PCB FR4 and DBC substrate, and a certain stress releasing effect can be achieved when the chip works at a high temperature, so that the thermomechanical stress on the chip is reduced, and the working reliability and the service life of the module are improved.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims

1. A flexible gallium nitride power module, comprising:

the substrate comprises a first conductive layer and a second conductive layer, polyimide materials are filled between the first conductive layer and the second conductive layer to form a polyimide dielectric layer, and the first conductive layer is electrically connected with the second conductive layer through a plurality of welding spots;

2. The flexible gallium nitride power module according to claim 1, wherein the decoupling capacitors and the GaN devices are disposed on a first plane, the thickness direction of the substrate is perpendicular to the first plane, and the first plane is parallel to the plane of the first conductive layer.

3. The flexible gallium nitride power module of claim 1, wherein the polyimide dielectric layer has a thickness of 18-25 μm.

4. The flexible gallium nitride power module of claim 1, wherein a plurality of solder joints are disposed on the polyimide dielectric layer, each solder joint is configured as an interconnect solder ball, and the first conductive layer and the second conductive layer are electrically connected by a plurality of interconnect solder balls.

5. The flexible gallium nitride power module of claim 1, wherein the GaN devices have two and are denoted as a first GaN device and a second GaN device, respectively; at least one of the decoupling capacitors is disposed between the first GaN device and the second GaN device.

6. The flexible gallium nitride power module according to claim 5, wherein the first conductive layer is partitioned by a polyimide material to form a first conductive unit, a second conductive unit, a third conductive unit, and a fourth conductive unit, the second conductive unit being disposed inside the first conductive unit, the fourth conductive unit being disposed inside the third conductive unit;

7. The flexible gallium nitride power module according to claim 6, wherein the first source of the first GaN device is electrically connected to the first conductive element by an interconnect solder layer and the first drain of the first GaN device is electrically connected to the second conductive element by an interconnect solder layer;

8. The flexible gallium nitride power module according to claim 7, wherein the decoupling capacitor is electrically connected to the first conductive element and the third conductive element, respectively, by an interconnect solder layer.

9. A method of packaging the flexible gallium nitride power module of claim 1, comprising the steps of:

10. The packaging method of the flexible gallium nitride power module according to claim 9, wherein the first conductive layer is partitioned by polyimide material to form a first conductive unit, a second conductive unit, a third conductive unit and a fourth conductive unit, the second conductive unit is disposed inside the first conductive unit, and the fourth conductive unit is disposed inside the third conductive unit;

the second conductive layer is electrically connected with the second conductive unit and the fourth conductive unit which correspond to the second conductive layer through a plurality of welding spots respectively;

the first source electrode of the first GaN device is electrically connected with the first conductive unit through an interconnection welding layer, and the first drain electrode of the first GaN device is electrically connected with the second conductive unit through an interconnection welding layer;

The second source electrode of the second GaN device is electrically connected with the fourth conductive unit through an interconnection welding layer, and the second drain electrode of the second GaN device is electrically connected with the third conductive unit through an interconnection welding layer;

The decoupling capacitor is electrically connected with the first conductive unit and the third conductive unit through interconnection welding layers respectively.