CN118300613A - Digital-to-analog converter and image sensor using same - Google Patents
Digital-to-analog converter and image sensor using same Download PDFInfo
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- CN118300613A CN118300613A CN202310006849.9A CN202310006849A CN118300613A CN 118300613 A CN118300613 A CN 118300613A CN 202310006849 A CN202310006849 A CN 202310006849A CN 118300613 A CN118300613 A CN 118300613A
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Abstract
The invention provides a digital-to-analog converter and an image sensor using the same, wherein one or more bias signals are output to a current generating unit through a bias circuit to adjust the branch current of each current generating branch, the on-off of a switch circuit is controlled to form an analog signal, the level of the bias signals is adjusted to adjust the branch current of each current generating branch, so that the required analog signal is obtained, the layout area of the image sensor is not occupied excessively, and the power consumption is low. In an application scene with lower requirements on precision and speed, the current values of accumulated currents generated by the current generating units are identical to each other, and the analog signals are linear ramp signals; in an application scenario with high requirements on precision and speed, the current values of the accumulated currents are different from each other, and the analog signal is a nonlinear ramp signal. The analog signal may be an analog current signal formed by directly outputting the accumulated current, or may be an analog voltage signal formed by flowing the accumulated current through a resistor.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a digital-to-analog converter and an image sensor using the same.
Background
In the image sensor, along with the continuous expansion of the scale of the pixel unit array, the traditional chip-level analog-to-digital converter (CHIP LEVEL Analog to Digital Converter) cannot meet the requirement of high frame rate, and the single-slope digital-to-analog converter (Single Slope Analog to Digital Converter, SSADC) has the characteristic of realizing high precision with small area and power consumption, so that the single-slope digital-to-analog converter is widely applied to the image sensor with high pixel and high frame rate.
SSADC is mainly composed of a comparator and a storage unit or a counting unit. In the analog-to-digital converter (Analog to Digital Converter, ADC), a ramp signal (VRAMP) is needed as a comparison level of the comparator, and the precision of the ramp signal directly influences the output precision of the SS ADC; in addition, the application scenario of the image sensor nowadays is more and more wide and variable, and a single linear ramp signal is difficult to adapt to different application requirements, so that the design of the ramp signal generating circuit capable of simultaneously meeting different application requirements is necessary.
Patent document 222110555245.0 discloses a generation circuit of a ramp signal of an image sensor, which includes a coefficient control unit, a plurality of ramp signal current generation units, and a resistor, the coefficient control unit being adapted to provide a plurality of different ramp signal coefficients to be respectively and correspondingly transmitted to the plurality of ramp signal current generation units according to application requirements. That is, the coefficient control unit controls the weight coefficients of the different ramp signal current generating units by generating different bias voltages, occupies a larger chip area, and consumes higher power.
Disclosure of Invention
The invention aims to provide a digital-to-analog converter which meets the requirements of linearity and nonlinearity simultaneously, occupies a small area and has low power consumption.
Based on the above considerations, the present invention provides a digital-to-analog converter comprising: the circuit comprises a bias circuit and at least one current generation unit, wherein the bias circuit is connected with the current generation unit, and the current generation unit comprises a switching circuit and a plurality of current generation branches which are connected with each other; the bias circuit outputs one or more bias signals to the current generating unit to adjust the branch current of each current generating branch, and controls the on-off of the switch circuit to form an analog signal.
Preferably, the current values of the branch currents are identical or at least partially different from each other in the same current generating unit.
Preferably, the number of current generating branches is identical or at least partially different from one current generating unit to the other.
Preferably, each of the branch currents is accumulated to form an accumulated current to the switching circuit.
Preferably, the current values of the accumulated currents are identical to each other between different current generating units, and the analog signal includes a linear ramp signal.
Preferably, the number of on-off states of the switch circuit is controlled at the same time to realize any slope of the linear ramp signal.
Preferably, the current values of the accumulated currents are different from each other between different current generating units, and the analog signal includes a nonlinear ramp signal.
Preferably, the number of on-off states of the switch circuit is controlled at the same time to realize any shape and slope of the nonlinear ramp signal.
Preferably, the current value of the accumulated current is partially different between different current generating units, and the analog signal includes a ramp signal with a stepwise linear phase and a stepwise nonlinear phase connected.
Preferably, the current generating branch is provided with one or more transistors to input the corresponding bias signals and output the corresponding branch currents.
Preferably, the transistors are all of the same type.
Preferably, the aspect ratio of some of the transistors is the same between different current generating units.
Preferably, in the same current generating unit, the same bias signal is input to a plurality of the transistors to form a plurality of the branch currents having the same or different current values.
Preferably, one or more identical bias signals are input to the corresponding transistors between different current generating units to form the branch currents with identical or different current values.
Preferably, part of the bias signal has a fixed level, and the rest of the bias signal has an adjustable level.
Preferably, the transistors are PMOS transistors, and the fixed level is a high level; or, the transistors are NMOS transistors, and the fixed level is low level.
Preferably, the method further comprises: and the digital logic circuit is connected with the switching circuit and outputs logic signals to control the on-off of the switching circuit.
The digital-to-analog converter is applied to an image sensor, outputs one or more bias signals to the current generating units through the bias circuit to adjust the branch current of each current generating branch, controls the on-off of the switch circuit to form analog signals, adjusts the level of the bias signals to adjust the branch current of each current generating branch, and accordingly obtains the required analog signals without occupying excessive layout area of the image sensor and with lower power consumption.
Further, in an application scenario with low requirements on precision and speed, current values of accumulated currents generated by the current generating units are identical to each other, and the analog signals are linear ramp signals; in an application scenario with high requirements on precision and speed, the current values of the accumulated currents are different from each other, and the analog signal is a nonlinear ramp signal.
Further, the analog signal may be an analog current signal formed by directly outputting the accumulated current, or may be an analog voltage signal formed by flowing the accumulated current through a resistor.
Drawings
Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments which follows, which is read in connection with the accompanying drawings.
FIG. 1 shows a schematic circuit diagram of a digital-to-analog converter according to an embodiment of the present invention;
FIG. 2 shows a schematic circuit diagram of a current generating unit according to an embodiment of the invention;
fig. 3 shows a waveform diagram of a ramp signal according to an embodiment of the present invention.
In the drawings, the same or similar reference numerals denote the same or similar devices (modules) or steps throughout the different drawings.
Detailed Description
In order to make the contents of the present invention more clear and understandable, the contents of the present invention will be further described with reference to the accompanying drawings. Of course, the invention is not limited to this particular embodiment, and common alternatives known to those skilled in the art are also encompassed within the scope of the invention.
In the description of the embodiments of the present invention, the structures of the present invention are not drawn to a general scale and are not partially enlarged, deformed, or simplified, so that the present invention should not be construed as being limited thereto.
A digital-to-analog converter according to the present invention will be described in detail below with reference to the accompanying drawings.
FIG. 1 shows a schematic circuit diagram of a digital-to-analog converter according to an embodiment of the present invention; FIG. 2 shows a schematic circuit diagram of a current generating unit according to an embodiment of the invention; fig. 3 shows a waveform diagram of a ramp signal according to an embodiment of the present invention.
The digital-to-analog converter comprises at least one current generating unit, and each current generating unit comprises a current source and a switching circuit which are connected. The current source includes one or more current generating branches that generate one or more branch currents to sum and output a summed current.
As shown in fig. 1, in the present embodiment, the current source array 22 and the switch array 33 connected in a one-to-one correspondence form a current generating unit array, and the control circuit 11 includes a bias circuit (not shown) connected to the current generating unit array 22 and a digital logic circuit (not shown) connected to the switch array 22. The bias circuit outputs one or more bias signals to the current generating unit to correspondingly adjust the branch current of each current generating branch.
The switch array 33 includes a plurality of switch circuits, each of which may be a differential switch group, and the digital logic circuit outputs a logic signal to control the on/off of the differential switch group to form an analog signal.
The analog signal may be an analog current signal formed by directly outputting the accumulated current, or may be an analog voltage signal formed by flowing the accumulated current through a resistor.
As shown in fig. 2, each of the differential switch groups determines the accumulated current to flow to a first output terminal (OUT 1 shown in fig. 2) or a second output terminal (OUT 2 shown in fig. 2) according to the logic signal. The accumulated currents of the current generating units are further summed together to obtain the accumulated currents, and the accumulated currents are directly output to form an analog current signal.
As shown in fig. 1, one end of the resistor R is connected to the second output end of each differential switch group, and the other end is commonly connected to a fixed voltage or ground with the first output end of each differential switch group. The accumulated current flows through the resistor R and then outputs a desired analog voltage signal (e.g., a ramp signal as shown in fig. 1) at the node.
As shown in fig. 3, when the voltage across the resistor R increases by the same amount in a unit cycle time, the analog signal is a linear ramp signal; when the voltage at two ends of the resistor R is increased by different amounts in unit period time, the analog signal is a nonlinear ramp signal.
In a preferred embodiment, the current values of the accumulated currents differ from one another or at least partially differ between different current generating units.
When the current flowing to the resistor R in the unit cycle time is increased or decreased, that is, the accumulated current I unit generated by each current generating unit is the same, the analog signal is a linear ramp signal; the analog signal is a nonlinear ramp signal when the magnitude of the current flowing to the resistor in the unit cycle time is different, that is, when the cumulative currents generated by the respective current generating units are different (different from each other or partially the same portion is different).
In particular, each of the current generating units may be provided with a first shunt for generating an equal and constant first shunt current, and a second shunt for generating an at least partly different and adjustable second shunt current. The first shunt and the second shunt may each include one or more current generating branches to generate one or more branch currents and are summed to form the first shunt current and the second shunt current, respectively. The first shunt current and the second shunt current are accumulated as accumulated current of the current generating unit.
The first branches are all on, the second branches are all off, the current values of the accumulated currents are the same, namely the accumulated currents I unit generated by the current generating units are the same, the analog signals are linear ramp signals, and the current values of the accumulated currents are adjusted to adjust the slopes of the linear ramp signals.
On the contrary, the first branches are all disconnected, the second branches are all conducted, the current values of the accumulated currents are at least partially different, the accumulated currents I unit generated by the current generating units are at least partially different, the analog signals are nonlinear slope signals, and the current values of the accumulated currents are adjusted to adjust the shapes of the nonlinear slope signals.
Or controlling the on-off of the first shunt and the second shunt to realize that the accumulated currents are the same for a period of time and are different for another period of time, wherein the analog signal is a slope signal with a stepwise linear phase and a stepwise nonlinear phase connected.
The first shunt and the second shunt may each include a plurality of current generating branches connected in parallel. Each current generating branch is provided with one or more transistors for inputting the corresponding bias signals and outputting the corresponding branch currents.
In the same current generating unit, the aspect ratio of part of the transistors is the same.
For example, the aspect ratios of the transistors of the first shunt are the same, so as to input the same bias signal and output a plurality of branch currents with the same current value, if the level of the bias signal is set to be a fixed level, a plurality of equal and constant branch currents are correspondingly generated, if the level of the bias signal is set to be an adjustable level, a plurality of equal and adjustable branch currents are correspondingly generated, and then the current value of the first shunt current can be adjusted.
Or the aspect ratios of the transistors of the second shunt circuit are at least partially different, if the level of the bias signal is set to be an adjustable level, a plurality of different and adjustable shunt currents are correspondingly generated, and then the current value of the second shunt current can be adjusted.
The transistors are PMOS transistors, and the fixed level is high level; or, the transistors are NMOS transistors, and the fixed level is low level.
The number of the current generation branches of the first branches is the same as each other among different current generation units, the length-width ratios of the transistors of the first branches are the same, and one bias signal is input to the transistors of the first branches to form a plurality of branch currents with the same current value. The number of the current generating branches of the second branches is the same as each other and the aspect ratios of the transistors are at least partially different, or the number of the current generating branches of the second branches is different from each other and the aspect ratios of the transistors are all different, and another bias signal is input to the transistors of each of the second branches to form a plurality of branch currents having different current values.
In this embodiment, as shown in fig. 2, each of the current generating units includes a first transistor MP1, a second transistor MP2, and a third transistor MP3.
The first transistor MP1, the second transistor MP2 and the third transistor MP3 are all transistors of the same type, such as PMOS transistors or NMOS transistors.
The first transistor MP1 and the second transistor MP2 form a cascode structure, that is, the first transistor MP1 is a cascode transistor of the cascode structure, and the second transistor MP2 is a cascode transistor of the cascode structure. The third transistor MP3 is connected in parallel with the common source tube.
The sources of the first transistor MP1 and the third transistor MP3 are commonly connected to a power source, and the gates of the first transistor MP1 and the third transistor MP3 are respectively connected to a first bias signal VBSP and a third bias signal VBSP3 to generate a first current I 1 and a third current I 3, respectively. The drains of the first transistor MP1 and the third transistor MP3 are commonly connected to the source of the second transistor MP2, and the gate of the second transistor MP2 is connected to the second bias signal VBSP to accumulate the first current I 1 and the third current I 3 and output an accumulated current I unit (the second current I 2) to the input terminal of the switching circuit through the drain of the second transistor MP 2.
In this embodiment, the cascode structure is a first shunt, the cascode tube of the cascode structure, that is, the first transistor MP1 outputs a constant current (first current I 1), the third transistor MP3 is a second shunt and outputs an adjustable current, and the cascode tube of the cascode structure outputs an adjustable accumulated current to the differential switch group.
Referring to fig. 1 in conjunction with fig. 2, the differential switch set includes a first switch SW1 and a second switch SW2. One end of the first switch SW1 and one end of the second switch SW2 are commonly connected to the drain of the second transistor MP2, the other end of the first switch SW1 is grounded, and the other end of the second switch SW2 is connected to the node.
The current values of the branch currents are identical or at least partially different from each other in the same current generating unit. By adjusting VBSP, the third transistor MP3 is caused to generate the third current I 3 which is the same as or different from the first current I 1.
When the linear ramp signal needs to be output, only I 3 needs to be controlled to zero, for example, VBSP3 is set to a high level, such as a power supply level; when the nonlinear ramp signal needs to be output, the level of VBSP is only required to be adjusted to adjust I 3.
In one embodiment, the digital-to-analog converter described above is applied to an image sensor, the image sensor block comprising: a pixel array of a plurality of pixels, a row control circuit, an analog-to-digital converter, a ramp signal generating circuit, and a digital processing circuit. The row control circuit provides a row control signal to control the pixel units of each row; the pixel units of each column are connected with the analog-to-digital converters of the corresponding columns, and the ramp signal generating circuit respectively provides the ramp signals of each column to the analog-to-digital converters of the corresponding columns, and the analog-to-digital converters output analog signals to the digital processing circuit.
The analog-digital converter mainly comprises a comparator and a storage unit or a counting unit, wherein a ramp signal (VRAMP) is adopted in the analog-digital converter (Analog to Digital Converter, ADC) as a comparison level of the comparator, and the precision of the ramp signal directly influences the output precision of the SS ADC, so that the technical scheme of the invention can generate the ramp signal with high speed and high precision and can be suitable for the application of a high-frame-rate image sensor.
According to the invention, one or more bias signals are output to the current generation unit through the bias circuit to adjust the branch current of each current generation branch, the on-off of the switch circuit is controlled to form an analog signal, the level of the bias signals is adjusted to adjust the branch current of each current generation branch, so that the required analog signal is obtained, the layout area of an excessive image sensor is not occupied, and the power consumption is low.
Further, in an application scenario with low requirements on precision and speed, current values of accumulated currents generated by the current generating units are identical to each other, and the analog signals are linear ramp signals; in an application scenario with high requirements on precision and speed, the current values of the accumulated currents are different from each other, and the analog signal is a nonlinear ramp signal.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Thus, the embodiments should be considered in all respects as illustrative and not restrictive. Furthermore, it is evident that the word "comprising" does not exclude other elements or steps, and that the word "a" or "an" does not exclude a plurality. The elements recited in the apparatus claims may also be embodied by one element. The terms first, second, etc. are used to denote a name, but not any particular order.
Claims (18)
1. A digital-to-analog converter, comprising: the circuit comprises a bias circuit and at least one current generation unit, wherein the bias circuit is connected with the current generation unit, and the current generation unit comprises a switching circuit and a plurality of current generation branches which are connected with each other; the bias circuit outputs one or more bias signals to the current generating unit to adjust the branch current of each current generating branch, and controls the on-off of the switch circuit to form an analog signal.
2. A digital-to-analogue converter as claimed in claim 1 in which the current values of the branch currents are identical or at least partially different from each other in the same current generating unit.
3. A digital-to-analogue converter as claimed in claim 1 in which the number of current generating branches is the same or at least partially different from one current generating unit to the other.
4. A digital-to-analogue converter as claimed in any one of claims 1 to 3 in which each of the branch currents is summed to form a summed current to the switching circuit.
5. The digital-to-analog converter of claim 4, wherein current values of said accumulated currents are identical to each other between different current generating units, and said analog signal comprises a linear ramp signal.
6. The digital-to-analog converter of claim 5, wherein the number of on-off of said switching circuit is controlled at the same time to achieve any slope of said linear ramp signal.
7. The digital-to-analog converter of claim 4, wherein current values of the accumulated currents are different from each other between different current generating units, and the analog signal comprises a nonlinear ramp signal.
8. The digital to analog converter of claim 7, wherein the number of on/off of said switching circuit is controlled at the same time to achieve any shape and slope of said nonlinear ramp signal.
9. The digital-to-analog converter of claim 4, wherein the current values of the accumulated currents are partially different between different current generating units, and the analog signal comprises a ramp signal with a stepwise linear phase and a stepwise nonlinear phase.
10. The digital-to-analog converter of claim 4, wherein said current generating branch is provided with one or more transistors for inputting said corresponding bias signal and outputting said corresponding branch current.
11. The digital to analog converter of claim 10, wherein the transistors are all of the same type.
12. The digital-to-analog converter of claim 11, wherein aspect ratios of some of said transistors are the same among different current generating units.
13. The digital-to-analog converter of claim 11, wherein the same bias signal is input to a plurality of said transistors in the same current generating unit to form a plurality of said branch currents having the same or different current values.
14. The digital-to-analog converter of claim 11, wherein one or more identical bias signals are input to corresponding transistors between different current generating units to form the branch currents having identical or different current values.
15. The digital-to-analog converter of claim 10, wherein a portion of said bias signal has a fixed level and the remainder of said bias signal has an adjustable level.
16. The digital to analog converter of claim 15, wherein said transistors are PMOS transistors, said fixed level being high; or, the transistors are NMOS transistors, and the fixed level is low level.
17. The digital-to-analog converter of claim 1, further comprising: and the digital logic circuit is connected with the switching circuit and outputs logic signals to control the on-off of the switching circuit.
18. An image sensor, comprising: a digital-to-analogue converter as claimed in any one of claims 1 to 17.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310006849.9A CN118300613A (en) | 2023-01-04 | 2023-01-04 | Digital-to-analog converter and image sensor using same |
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| CN202310006849.9A CN118300613A (en) | 2023-01-04 | 2023-01-04 | Digital-to-analog converter and image sensor using same |
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