CN118281118A - Manufacturing method of crystalline silicon battery and crystalline silicon battery - Google Patents

Manufacturing method of crystalline silicon battery and crystalline silicon battery Download PDF

Info

Publication number
CN118281118A
CN118281118A CN202410577858.8A CN202410577858A CN118281118A CN 118281118 A CN118281118 A CN 118281118A CN 202410577858 A CN202410577858 A CN 202410577858A CN 118281118 A CN118281118 A CN 118281118A
Authority
CN
China
Prior art keywords
layer
reflection
hydrotreatment
polysilicon layer
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202410577858.8A
Other languages
Chinese (zh)
Inventor
王爽
冯德魁
丁留伟
刘成法
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Trina Solar Co Ltd
Original Assignee
Trina Solar Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Trina Solar Co Ltd filed Critical Trina Solar Co Ltd
Priority to CN202410577858.8A priority Critical patent/CN118281118A/en
Publication of CN118281118A publication Critical patent/CN118281118A/en
Pending legal-status Critical Current

Links

Landscapes

  • Photovoltaic Devices (AREA)

Abstract

The application discloses a manufacturing method of a crystalline silicon battery and the crystalline silicon battery, and belongs to the technical field of batteries. The manufacturing method of the crystalline silicon battery comprises the following steps: providing a substrate, a tunneling oxide layer positioned on the back surface of the substrate, and a polysilicon layer positioned on one side of the tunneling oxide layer away from the substrate; and carrying out hydrotreatment on the polycrystalline silicon layer, and forming an anti-reflection structure on one side of the polycrystalline silicon layer, which is away from the tunneling oxide layer. The application can improve the passivation effect of the battery and the open-circuit voltage and the short-circuit current of the battery.

Description

Manufacturing method of crystalline silicon battery and crystalline silicon battery
Technical Field
The application belongs to the technical field of batteries, and particularly relates to a manufacturing method of a crystalline silicon battery and the crystalline silicon battery.
Background
The back of the crystalline silicon battery adopts the tunneling oxide layer and the polycrystalline silicon layer to form a tunneling oxide layer passivation contact structure, so that selective carrier transmission is realized, and excellent passivation quality and contact performance are realized. However, the atoms on the surface of the doped polysilicon layer inside the polysilicon layer have a large number of unsaturated chemical bonds, and more impurities and defects exist in the polysilicon material, so that when electrons pass through the tunneling oxide layer, certain carrier recombination occurs in the polysilicon layer, the passivation effect is affected, and the open-circuit voltage and the short-circuit current of the battery are reduced.
Disclosure of Invention
The present application aims to solve at least one of the technical problems existing in the prior art. Therefore, the application provides the manufacturing method of the crystalline silicon battery and the crystalline silicon battery, which can improve the passivation effect of the battery and improve the open-circuit voltage and the short-circuit current of the battery.
In a first aspect, the present application provides a method for manufacturing a crystalline silicon cell, including:
Providing a substrate, a tunneling oxide layer positioned on the back surface of the substrate, and a polysilicon layer positioned on one side of the tunneling oxide layer away from the substrate;
And carrying out hydrotreatment on the polycrystalline silicon layer, and forming an anti-reflection structure on one side of the polycrystalline silicon layer, which is away from the tunneling oxide layer.
According to the manufacturing method of the crystalline silicon battery, after the tunneling oxide layer and the polycrystalline silicon layer are sequentially formed on the back surface of the battery, the polycrystalline silicon layer is subjected to hydrotreatment, so that hydrogen diffuses into polycrystalline silicon, defects in the polycrystalline silicon are passivated, the number of surface dangling bonds is reduced, the passivation effect of the polycrystalline silicon layer is improved, the passivation effect of the battery is further improved, and the open-circuit voltage and the short-circuit current of the battery are improved.
According to one embodiment of the application, the anti-reflective structure comprises a first anti-reflective layer and a second anti-reflective layer;
The hydrotreating is performed on the polysilicon layer, and an antireflection structure is formed on one side of the polysilicon layer away from the tunneling oxide layer, including:
performing first hydrotreatment on the polysilicon layer by adopting hydrogen-containing gas;
forming the first anti-reflection layer on one side of the polycrystalline silicon layer, which is away from the tunneling oxide layer;
performing second hydrotreatment on the polysilicon layer by adopting hydrogen-containing gas;
And forming the second anti-reflection layer on one side of the first anti-reflection layer, which is away from the polycrystalline silicon layer.
According to one embodiment of the application, the anti-reflective structure further comprises a third anti-reflective layer;
The hydrotreating is performed on the polysilicon layer, and an antireflection structure is formed on one side of the polysilicon layer away from the tunneling oxide layer, and the method further comprises:
Performing third hydrotreatment on the polysilicon layer by adopting hydrogen-containing gas;
and forming the third anti-reflection layer on one side of the second anti-reflection layer, which faces away from the first anti-reflection layer.
According to one embodiment of the application, the hydrogen-containing gas comprises ammonia.
According to one embodiment of the application, the first hydrotreatment satisfies at least one of the following characteristics:
The flow of the ammonia gas is 10000 sccm-15000 sccm;
the first hydrotreating time is 30 s-50 s;
The pressure of the first hydrotreatment is 1500 mTorr-2000 mTorr;
the power of the first hydrotreatment is 14000W-17000W.
According to one embodiment of the application, the second hydrotreatment satisfies at least one of the following characteristics:
The flow rate of the ammonia gas is 11000 sccm-16000 sccm;
the first hydrotreating time is 30 s-50 s;
The pressure of the first hydrotreatment is 1500 mTorr-2000 mTorr;
the power of the first hydrotreatment is 14000W-17000W.
According to one embodiment of the application, the third hydrotreatment satisfies at least one of the following characteristics:
The flow rate of the ammonia gas is 11000 sccm-16000 sccm;
the first hydrotreatment time is 40-80 s;
The pressure of the first hydrotreatment is 1500 mTorr-2000 mTorr;
the power of the first hydrotreatment is 14000W-17000W.
According to one embodiment of the application, the first, second and third anti-reflection layers each comprise at least one passivation layer.
According to one embodiment of the application, the first and second anti-reflection layers each comprise one passivation layer, and the third anti-reflection layer comprises three passivation layers arranged in a stack.
According to one embodiment of the application, the refractive index of the passivation layer gradually decreases in a direction of the polysilicon layer away from the tunnel oxide layer.
According to one embodiment of the present application, before the hydrotreating the polysilicon layer and forming the anti-reflection structure on a side of the polysilicon layer facing away from the tunnel oxide layer, the method further includes:
And carrying out thickness thinning treatment on the polysilicon layer.
According to one embodiment of the present application, the thickness thinning process for the polysilicon layer includes:
and carrying out plasma etching on the polycrystalline silicon layer by adopting plasma gas so as to thin the thickness of the polycrystalline silicon layer.
According to one embodiment of the application, the plasma gas comprises ammonia.
According to one embodiment of the application, the plasma etch satisfies at least one of the following characteristics:
The flow of the ammonia gas is 10000 sccm-15000 sccm
The temperature of the plasma etching is 450-550 ℃;
The power of the plasma etching is 10000W-15000W;
the pressure of the plasma etching is 1500 mTorr-2000 mTorr;
the plasma etching time is 100 s-300 s.
According to one embodiment of the application, the thickness of the polysilicon layer is reduced to 5 nm-10 nm.
According to one embodiment of the present application, the forming an anti-reflection structure on a side of the polysilicon layer facing away from the tunnel oxide layer includes:
And forming an anti-reflection structure on one side of the polycrystalline silicon layer, which is away from the tunneling oxide layer, based on the reaction gas.
According to one embodiment of the application, the reactive gas comprises silane and ammonia.
In a second aspect, the application provides a crystalline silicon cell, which is manufactured and formed by the manufacturing method of the crystalline silicon cell in the first aspect.
The above technical solutions in the embodiments of the present application have at least one of the following technical effects:
After a tunneling oxide layer and a polycrystalline silicon layer are sequentially formed on the back surface of the battery, the polycrystalline silicon layer is subjected to hydrotreatment, so that hydrogen diffuses into polycrystalline silicon, defects in the polycrystalline silicon are passivated, the number of dangling bonds on the surface is reduced, the passivation effect of the polycrystalline silicon layer is improved, the passivation effect of the battery is further improved, the open-circuit voltage and the short-circuit current of the battery are improved, and the photoelectric conversion efficiency of the battery is improved;
The thickness of the polycrystalline silicon layer can be thinned by adopting specific gas ammonia to carry out plasma etching on the polycrystalline silicon layer, and the radius of hydrogen ions ionized by the ammonia is smaller, so that the damage caused by ionization is smaller, the thickness uniformity of the thinned polycrystalline silicon layer is better, the parasitic absorption is effectively reduced, and the short-circuit current is further improved, and the photoelectric conversion efficiency of the battery is further improved.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the application will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
Fig. 1 is a schematic flow chart of a method for manufacturing a crystalline silicon battery according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a method for manufacturing a crystalline silicon battery according to an embodiment of the present application;
Fig. 3 is a schematic structural diagram of a crystalline silicon battery according to an embodiment of the present application;
FIG. 4 is a second flow chart of a method for manufacturing a crystalline silicon cell according to an embodiment of the present application;
FIG. 5 is a second schematic diagram of a method for manufacturing a crystalline silicon cell according to an embodiment of the present application;
FIG. 6 is a third schematic diagram of a method for fabricating a crystalline silicon cell according to an embodiment of the present application;
FIG. 7 is a second schematic diagram of a crystalline silicon cell according to an embodiment of the present application;
FIG. 8 is a third schematic structural diagram of a crystalline silicon cell according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a crystalline silicon cell according to an embodiment of the present application;
Fig. 10 is a third flow chart of a method for manufacturing a crystalline silicon battery according to an embodiment of the application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
The following describes a method for manufacturing a crystalline silicon cell and a crystalline silicon cell provided by the embodiment of the application with reference to the accompanying drawings.
Fig. 1 is a flow chart of a method for manufacturing a crystalline silicon battery according to an embodiment of the application.
As shown in fig. 1, the method for manufacturing a crystalline silicon battery according to the embodiment of the present application includes step 110 and step 120.
Step 110, providing a substrate, a tunneling oxide layer on the back surface of the substrate, and a polysilicon layer on the side of the tunneling oxide layer facing away from the substrate.
As shown in fig. 2, a substrate 1, a tunnel oxide layer 2 and a polysilicon layer 3 are provided. The tunneling oxide layer 2 is located on the back surface of the substrate 1, and the polysilicon layer 3 is located on the side of the tunneling oxide layer 2 facing away from the substrate 1. The tunneling oxide layer 2 and the polysilicon layer 3 can form a tunneling oxide layer passivation contact (TOPCon) structure to realize selective carrier transmission, thereby realizing excellent passivation quality and contact performance.
During the manufacturing process, the substrate 1 may be provided first. In some embodiments, the substrate 1 may be back polished or back fine pile prepared. Then, a tunnel oxide layer 2 is formed on the back surface of the substrate 1 by a thin film deposition process. A polysilicon layer 3 is formed on the side of the tunnel oxide layer 2 facing away from the substrate 1 by a thin film deposition process. The thin film deposition process can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser-assisted deposition and the like.
It can be understood that when the tunnel oxide layer 2 and the polysilicon layer 3 are sequentially formed on the back surface of the substrate 1, the tunnel oxide layer 2 and the polysilicon layer 3 will wrap around to the front surface of the substrate 1, and RCA cleaning is further required to be performed on the tunnel oxide layer 2 and the polysilicon layer 3 wrapped around to the front surface of the substrate 1, so as to remove the tunnel oxide layer 2 and the polysilicon layer 3 wrapped around to the front surface of the substrate 1. The reagent used for removing the tunneling oxide layer 2 from the front surface of the substrate 1 may include HF, etc., and the reagent used for removing the polysilicon layer 3 from the front surface of the substrate 1 may include alkali solution, etc. Wherein the alkali solution may include sodium hydroxide solution, etc.
In some embodiments, the substrate 1 may comprise an N-type silicon substrate. The tunnel oxide layer 2 may include silicon oxide or the like, and the thickness of the tunnel oxide layer 2 may be between 1nm and 2 nm. The polysilicon layer 3 may include P-type polysilicon (poly) or the like, and the thickness of the polysilicon layer 3 may be between 90nm and 115 nm.
In some embodiments, before the tunneling oxide layer 2 and the polysilicon layer 3 are sequentially formed on the back surface of the substrate 1, a PN junction is formed on the front surface of the substrate 1, and the front surface and the back surface of the substrate 1 are disposed opposite to each other.
The step of forming a PN junction on the front surface of the substrate 1 may include:
The front side of the substrate 1 was boron-amplified to prepare a PN junction.
It will be appreciated that the boron diffusion step may be performed in a boron diffusion furnace. Gases used for boron diffusion include, but are not limited to, BCl3 and oxygen.
It will be appreciated that when the front surface of the substrate 1 is boron-expanded, the back surface of the substrate 1 will form a degree of lapping BSG (borosilicate glass layer), and the degree of lapping BSG of the back surface of the silicon wafer will be removed. Among these, the agents used to remove the back side wrap BSG of the substrate 1 include, but are not limited to, HF.
In some embodiments, the front side of the substrate 1 is further formed with a passivation film, which is located at a side of the PN junction facing away from the substrate 1. The passivation film includes at least one of an aluminum oxide film, silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the passivation film is 65 nm-85 nm.
And 120, hydrotreating the polysilicon layer, and forming an anti-reflection structure on one side of the polysilicon layer, which is away from the tunneling oxide layer.
After forming the polysilicon layer 3, the polysilicon layer 3 is hydrotreated, and an anti-reflection structure 4 is formed on the side of the polysilicon layer 3 facing away from the tunnel oxide layer 2, as shown in fig. 3.
Because the polysilicon layer 3 is doped with ions, the doped polysilicon surface atoms have a large number of unsaturated chemical bonds, and more impurities and defects exist in the polysilicon material, when electrons pass through the tunneling oxide layer 2, certain carrier recombination occurs in the polysilicon layer 3, and the passivation effect is affected, so that the open-circuit voltage and the short-circuit current of the battery are reduced.
Therefore, after the polysilicon layer 3 is formed, the polysilicon layer 3 is hydrotreated to diffuse hydrogen into polysilicon, so that defects in the polysilicon are passivated, the number of dangling bonds on the surface is reduced, the passivation effect of the polysilicon layer 3 is improved, the passivation effect of a battery is further improved, the open-circuit voltage and the short-circuit current of the battery are improved, and the overall performance of the battery is improved.
The anti-reflection structure 4 can increase light absorption, reduce light reflection, and effectively improve photoelectric conversion efficiency of the solar cell when the crystalline silicon cell is applied to the solar cell. In addition, the anti-reflection structure 4 also has passivation effect on the polysilicon layer 3 in the forming process, so that the passivation effect of the battery is further improved.
In some embodiments, the hydrotreating of the polysilicon layer in step 120 includes:
And (3) hydrotreating the polysilicon layer by adopting hydrogen-containing gas.
Wherein the hydrotreatment of the polysilicon layer 3 can be performed in a reaction chamber. The structure of the substrate 1, the tunnel oxide layer 2 and the polysilicon layer 3 may be placed in a reaction chamber, and then a hydrogen-containing gas is introduced into the reaction chamber. The polysilicon layer 3 is hydrotreated using a hydrogen-containing gas. Parameters such as the flow rate of the hydrogen-containing gas, the treatment duration, the radio frequency power and the pressure intensity can be adjusted according to actual requirements, so that the hydrotreating effect of the polysilicon layer 3 can be ensured to meet the requirements.
In some embodiments, the hydrogen-containing gas comprises ammonia. The hydrogen-containing gas may include other gases as long as the hydrotreating of the polysilicon layer 3 is satisfied, and is not particularly limited herein.
In some embodiments, forming the anti-reflection structure on the side of the polysilicon layer facing away from the tunnel oxide layer in step 120 includes:
an anti-reflection structure is formed on a side of the polysilicon layer facing away from the tunnel oxide layer based on the reaction gas.
Wherein the formation of the anti-reflection structure 4 may be performed in a reaction chamber. The structure of the substrate 1, the tunnel oxide layer2 and the polysilicon layer3 may be placed in a reaction chamber. After hydrotreating the polysilicon layer3, a reaction gas is introduced into the reaction chamber. An anti-reflection structure 4 is formed on the side of the polysilicon layer3 facing away from the tunnel oxide layer2 based on the reaction gas. Parameters such as the flow rate of the reaction gas, the processing time, the radio frequency power, the pressure and the like can be adjusted according to actual requirements, so that the formation effect of the anti-reflection structure 4 can be ensured to meet the requirements.
In some embodiments, the reactive gas comprises silane and ammonia. The reaction gas may include other gases as long as the antireflection structure 4 can be formed, and is not particularly limited herein. The flow ratio of each gas in the reaction gas may be set according to actual requirements, and is not particularly limited herein.
In some embodiments, the polysilicon layer 3 may be hydrotreated once, i.e. after forming the polysilicon layer 3 and before forming the anti-reflective structure 4, the polysilicon layer 3 may be hydrotreated to improve the passivation effect of the polysilicon layer 3. In some embodiments, the polysilicon layer 3 is hydrotreated using a hydrogen-containing gas. An anti-reflection structure 4 is then formed on the side of the polysilicon layer 3 facing away from the tunnel oxide layer 2.
The antireflection structure 4 may have a single-layer structure or a stacked-layer structure. For example, the anti-reflection structure 4 may include a plurality of passivation layers arranged in a stack. The step of forming the anti-reflection structure 4 on the side of the polysilicon layer 3 facing away from the tunnel oxide layer 2 may comprise: and a thin film deposition process is adopted, and a plurality of passivation layers are sequentially formed on one side of the polycrystalline silicon layer 3, which is away from the tunneling oxide layer 2.
In some embodiments, the polysilicon layer 3 may be hydrotreated multiple times. The anti-reflection structure 4 may be a laminated structure, for example, the anti-reflection structure 4 includes a plurality of anti-reflection layers arranged in a laminated manner. After the formation of the polysilicon layer 3 and before each formation of the anti-reflection layer, the polysilicon layer 3 is hydrotreated.
The anti-reflection structure 4 comprises a first anti-reflection layer and a second anti-reflection layer. As shown in fig. 4, the hydrotreating of the polysilicon layer in step 120 forms an anti-reflection structure on a side of the polysilicon layer facing away from the tunnel oxide layer, including:
step 121, performing first hydrotreatment on the polysilicon layer by adopting hydrogen-containing gas;
step 122, forming a first anti-reflection layer on one side of the polysilicon layer away from the tunneling oxide layer;
step 123, performing second hydrotreatment on the polysilicon layer by adopting hydrogen-containing gas;
And 124, forming a second anti-reflection layer on the side of the first anti-reflection layer, which faces away from the polycrystalline silicon layer.
After the formation of the polysilicon layer 3 and before the formation of the first anti-reflection layer 41, the polysilicon layer 3 is subjected to a first hydrotreatment using a hydrogen-containing gas. Wherein the hydrogen-containing gas may comprise ammonia. And ammonia is introduced into the reaction chamber so as to carry out hydrotreatment on the polycrystalline silicon layer 3 by adopting the ammonia, and the passivation effect of the polycrystalline silicon layer 3 is improved.
Wherein the first hydrotreatment satisfies at least one of the following characteristics:
The flow of the ammonia is 10000 sccm-15000 sccm;
the first hydrotreating time is 30 s-50 s;
The pressure of the first hydrotreatment is 1500 mTorr-2000 mTorr;
the power of the first hydrotreatment is 14000W-17000W.
Then, as shown in fig. 5, a first anti-reflection layer 41 is formed on the side of the polysilicon layer 3 facing away from the tunnel oxide layer 2. In some embodiments, the first anti-reflection layer 41 is formed on the side of the polysilicon layer 3 facing away from the tunnel oxide layer 2 based on the reaction gas. Wherein the reaction gas may include silane and ammonia. Silane and ammonia gas are introduced into the reaction chamber to form a first anti-reflection layer 41 on the side of the polysilicon layer 3 facing away from the tunnel oxide layer 2, based on the silane and ammonia gas, and using a thin film deposition process.
The first antireflection layer 41 may have a single-layer structure or a stacked-layer structure. The first anti-reflection layer 41 may include at least one passivation layer. In some embodiments, the first anti-reflective layer 41 may include a passivation layer. Wherein the passivation layer may include at least one of an aluminum oxide film, a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. For example, the first anti-reflection layer 41 may include one silicon nitride layer (first silicon nitride layer).
In case the first anti-reflection layer 41 comprises a silicon nitride layer, the first silicon nitride layer is formed on the side of the polysilicon layer 3 facing away from the tunnel oxide layer 2, based on silane and ammonia, and using a thin film deposition process. Wherein, the ratio of the flow rates of the silane and the ammonia gas can be between 0.23 and 0.28, the reaction time period can be between 50s and 80s, the pressure can be between 1500pa and 2000pa, and the power can be between 14000w and 17000 w.
After the formation of the first anti-reflection layer 41 and before the formation of the second anti-reflection layer 42, the polysilicon layer 3 is subjected to a second hydrotreatment with a hydrogen-containing gas. Wherein the hydrogen-containing gas may comprise ammonia. And (3) introducing ammonia gas into the reaction chamber so as to carry out hydrotreatment on the polycrystalline silicon layer 3 again by adopting the ammonia gas, thereby further improving the passivation effect of the polycrystalline silicon layer 3.
Wherein the second hydrotreatment satisfies at least one of the following characteristics:
The flow rate of the ammonia gas is 11000 sccm-16000 sccm;
the first hydrotreating time is 30 s-50 s;
The pressure of the first hydrotreatment is 1500 mTorr-2000 mTorr;
the power of the first hydrotreatment is 14000W-17000W.
Then, as shown in fig. 6, a second anti-reflection layer 42 is formed on a side of the first anti-reflection layer 41 facing away from the polysilicon layer 3. In some embodiments, a second anti-reflection layer 42 is formed on the side of the first anti-reflection layer 41 facing away from the polysilicon layer 3 based on the reaction gas. Wherein the reaction gas may include silane and ammonia. The reaction chamber is fed with reactive silane and ammonia to form a second anti-reflective layer 42 on the side of the first anti-reflective layer 41 facing away from the polysilicon layer 3, based on silane and ammonia, and using a thin film deposition process.
The second anti-reflection layer 42 may have a single layer structure or a stacked structure. The second anti-reflection layer 42 may include at least one passivation layer. In some embodiments, the second anti-reflective layer 42 may include a passivation layer. Wherein the passivation layer may include at least one of an aluminum oxide film, a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. For example, the first anti-reflection layer 41 may include one silicon nitride layer (second silicon nitride layer).
In the case where the second anti-reflection layer 42 comprises one silicon nitride layer, the second silicon nitride layer is formed on the side of the first anti-reflection layer 41 facing away from the polysilicon layer 3 based on silane and ammonia gas and using a thin film deposition process. The ratio of the flow rates of the silane and the ammonia gas can be between 0.15 and 0.23, the reaction time can be between 50s and 80s, the pressure can be between 1500 mTorr and 2000 mTorr, and the power can be between 14000w and 17000 w.
In some embodiments, the anti-reflective structure 4 further comprises a third anti-reflective layer. Referring to fig. 4, in step 120, the polysilicon layer is hydrotreated to form an anti-reflection structure on a side of the polysilicon layer facing away from the tunnel oxide layer, and the method further includes:
Step 125, performing a third hydrotreatment on the polysilicon layer;
Step 126, forming a third anti-reflection layer on a side of the second anti-reflection layer facing away from the first anti-reflection layer.
After the formation of the second anti-reflection layer 42 and before the formation of the third anti-reflection layer 43, the polysilicon layer 3 is subjected to a third hydrotreatment with a hydrogen-containing gas. Wherein the hydrogen-containing gas may comprise ammonia. And (3) introducing ammonia gas into the reaction chamber so as to carry out hydrotreatment on the polycrystalline silicon layer 3 again by adopting the ammonia gas, thereby further improving the passivation effect of the polycrystalline silicon layer 3.
Wherein the third hydrotreatment satisfies at least one of the following characteristics:
The flow rate of the ammonia gas is 11000 sccm-16000 sccm;
the first hydrotreating time is 40 s-80 s;
The pressure of the first hydrotreatment is 1500 mTorr-2000 mTorr;
the power of the first hydrotreatment is 14000W-17000W.
Then, as shown in fig. 7, a third antireflection layer 43 is formed on the side of the second antireflection layer 42 facing away from the first antireflection layer 41. In some embodiments, a third anti-reflection layer 43 is formed on a side of the second anti-reflection layer 42 facing away from the first anti-reflection layer 41 based on the reaction gas. Wherein the reaction gas may include silane and ammonia. The reaction chamber is fed with reactive silane and ammonia to form a third anti-reflective layer 43 on the side of the second anti-reflective layer 42 facing away from the first anti-reflective layer 41, based on silane and ammonia, and using a thin film deposition process.
The third antireflection layer 43 may have a single-layer structure or a stacked-layer structure. The third anti-reflection layer 43 may include at least one passivation layer. In some embodiments, the third anti-reflection layer 43 may include three passivation layers disposed in a stacked manner. Wherein the passivation layer may include at least one of an aluminum oxide film, a silicon nitride layer, a silicon oxynitride layer, and a silicon oxide layer. For example, the third anti-reflection layer 43 may include three silicon nitride layers (a third silicon nitride layer, a fourth silicon nitride layer, and a fifth silicon nitride layer) provided in a stacked manner.
In the case where the third anti-reflection layer 43 includes three silicon nitride layers which are stacked, three silicon nitride layers are sequentially formed on the side of the second anti-reflection layer 42 facing away from the first anti-reflection layer 41 based on silane and ammonia gas, and using a thin film deposition process. In other words, a third silicon nitride layer is formed on the side of the second anti-reflection layer 42 facing away from the first anti-reflection layer 41, then a fourth silicon nitride layer is formed on the side of the third silicon nitride layer facing away from the second anti-reflection layer 42, and then a fifth silicon nitride layer is formed on the side of the fourth silicon nitride layer facing away from the third silicon nitride layer.
In the formation process of the third silicon nitride layer, the ratio of the flow rates of the silane and the ammonia gas can be between 0.11 and 0.15, the reaction duration can be between 90s and 120s, the pressure can be between 1500 mTorr and 2000 mTorr, and the power can be between 14000w and 17000 w.
In the formation process of the fourth silicon nitride layer, the ratio of the flow rates of the silane and the ammonia gas can be between 0.08 and 0.13, the reaction duration can be between 110s and 140s, the pressure can be between 1500 mTorr and 2000 mTorr, and the power can be between 14000w and 17000 w.
In the formation process of the fifth silicon nitride layer, the ratio of the flow rates of the silane and the ammonia gas can be between 0.06 and 0.11, the reaction duration can be between 180s and 230s, the pressure can be between 1500 mTorr and 2000 mTorr, and the power can be between 14000w and 17000 w.
In the case where the antireflection structure 4 includes five passivation layers, each of the first and second antireflection layers 41 and 42 may include one passivation layer, and the third antireflection layer 43 may include a plurality of passivation layers disposed in a stacked manner. In the manufacturing process, the polysilicon layer 3 may be subjected to a first hydrotreatment after the polysilicon layer 3 is formed. Then, as shown in connection with fig. 8, a first passivation layer 40a is formed on the side of the polysilicon layer 3 facing away from the tunnel oxide layer 2. The polysilicon layer 3 is subjected to a second hydrotreatment. Then, a second passivation layer 40b is formed on the side of the first silicon nitride layer facing away from the polysilicon layer 3. The polysilicon layer 3 is subjected to a third hydrotreatment. Then, a third passivation layer 40c, a fourth passivation layer 40d, and a fifth passivation layer 40e are sequentially formed on a side of the second silicon nitride layer facing away from the first silicon nitride layer.
In this embodiment, after the polysilicon layer 3 is formed, the polysilicon layer 3 is hydrotreated, so as to effectively improve the passivation effect of the polysilicon layer 3. After forming a passivation layer (first passivation layer 40 a), the polysilicon layer 3 is subjected to a second hydrotreatment, so that the effect of hydrogen diffusion is prevented from being affected due to thicker passivation layer, and the passivation effect of the polysilicon layer 3 is further improved. After forming another passivation layer (second passivation layer 40 b), the polysilicon layer 3 is subjected to a third hydrotreatment, so that the effect of hydrogen diffusion is prevented from being affected by thicker passivation layer, and the passivation effect of the polysilicon layer 3 is further improved.
In case the anti-reflective structure 4 comprises five passivation layers, the first 41, second 42 and third 43 anti-reflective layers may also comprise other numbers of passivation layers. For example, the first and second anti-reflection layers 41 and 43 may each include two passivation layers disposed in a stacked manner, and the third anti-reflection layer may include one passivation layer. In the manufacturing process, the polysilicon layer 3 may be subjected to a first hydrotreatment after the polysilicon layer 3 is formed. Then, as shown in fig. 9, a first passivation layer 40a and a second passivation layer 40b are sequentially formed on a side of the polysilicon layer 3 facing away from the tunnel oxide layer 2. The polysilicon layer 3 is subjected to a second hydrotreatment. Then, a third passivation layer 40c and a fourth passivation layer 40d are sequentially formed on a side of the second passivation layer 40b facing away from the first passivation layer 40 a. The polysilicon layer 3 is subjected to a third hydrotreatment. Then, a fifth passivation layer 40e is sequentially formed on a side of the fourth passivation layer 40d facing away from the third passivation layer 40 c.
In some embodiments, where the anti-reflective structure 4 comprises a plurality of passivation layers arranged in a stack, the refractive index of the plurality of passivation layers gradually decreases in a direction of the polysilicon layer 3 away from the tunnel oxide layer 2.
In this embodiment, the refractive indexes of the passivation layers in the anti-reflection structure 4 are different, so that the reflection of light can be effectively reduced, and the photoelectric conversion efficiency of the battery can be improved. And the refractive index of the passivation layer arranged close to the polycrystalline silicon layer 3 is higher, so that the surface passivation effect is better.
In some embodiments, as shown in fig. 10, the hydrotreating of the polysilicon layer in step 120, before forming the anti-reflective structure on the side of the polysilicon layer facing away from the tunnel oxide layer, further includes:
and 111, performing thickness thinning treatment on the polysilicon layer.
In the related art, the thickness of the polysilicon layer in the crystalline silicon battery is larger, so that higher parasitic absorption is brought, the short-circuit current of the crystalline silicon battery is influenced, and the conversion efficiency of the solar battery is lower. In the embodiment, the thickness of the polysilicon layer 3 is thinned, so that the thickness uniformity of the thinned polysilicon layer 3 is better, parasitic absorption is effectively reduced, short-circuit current is further improved, and the conversion efficiency of the solar cell is further improved.
In some embodiments, the thickness reduction of the polysilicon layer in step 111 includes:
and adopting plasma gas to carry out plasma etching on the polycrystalline silicon layer so as to thin the thickness of the polycrystalline silicon layer.
Wherein the thickness reduction treatment of the polysilicon layer 3 may be performed in a reaction chamber. The structure of the substrate 1, the tunnel oxide layer 2 and the polysilicon layer 3 may be placed in a reaction chamber, and then plasma gas is introduced into the reaction chamber. The polysilicon layer 3 is plasma etched using a plasma gas. Parameters such as the flow rate of the plasma gas, the processing time, the radio frequency power and the pressure intensity can be adjusted according to actual requirements, so that the thickness reduction effect of the polysilicon layer 3 is ensured to meet the requirements.
In some embodiments, the plasma gas comprises ammonia. The plasma gas may include other gases as long as the thickness reduction treatment of the polysilicon layer 3 is satisfied, and is not particularly limited herein.
According to the embodiment, the polysilicon layer 3 on the back surface of the substrate 1 is subjected to plasma etching by adopting the specific type of gas ammonia, the polysilicon layer 3 can be thinned, and the radius of hydrogen ions ionized by the ammonia is smaller, so that the damage caused by ionization is smaller, the thickness uniformity of the thinned polysilicon layer 3 is better, the parasitic absorption is effectively reduced, the short-circuit current is further improved, and the conversion efficiency of the solar cell is further improved.
In some embodiments, the thickness of the polysilicon layer 3 is reduced by 5nm to 10nm, i.e., the thickness difference between the polysilicon layer 3 before and after the plasma etching is 5nm to 10nm.
In some embodiments, the thickness of the polysilicon layer 3 after plasma etching is 70nm to 100nm.
In some embodiments, the plasma etch satisfies at least one of the following features:
the flow rate of the ammonia gas is 10000 sccm-15000 sccm
The temperature of plasma etching is 450-550 ℃;
The power of plasma etching is 10000W-15000W;
the pressure of plasma etching is 1500 mTorr-2000 mTorr;
The plasma etching time is 100 s-300 s.
In some embodiments, the front and back sides of the crystalline silicon cell are also formed with first and second electrodes, respectively. The first electrode is located at a side of the PN junction facing away from the substrate 1, and the second electrode is located at a side of the anti-reflection structure facing away from the substrate 1.
The manufacturing process of the first electrode and the second electrode may include printing and the like. For example, electrode grid lines are printed on the front and back surfaces of the substrate 1, respectively, and sintered to form a first electrode and a second electrode. It is further understood that the material of the first electrode and the second electrode is not limited in the present application.
According to the manufacturing method of the crystalline silicon battery provided by the embodiment of the application, after the tunneling oxide layer and the polycrystalline silicon layer are sequentially formed on the back surface of the battery, the polycrystalline silicon layer is subjected to hydrotreatment, so that hydrogen diffuses into polycrystalline silicon, thereby passivating defects in the polycrystalline silicon, reducing the number of dangling bonds on the surface, improving the passivation effect of the polycrystalline silicon layer, further improving the passivation effect of the battery, and improving the open-circuit voltage and the short-circuit current of the battery.
Correspondingly, the embodiment of the application also provides a crystalline silicon battery which can be manufactured by adopting the manufacturing method of the crystalline silicon battery in the embodiment.
As shown in fig. 3, the crystalline silicon cell includes a substrate 1, a tunnel oxide layer 2, a polysilicon layer 3, and an anti-reflection structure 4. The tunneling oxide layer 2 is located on the back surface of the substrate 1, the polysilicon layer 3 is located on one side of the tunneling oxide layer 2 away from the substrate 1, and the anti-reflection structure 4 is located on one side of the polysilicon layer 3 away from the tunneling oxide layer 2.
The substrate 1 may include an N-type silicon substrate. The tunneling oxide layer 2 and the polysilicon layer 3 can form a tunneling oxide layer passivation contact (TOPCon) structure to realize selective carrier transmission, thereby realizing excellent passivation quality and contact performance. The tunnel oxide layer 2 may comprise silicon oxide and the thickness of the tunnel oxide layer 2 may be between 1.5nm and 2 nm. The polysilicon layer 3 may include P-type polysilicon (poly), and the thickness of the polysilicon layer 3 may be between 105nm and 115 nm.
The polysilicon layer 3 in this embodiment is subjected to independent hydrotreatment to passivate defects in the polysilicon body, so as to reduce the number of surface dangling bonds, so that the polysilicon layer 3 has a good passivation effect, the open-circuit voltage and short-circuit current of the battery are improved, and the overall performance of the battery is improved. In addition, the anti-reflection structure 4 can increase the absorption of light, reduce the reflection of light, and effectively improve the photoelectric conversion efficiency of the solar cell when the crystalline silicon cell is applied to the solar cell.
The antireflection structure 4 may have a single-layer structure or a stacked-layer structure.
In some embodiments, as shown in fig. 7, the anti-reflective structure 4 includes a first anti-reflective layer 41 and a second anti-reflective layer 42 that are stacked. The first anti-reflection layer 41 is located on the side of the polysilicon layer 3 facing away from the tunnel oxide layer 2 and the second anti-reflection layer 42 is located on the side of the first anti-reflection layer 41 facing away from the polysilicon layer 3.
In some embodiments, as shown in fig. 7, the anti-reflective structure 4 further comprises a third anti-reflective layer 43. The third anti-reflection layer 43 is located on the side of the second anti-reflection layer 42 facing away from the first anti-reflection layer 41.
In some embodiments, the first, second, and third anti-reflection layers 41, 42, and 43 each include at least one passivation layer.
For example, as shown in fig. 8, the first anti-reflection layer 41 includes one passivation layer (first passivation layer 40 a), the second anti-reflection layer 42 includes one passivation layer (second passivation layer 40 b), and the third anti-reflection layer 43 includes three passivation layers (third passivation layer 40c, fourth passivation layer 40d, and fifth passivation layer 40 e) which are stacked.
For another example, the first anti-reflection layer 41 includes two passivation layers (a first passivation layer 40a and a second passivation layer 40 b) which are stacked, the second anti-reflection layer 42 includes two passivation layers (a third passivation layer 40c and a fourth passivation layer 40 d) which are stacked, and the third anti-reflection layer 43 includes one passivation layer (a fifth passivation layer 40 e).
In some embodiments, the passivation layer comprises a silicon nitride layer.
According to the crystalline silicon battery provided by the embodiment of the application, after the tunneling oxide layer and the polycrystalline silicon layer are sequentially formed on the back surface of the battery, the polycrystalline silicon layer is subjected to hydrotreatment, so that hydrogen diffuses into polycrystalline silicon, thereby passivating defects in the polycrystalline silicon, reducing the number of surface dangling bonds, improving the passivation effect of the polycrystalline silicon layer, further improving the passivation effect of the battery, improving the open-circuit voltage and short-circuit current of the battery, and improving the photoelectric conversion efficiency of the battery. And moreover, the thickness of the polycrystalline silicon layer can be thinned by adopting specific gas ammonia to carry out plasma etching on the polycrystalline silicon layer, and the radius of hydrogen ions ionized by the ammonia is smaller, so that the damage caused by ionization is smaller, the thickness uniformity of the thinned polycrystalline silicon layer is better, the parasitic absorption is effectively reduced, the short-circuit current is further improved, and the photoelectric conversion efficiency of the battery is further improved.
Correspondingly, the embodiment of the application also provides a solar cell which comprises the crystalline silicon cell in the embodiment.
The embodiment can improve the passivation effect of the battery, improve the open-circuit voltage and short-circuit current of the battery, and effectively improve the photoelectric conversion efficiency of the solar battery.
Correspondingly, the embodiment of the application also provides a photovoltaic module, which comprises the solar cell in the embodiment.
The photovoltaic module comprises the solar cell provided by the application, and therefore has at least the same advantages as the solar cell.
Correspondingly, the embodiment of the application also provides electrical equipment comprising the photovoltaic module.
The electrical equipment provided by the application comprises the photovoltaic module provided by the application, so that the electrical equipment has at least the same advantages as the photovoltaic module.
In some embodiments, the electrical devices include, but are not limited to, transportation devices such as automobiles, airplanes, and the like, vehicle-mounted aromatherapy, and the like, which require a power supply for driving.
The present application will be described in further detail with reference to the following specific embodiments, but the embodiments of the present application are not limited thereto.
Example 1
(1) Cleaning and texturing an N-type silicon wafer, and forming a pyramid textured structure on the surface of the silicon wafer;
(2) Performing boron expansion on the front surface of the cleaned and textured silicon wafer to form a P-type region so as to prepare a PN junction;
(3) Alkali polishing is carried out on the back of the silicon wafer, and PN junctions from the degree of winding to the back and the edge of the silicon wafer when the front boron expansion is carried out in the step (2) are removed;
(4) Sequentially preparing a tunneling oxide layer and a Poly layer (polysilicon layer) on the back of the silicon wafer after alkali polishing, wherein the tunneling oxide layer is a SiO 2 layer with the thickness of 1.5nm; the thickness of the Poly layer is 90nm;
(5) RCA cleaning, namely removing a tunneling oxide layer and a polycrystalline silicon layer which are wound to the front side of the silicon wafer when the tunneling oxide layer and the Poly layer are prepared on the back side of the silicon wafer in the step (4);
(6) ALD front deposition of alumina: depositing an alumina (Al 2O3) film layer on the PN junction surface of the silicon wafer after RCA cleaning, wherein the thickness is 8nm;
(7) Preparing a passivation film on the front surface: depositing silicon oxynitride, silicon nitride and silicon oxide on the surface of the aluminum oxide film layer, wherein the thickness is 75nm;
(8) Carrying out plasma etching on the polysilicon layer on the back of the silicon wafer by adopting ammonia gas; wherein the flow of the ammonia gas is 12000sccm, the temperature of plasma etching is 500 ℃, the power is 13500W, the pressure is 1800 mTorr, and the time is 200s; the thickness of the Poly layer after plasma etching is 80nm;
(9) Carrying out hydrogenation treatment on the polycrystalline silicon layer on the back surface of the silicon wafer by adopting ammonia gas; wherein the flow of the ammonia gas is 10000sccm, the hydrotreating time is 30s, the pressure is 1500 mTorr, and the power is 14000W;
(10) Back side preparation antireflection structure: depositing silicon oxynitride and silicon nitride on the surface of the polysilicon layer of the silicon wafer after plasma etching, wherein the thickness is 85nm;
(11) Front and back printed electrode grid lines: electrode grid lines are printed on the surface of the passivation film and the surface of the anti-reflection structure respectively, and the crystalline silicon battery is prepared through sintering.
Example 2
Substantially the same as in example 1, except that in step (8) of example 2, the plasma etching time was 100s, step (8) was as follows:
(8) Carrying out plasma etching on the intermediate obtained in the step (7) by adopting ammonia gas; wherein, the flow of the ammonia is 12000sccm, the temperature of the plasma etching is 500 ℃, the power is 13500W, the pressure is 1800 mTorr, and the time is 100s.
Example 3
Substantially the same as in example 1, except that in step (8) of example 3, the plasma etching time was 300s, step (8) was as follows:
(8) Carrying out plasma etching on the intermediate obtained in the step (7) by adopting ammonia gas; wherein, the flow of the ammonia is 12000sccm, the temperature of the plasma etching is 500 ℃, the power is 13500W, the pressure is 1800 mTorr, and the time is 300s.
Example 4
Substantially the same as in example 1, except that in step (8) of example 4, the power of plasma etching was 10000W, step (8) was as follows:
(8) Carrying out plasma etching on the intermediate obtained in the step (7) by adopting ammonia gas; wherein the flow of the ammonia gas is 12000sccm, the temperature of plasma etching is 500 ℃, the power is 10000W, the pressure is 1800 mTorr, and the time is 200s.
Example 5
Substantially the same as in example 1, except that the power of plasma etching was 15000W, example 5, step (8), was as follows:
(8) Carrying out plasma etching on the intermediate obtained in the step (7) by adopting ammonia gas; wherein, the flow of the ammonia gas is 12000sccm, the temperature of plasma etching is 500 ℃, the power is 15000W, the pressure is 1800 mTorr, and the time is 200s.
Example 6
Substantially the same as in example 1, except that in step (8) of example 6, the flow rate of ammonia gas was 15000sccm, and step (8) was as follows:
The flow of ammonia gas was 15000sccm, the temperature of plasma etching was 500 ℃, the power was 13500W, the pressure was 1800 mTorr, and the time was 200s.
Example 7
Substantially the same as in example 1, except that in step (8) of example 7, the flow rate of ammonia gas was 10000sccm, and step (8) was as follows:
the flow of ammonia is 10000sccm, the temperature of plasma etching is 500 ℃, the power is 13500W, the pressure is 1800 mTorr, and the time is 200s.
Comparative example 1
Substantially the same as in example 1, except that in step (8) of comparative example 1, ammonia gas was replaced with dinitrogen monoxide (laughing gas), and other parameters were the same; the step (8) is as follows:
(8) Performing plasma etching on the intermediate obtained in the step (7) by adopting nitrous oxide; wherein, the flow of nitrous oxide is 12000sccm, the temperature of plasma etching is 500 ℃, the power is 13500W, the pressure is 1800 mTorr, and the time is 200s.
Comparative example 2
Substantially the same as in example 1, except that in step (8) of comparative example 3, the gas used for plasma etching was a mixed gas of ammonia gas and nitrous oxide, and the flow rates of ammonia gas and nitrous oxide were 6000sccm; the step (8) is as follows:
(8) Carrying out plasma etching on the intermediate obtained in the step (7) by adopting mixed gas of ammonia and nitrous oxide; wherein, the flow of ammonia is 6000sccm, the flow of nitrous oxide is 6000sccm, the temperature of plasma etching is 500 ℃, the power is 13500W, the pressure is 1800 mTorr, and the time is 200s.
Comparative example 3
Substantially the same as in example 1, except that in step (4) of comparative example 3, the thickness of the Poly layer was 80nm, and step (8) was omitted, specifically, the following was adopted:
(1) Cleaning and texturing an N-type silicon wafer, and forming a pyramid textured structure on the surface of the silicon wafer;
(2) Performing boron expansion on the front surface of the cleaned and textured silicon wafer to form a P-type region so as to prepare a PN junction;
(3) Alkali polishing is carried out on the back of the silicon wafer, and PN junctions from the degree of winding to the back and the edge of the silicon wafer when the front boron expansion is carried out in the step (2) are removed;
(4) Sequentially preparing a tunneling oxide layer and a Poly layer (polysilicon layer) on the back of the silicon wafer after alkali polishing, wherein the tunneling oxide layer is a SiO2 layer with the thickness of 1.5nm; the thickness of the Poly layer is 80nm;
(5) RCA cleaning, namely removing a tunneling oxide layer and a polycrystalline silicon layer which are wound to the front side of the silicon wafer when the tunneling oxide layer and the Poly layer are prepared on the back side of the silicon wafer in the step (4);
(6) ALD front deposition of alumina: depositing an alumina (Al 2O 3) film layer on the PN junction surface of the silicon wafer after RCA cleaning, wherein the thickness is 8nm;
(7) Preparing a passivation film on the front surface: depositing silicon oxynitride, silicon nitride and silicon oxide on the surface of the aluminum oxide film layer, wherein the thickness is 75nm;
(8) Carrying out hydrogenation treatment on the polycrystalline silicon layer on the back surface of the silicon wafer by adopting ammonia gas; wherein the flow of the ammonia gas is 10000sccm, the hydrotreating time is 30s, the pressure is 1500 mTorr, and the power is 14000W;
(9) Back side preparation antireflection structure: depositing silicon oxynitride and silicon nitride on the surface of the polysilicon layer of the silicon wafer after plasma etching, wherein the thickness is 85nm;
(10) Front and back printed electrode grid lines: and printing electrode grid lines on the surface of the first passivation film layer and the surface of the second passivation film layer respectively, and sintering to prepare the crystalline silicon battery.
The performance of the crystalline silicon batteries prepared in each example and comparative example was tested, and the IV test was performed using an electrochemical workstation under the following test conditions: as an analog light source, a xenon lamp of AM1.5 was used. The results are shown in table 1 below, in which the photoelectric conversion efficiency, open circuit voltage, and short circuit current of comparative example 3 are taken as references, and are denoted as 0, and the photoelectric conversion efficiency improvement rates of other examples and comparative examples=the photoelectric conversion efficiency of other examples or comparative examples-the photoelectric conversion efficiency of comparative example 3, the open circuit voltage improvement rates of other examples and comparative examples=the open circuit voltage of other examples or comparative examples-the open circuit voltage of comparative example 3, and the short circuit current improvement rates of other examples and comparative examples=the short circuit current of other examples or comparative examples-the short circuit current of comparative example 3.
TABLE 1
As can be seen from table 1, compared with comparative example 3, the thickness of the Poly layer is directly controlled to 80nm, the Poly layer with a thickness greater than that is prepared in each example, and then the Poly layer is thinned by plasma etching, so that the uniformity of the obtained Poly layer is better than that of comparative example 3, and the photoelectric conversion efficiency of the crystalline silicon cell prepared in each example is greatly improved; in contrast, in comparative examples 1 and 2, the Poly layer was thinned by plasma etching using laughing gas or a combination of laughing gas and ammonia gas, and the photoelectric conversion efficiency of the prepared crystalline silicon cell was improved less than that of the example, and the analysis suggested that the oxygen ion ionized from laughing gas was larger in radius, and damage was caused to the Poly layer, resulting in poor uniformity.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more.
In the description of the present application, "plurality" means two or more.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the application, the scope of which is defined by the claims and their equivalents.

Claims (16)

1. The manufacturing method of the crystalline silicon battery is characterized by comprising the following steps:
Providing a substrate, a tunneling oxide layer positioned on the back surface of the substrate, and a polysilicon layer positioned on one side of the tunneling oxide layer away from the substrate;
And carrying out hydrotreatment on the polycrystalline silicon layer, and forming an anti-reflection structure on one side of the polycrystalline silicon layer, which is away from the tunneling oxide layer.
2. The method for manufacturing a crystalline silicon cell according to claim 1, wherein the anti-reflection structure comprises a first anti-reflection layer and a second anti-reflection layer;
The hydrotreating is performed on the polysilicon layer, and an antireflection structure is formed on one side of the polysilicon layer away from the tunneling oxide layer, including:
performing first hydrotreatment on the polysilicon layer by adopting hydrogen-containing gas;
forming the first anti-reflection layer on one side of the polycrystalline silicon layer, which is away from the tunneling oxide layer;
performing second hydrotreatment on the polysilicon layer by adopting hydrogen-containing gas;
And forming the second anti-reflection layer on one side of the first anti-reflection layer, which is away from the polycrystalline silicon layer.
3. The method for manufacturing a crystalline silicon cell according to claim 2, wherein the anti-reflection structure further comprises a third anti-reflection layer;
The hydrotreating is performed on the polysilicon layer, and an antireflection structure is formed on one side of the polysilicon layer away from the tunneling oxide layer, and the method further comprises:
Performing third hydrotreatment on the polysilicon layer by adopting hydrogen-containing gas;
and forming the third anti-reflection layer on one side of the second anti-reflection layer, which faces away from the first anti-reflection layer.
4. The method for manufacturing a crystalline silicon cell according to claim 3, wherein the hydrogen-containing gas comprises ammonia gas.
5. The method of claim 4, wherein the first hydrotreatment satisfies at least one of the following characteristics:
The flow of the ammonia gas is 10000 sccm-15000 sccm;
the first hydrotreating time is 30 s-50 s;
The pressure of the first hydrotreatment is 1500 mTorr-2000 mTorr;
the power of the first hydrotreatment is 14000W-17000W.
6. The method of claim 4, wherein the second hydrotreatment satisfies at least one of the following characteristics:
The flow rate of the ammonia gas is 11000 sccm-16000 sccm;
the first hydrotreating time is 30 s-50 s;
The pressure of the first hydrotreatment is 1500 mTorr-2000 mTorr;
the power of the first hydrotreatment is 14000W-17000W.
7. The method of manufacturing a crystalline silicon cell according to claim 4, wherein the third hydrotreatment satisfies at least one of the following characteristics:
The flow rate of the ammonia gas is 11000 sccm-16000 sccm;
the first hydrotreatment time is 40-80 s;
The pressure of the first hydrotreatment is 1500 mTorr-2000 mTorr;
the power of the first hydrotreatment is 14000W-17000W.
8. The method of claim 3, wherein the first, second, and third anti-reflection layers each comprise at least one passivation layer.
9. The method of claim 8, wherein the first and second anti-reflection layers each comprise a passivation layer, and the third anti-reflection layer comprises three passivation layers stacked.
10. The method of claim 8, wherein the refractive index of the passivation layer gradually decreases in a direction of the polysilicon layer away from the tunnel oxide layer.
11. The method according to any one of claims 1 to 10, wherein before the hydrotreating the polysilicon layer to form an anti-reflection structure on a side of the polysilicon layer facing away from the tunnel oxide layer, the method further comprises:
And carrying out thickness thinning treatment on the polysilicon layer.
12. The method for manufacturing a crystalline silicon cell according to claim 11, wherein the thickness reduction treatment of the polysilicon layer comprises:
and carrying out plasma etching on the polycrystalline silicon layer by adopting plasma gas so as to thin the thickness of the polycrystalline silicon layer.
13. The method of claim 12, wherein the plasma gas comprises ammonia.
14. The method of claim 13, wherein the plasma etching satisfies at least one of the following characteristics:
The flow of the ammonia gas is 10000 sccm-15000 sccm
The temperature of the plasma etching is 450-550 ℃;
The power of the plasma etching is 10000W-15000W;
the pressure of the plasma etching is 1500 mTorr-2000 mTorr;
the plasma etching time is 100 s-300 s.
15. The method of claim 11, wherein the thickness of the polysilicon layer is reduced to 5nm to 10nm.
16. A crystalline silicon cell, characterized in that it is formed by the method for manufacturing a crystalline silicon cell according to any one of claims 1 to 15.
CN202410577858.8A 2024-05-10 2024-05-10 Manufacturing method of crystalline silicon battery and crystalline silicon battery Pending CN118281118A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202410577858.8A CN118281118A (en) 2024-05-10 2024-05-10 Manufacturing method of crystalline silicon battery and crystalline silicon battery

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202410577858.8A CN118281118A (en) 2024-05-10 2024-05-10 Manufacturing method of crystalline silicon battery and crystalline silicon battery

Publications (1)

Publication Number Publication Date
CN118281118A true CN118281118A (en) 2024-07-02

Family

ID=91641955

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202410577858.8A Pending CN118281118A (en) 2024-05-10 2024-05-10 Manufacturing method of crystalline silicon battery and crystalline silicon battery

Country Status (1)

Country Link
CN (1) CN118281118A (en)

Similar Documents

Publication Publication Date Title
CN113972302B (en) TOPCON battery, preparation method thereof and electrical equipment
CN116525708B (en) Front-side wide band gap doped combined passivation back contact solar cell and preparation method thereof
CN111628052B (en) Preparation method of passivated contact battery
WO2023208107A1 (en) Solar cell, preparation method therefor, and application thereof
CN110854240A (en) PERC battery and preparation method thereof
CN111755552A (en) Solar cell and manufacturing method thereof
EP4152417A1 (en) Solar cell, manufacturing method thereof, and photovoltaic module
CN117117044B (en) Combined passivation back contact battery and primary annealing preparation method thereof
CN111987182A (en) TOPCon solar cell and manufacturing method thereof
CN114792744B (en) Solar cell and preparation method and application thereof
CN111599898A (en) Method for manufacturing crystalline silicon solar cell and crystalline silicon solar cell
CN114335237B (en) Preparation method of crystalline silicon solar cell and crystalline silicon solar cell
CN115832069A (en) Passivation contact structure, solar cell, preparation method and photovoltaic module
CN114597267A (en) TOPCon battery and preparation method thereof
CN114883427B (en) Crystalline silicon heterojunction solar cell structure and preparation method thereof
CN116247123A (en) Preparation method of P-type back tunneling oxidation passivation contact solar cell
CN116741877A (en) TBC battery preparation method and TBC battery
CN116314471A (en) Preparation method of rear SE structure
CN117673207B (en) Preparation method of solar cell, solar cell and photovoltaic module
WO2024160191A1 (en) Solar cell and preparation method therefor
WO2022156101A1 (en) Solar cell stack passivation structure and preparation method therefor
CN117038799A (en) BC battery preparation method and BC battery
AU2023349665A1 (en) Solar cell and manufacturing method therefor
CN115377226A (en) Selective emitter structure, preparation method and selective emitter crystalline silicon battery
CN111755563B (en) P-type monocrystalline silicon boron back-field double-sided battery and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination