CN118275744B - Optical device test protection circuit and optical device test system - Google Patents
Optical device test protection circuit and optical device test system Download PDFInfo
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Abstract
The invention relates to the technical field of electrical elements, and particularly discloses an optical device testing protection circuit and an optical device testing system, wherein the optical device testing protection circuit comprises a control unit, a connection detection unit, a switch enabling unit and a load switching unit, wherein the control unit is respectively and electrically connected with the connection detection unit and the load switching unit, the switch enabling unit is respectively and electrically connected with the connection detection unit and the load switching unit, and the load switching unit selectively connects an optical device load or a discharge load; the switch enabling unit is configured with an interface for connecting a power supply, the connection detection unit is used for detecting the connection state of the optical device and the test board, and the control unit controls the switch enabling unit to switch on or off the power supply according to the connection state and controls the load switching unit to switch on the optical device load or the discharge load. The invention can effectively protect the optical device from being damaged by live plugging and pulling and improve the test efficiency.
Description
Technical Field
The invention relates to the technical field of optical devices, in particular to an optical device test protection circuit and an optical device test system.
Background
In the production process of the optical device, in order to ensure the delivery performance, the optical device needs to be tested in a multifunctional mode, and the optical device needs to be frequently connected into a test board and then taken out of the test board. In the normal practice, the flexible circuit board FPC of the optical device is directly connected to the test board in a crimping mode, or is connected to the test board through a quick connector, and after the test is finished, the connection with the test board is disconnected, and the optical device is taken out. And then the next optical device is continuously connected, and the operation is repeated to realize batch testing operation.
Under normal conditions, before the optical device is plugged/unplugged, the test board needs to be completely powered off to stop working, namely, the connection and disconnection operation of the optical device is carried out under the condition that the test board is completely unpowered, but in practical application, the fact that the test board is powered off due to the existence of a capacitor on the test board, even if the test is completed, a power supply loop of the test board is cut off, and part of residual voltage still exists on the actual test board, and at the moment, when the optical device is plugged/unplugged, soft damage of the optical device can be caused due to instantaneous impact current. This damage, in turn, is occasional and difficult to find. In order to avoid the situation, the test circuit board can be completely discharged after being powered off for a long time to finish the operation of plugging the device, and the operation is safe, but the waiting time is increased to influence the test efficiency.
Disclosure of Invention
The first object of the present invention is to improve the problem that the optical device is damaged due to the residual voltage after the test board is powered off, and to provide an optical device test protection circuit, which not only can protect the optical device from being damaged due to hot plug, but also can improve the test efficiency of the optical device.
The second purpose of the invention is to improve the problem of damage to the optical device caused by live plugging of the optical device due to software abnormality or human misoperation, and further improve and optimize the optical device test protection circuit.
In order to achieve the above object, the present invention provides the following technical solutions:
The optical device test protection circuit comprises a control unit, a connection detection unit, a switch enabling unit and a load switching unit, wherein the control unit is respectively and electrically connected with the connection detection unit and the load switching unit; the switch enabling unit is configured with an interface for connecting a power supply, the connection detection unit is used for detecting the connection state of the optical device and the test board, and the control unit controls the switch enabling unit to switch on or off the power supply according to the connection state and controls the load switching unit to switch on the optical device load or the discharge load.
In the scheme, the connection detection unit and the load switching unit are arranged, when the connection detection unit detects that the optical device is connected with the test board, the control unit controls the load switching unit to switch on the optical device load, and simultaneously controls the switch enabling unit to switch on the power supply, so that the power supply can supply power for the rear-stage load switching unit and the optical device load, and normal test of the optical device is realized; after the test is finished, the optical device is disconnected from the test board, and the connection detection unit detects that the optical device is disconnected from the test board, the control unit controls the load switching unit to switch on the discharge load so as to accelerate discharge, and meanwhile controls the switch enabling unit to switch off the power supply, so that the power supply does not supply power any more. Through the discharge load acceleration discharge, can make residual voltage release as early as possible in the test board, can ensure on the one hand that current optical device is taking off under the electroless state, avoid damaging because of electrified plug, on the other hand can accelerate to connect next optical device and test, has improved test efficiency promptly.
The connection detection unit comprises a first logic detection module and a second logic detection module, wherein the output end of the first logic detection module is connected with the switch enabling unit, the input end of the first logic detection module is connected with the control unit, the output end of the second logic detection module is connected with the control unit, and the input end of the second logic detection module is connected with the test board.
In the above scheme, the second logic detection module is mainly used for detecting the connection state of the optical device and the test board, and the first logic detection module is mainly used for outputting a corresponding trigger signal under the control of the control unit to trigger the switch enabling unit to switch on or off the power supply. Because the hardware logic detection mode is adopted, even if the SOFT abnormality causes live working, the power supply is rapidly cut off by the hardware once the bonding pad of the FPC is detected to be separated from the test board, so that the protection purpose is achieved, the reliability is high, and the response time is short.
The second logic detection module is a NOR gate module, the output end of the NOR gate module is simultaneously connected with one input end of the first logic detection module, a second GPIO port of the control unit and the input end of the load switching unit through the isolation resistor, and the four input ends of the NOR gate module are respectively connected with the four bonding pads of the test board.
In the scheme, the second logic detection module is realized by adopting the NOR gate circuit, as long as one of the four input ends is in the off state, the detection result is considered as the off state, then the switch enabling unit is triggered to disconnect the power supply, and the whole circuit is in the power-off state, and the second logic detection module is a hardware circuit, so that the response time of the abnormality is extremely short, and the power supply of the test board is effectively disconnected. The protection purpose is achieved.
The first logic detection module is an AND gate module comprising two input ends, and the other input end of the AND gate module is connected with a first GPIO port of the control unit.
In the scheme, the double-input AND gate module is low as long as one input is low in output, the implementation mode is simple, and the complexity and the cost of the circuit are reduced.
The switch enabling unit comprises a PMOS tube, an NMOS tube and a first resistor, wherein the grid electrode of the PMOS tube is connected with the drain electrode of the NMOS tube, the source electrode of the PMOS tube is used for being connected with a power supply, the drain electrode of the PMOS tube is connected with the load switching unit, the source electrode of the NMOS tube is grounded, the grid electrode of the NMOS tube is connected with the output end of the first logic detection module, and the two ends of the first resistor are respectively connected with the source electrode of the PMOS tube and the drain electrode of the NMOS tube.
The load switching unit comprises a switch, a first diode, a triode and a fourth resistor, one end of the switch is connected with the switch enabling unit, the other end of the switch selectively connects with the optical device load or the discharge load, the negative electrode end of the first diode is connected with the positive electrode pin of the switch, the positive electrode end of the first diode is connected with the negative electrode pin of the switch and the collector electrode of the triode, the emitter electrode of the triode is grounded, and the base electrode of the triode is connected with the output end of the second logic detection module through the fourth resistor.
The second GPIO port of the control unit is configured as a bidirectional input/output port, the base electrode of the triode is also connected with the second GPIO port of the control unit through the fourth resistor, and the control unit outputs a control signal to the triode to be continuously disconnected or closed through the second GPIO port according to the input signal of the second logic detection module;
Or the base electrode of the triode is connected with a third GPIO port of the control unit through the fourth resistor, the base electrode of the triode is connected with the output end of the second logic detection module through the second diode, and the control unit outputs a control signal to the triode through the third GPIO port according to the input signal of the second logic detection module to be continuously disconnected or closed.
In the two schemes, the second GPIO port of the control unit is configured as the bidirectional input/output port, or the base electrode of the triode is connected with the third GPIO port of the control unit through the fourth resistor, when the connection state is detected to be disconnected, the triode can be continuously disconnected from the software angle, then the load of the optical device is protected, and the problem that the optical device is damaged due to the fact that the optical device is plugged in and pulled out in an electrified mode due to software abnormality or manual misoperation is solved.
The automatic discharging device further comprises a discharging detection unit and a state indication unit, wherein the discharging detection unit is respectively and electrically connected with the control unit and the switch enabling unit, the state indication unit is electrically connected with the control unit and is used for detecting a discharging ending state, and the control unit controls the state indication unit to output a first indication signal according to the discharging ending state.
In the scheme, the discharge end state is detected through the discharge detection unit, and the corresponding display is performed through the state indication unit, so that an operator can conveniently and accurately determine whether the current optical device can be canceled and the next optical device to be tested is connected, the reliability of optical device protection is improved, and the auxiliary test efficiency is further improved.
The discharge detection unit comprises a second resistor and a third resistor, one end of the second resistor is connected with the switch enabling unit, the other end of the second resistor is connected with one end of the third resistor, the other end of the third resistor is grounded, and an intersection point of the second resistor and the third resistor is connected with an ADC interface of the control unit.
The state indicating unit comprises a first indicating module and a second indicating module, wherein the first indicating module is used for indicating the discharge ending state, and the second indicating module is used for indicating the abnormal disconnection locking state.
In the scheme, the discharge end state and the abnormal disconnection locking state are respectively indicated by different indication modules, so that the two indication modules are not mutually interfered, the recognition error is avoided, and the effectiveness of the indication effect is improved.
The optical device testing system comprises a testing board and further comprises an optical device testing protection circuit, wherein the testing board is provided with a first bonding pad and a second bonding pad, the first bonding pad is used for being electrically connected with an optical device load, the second bonding pad is used for being connected with a connection detection unit, and a discharge load is installed on the testing board.
The invention has the following beneficial effects:
The invention mainly solves the problem of abnormal electrified disassembly and assembly of the optical device in the test process. When the connection detection unit detects that the optical device is connected with the test board, the control unit controls the load switching unit to switch on the optical device load, and simultaneously controls the switch enabling unit to switch on the power supply, so that the power supply can supply power for the rear-stage load switching unit and the optical device load, and normal test of the optical device is realized; after the test is finished, the optical device is disconnected from the test board, and the connection detection unit detects that the optical device is disconnected from the test board, the control unit controls the load switching unit to switch on the discharge load so as to accelerate discharge, and meanwhile controls the switch enabling unit to switch off the power supply, so that the power supply does not supply power any more. Through the discharge load acceleration discharge, can make residual voltage release as early as possible in the test board, can ensure on the one hand that current optical device is taking off under the electroless state, avoid damaging because of electrified plug, on the other hand can accelerate to connect next optical device and test, has improved test efficiency promptly.
The invention has the biggest characteristics that on the premise of not changing the original test scheme, only part of bonding pads of the test board are decomposed to form detection points, the multi-point simultaneous detection can be flexibly realized, the circuit designs a quick discharge loop when cutting off a power supply loop, the discharge time is effectively saved, and the purpose of quickly releasing the residual power supply is achieved, so that the timeliness and the safety are extremely high.
Drawings
Fig. 1 is a block diagram showing the components of an optical device test protection circuit provided in the embodiment.
Fig. 2a, 2b, 2c, and 2d are partial diagrams of electrical schematic diagrams of the optical device test protection circuit provided in the embodiment, respectively.
Fig. 3 is a schematic diagram illustrating connection between a triode Q3 and an MCU or a nor module U2 in another optical device test protection circuit according to an embodiment.
Fig. 4 is a diagram showing the correspondence between pads of the original test board and pads of the FPC.
Fig. 5 is a graph showing the correspondence between pads of the improved test board and pads of the FPC.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
Referring to fig. 1, the optical device test protection circuit provided in this embodiment includes a control unit, a connection detection unit, a switch enabling unit, a load switching unit, a discharge detection unit and a status indication unit, where the control unit is electrically connected with the connection detection unit, the load switching unit, the discharge detection unit and the status indication unit, and the switch enabling unit is electrically connected with the connection detection unit and the load switching unit, respectively.
When the light device load is applied, the light device load is connected with the test board through the flexible circuit board, the connection detection unit is used for detecting the connection state of the flexible circuit board and the test board, the connection state of the flexible circuit board and the test board is used as an input signal of the switch enabling unit, the switch enabling unit is used for switching off or switching on a power supply according to the input signal, the connection state of the flexible circuit board and the test board is simultaneously transmitted to the control unit, and the control unit actively controls the load switching unit to switch and connect the discharge load or the light device load.
Fig. 2a, fig. 2b, fig. 2c, fig. 2d are partial diagrams of electrical schematic diagrams of the optical device test protection circuit provided in the embodiment, respectively, and the electrical schematic diagrams are combined to form a complete electrical schematic diagram. Referring to fig. 2a, fig. 2b, fig. 2c, in this embodiment, the control unit is implemented by using an MCU, the connection detection unit includes an and gate module U1 and a nor gate module U2, the output end (pin 4) of the and gate module U1 is connected to the switch enabling unit (gate of the NMOS tube Q2), one input end of the and gate module U1 is connected to the first GPIO port GPIO1 of the MCU, the output end of the nor gate module U2 is simultaneously connected to the other input end of the and gate module U1, the second GPIO port GPIO2 of the MCU is connected to the load switching unit (base of the triode Q3) through the isolation resistor R11, the four input ends of the nor gate module U2 are respectively connected to the four pads of the test board, and each input end is further connected to the power VCC through a resistor (respectively, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9). The isolation resistor R11 can avoid burning out the port when the level signal of the GPIO2 is inconsistent with the output level signal of the nor gate module U2.
Referring to fig. 2a and 2b, in this embodiment, the switch enabling unit includes a PMOS transistor Q1, an NMOS transistor Q2, and a first resistor R1, where a gate of the PMOS transistor Q1 is connected to a drain of the NMOS transistor Q2, a source of the PMOS transistor Q1 is connected to a power supply PWR, a drain of the PMOS transistor Q1 is connected to the load switching unit, a source of the NMOS transistor Q2 is grounded, and a gate of the NMOS transistor Q2 is connected to an output pin of the and gate module U1 in the connection detecting unit. Two ends of the first resistor R1 are respectively connected with the source electrode of the PMOS tube Q1 and the drain electrode of the NMOS tube Q2.
It should be noted that, fig. 2b shows that the drain electrode of PMOS transistor Q1 is connected to PWBA, which is merely an indication that the capacitor exists in the entire circuit of test board PWBA, and the capacitor will be discharged through this route, not an indication that the test board is connected thereto. The power supply PWR may not be an external power supply, but may be an external power supply, so as to provide a voltage for testing.
Referring to fig. 2a and 2D, in the present embodiment, the load switching unit includes a switch rliy 1, a first diode D1, a triode Q3 and a fourth resistor R10, one end of the switch rliy 1 is connected to the switch enabling unit (drain of the PMOS transistor Q1), and the other end of the switch rliy 1 is selectively connected to the optical device load R4 or the discharge load R5. The first diode D1 is a freewheeling diode of the switch rliy 1, and is configured to absorb reverse voltage generated by the coil when the switch rliy 1 is turned on and turned off, the cathode terminal of the first diode D1 is connected to the anode pin of the switch rliy 1, the anode terminal of the first diode D1 is connected to the cathode pin of the switch rliy 1 and the collector of the (NPN) triode Q3, the emitter of the triode Q3 is grounded, the base of the triode Q3 is connected to the second GPIO port GPIO2 of the MCU through the fourth resistor R10, and at this time, the second GPIO port GPIO2 of the MCU is a bidirectional input/output port.
Referring to fig. 3, in another structure, a base of a triode Q3 is connected to a third GPIO port GPIO3 of the MCU through a fourth resistor R10, and is connected to an output end of the nor gate module U2 through a second diode D2, and a base of the triode Q3 is connected to an anode end of the second diode D2, at this time, an output signal of the second logic detection module U2 is received by the second GPIO port GPIO2 of the MCU, and then the third GPIO port GPIO3 of the MCU outputs a control signal to the triode Q3. In this scheme, GPIO1 is used as an output port to output a level signal to the and gate module U1, GPIO2 is used as an input port to the nor gate module U2, the output signal is input to the MCU through GPIO2, and GPIO3 is used as an output port to output a level signal to the transistor Q3. When the nor gate module U2 outputs a low level signal logic 0, the transistor Q3 is turned off through the isolation resistor R11 and the second diode D2, the GPIO2 detects that the and gate module U1 is 0, and the GPIO3 outputs a low level signal logic 0 to continuously turn off the transistor Q3. When the nor gate module U2 outputs a high level signal logic 1, the second diode D2 is turned off, the GPIO2 detects that the and gate module U1 is high level, and the GPIO3 outputs a high level signal logic 1 to turn on the transistor Q3.
The optical device load R4 is only connected to the optical device test protection circuit when the test is needed, and is not connected to the optical device test protection circuit when the test is not needed; the discharging load R5 is arranged in the test board and is used for rapidly releasing the residual voltage after the test board is powered off.
Referring to fig. 2a, fig. 2b, and fig. 2d, the discharge detection unit in this embodiment includes a second resistor R2 and a third resistor R3 connected in series, one end of the second resistor R2 is connected to the switch enabling unit (drain of the PMOS transistor Q1), the other end of the second resistor R2 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is grounded. And the intersection point of the second resistor R2 and the third resistor R3 is connected with an ADC interface of the MCU.
The second GPIO port GPIO2 of the MCU is configured as a bidirectional input/output port, or the output of the AND gate module U2 can be used as an input signal to be input into the MCU through the second GPIO port GPIO2, the MCU can also output a control signal to the triode Q3 according to the input signal to enable the triode Q3 to be disconnected or closed, and when an operator or software SOFT is abnormal, the triode Q3 is disconnected, so that the whole circuit is in an abnormal disconnection locking state, and the aim of protecting an optical device is achieved.
In order not to influence the normal use of the test board, the test protection circuit of the optical device can be connected into the test board, so that the original four bonding pads on the test board are improved. As shown in fig. 4, before the pads of the test board are not changed, the pads of the flexible circuit board and the pads of the test board are 1 to 1, and in normal test, the pads of the FPC of the flexible circuit board are covered on the pads of the test board PWBA, and then the power-on test is performed. After the test is completed, the FPC is detached PWBA. The modified design is shown in fig. 5, in which the individual pads on the test board PWBA are decomposed into 2 or more, 1 of which is used for the continuous state test, such as PD1, PD2, PD3, PD4 shown in fig. 2c, which may be referred to as a first pad, and the remaining pads PD5, PD6, PD7, PD8 may be referred to as second pads, so as to maintain the original network characteristics. When the pads of the flexible circuit board FPC are connected to the test board, the connection detection unit detects 0 and the original pad function is not affected at all. The connection state of the whole row of bonding pads can be ensured to be detected by designing and decomposing at least two bonding pads, and if the connection of the FPC is inclined or is broken, the test board is not electrified, so that the protection purpose is achieved.
Referring to fig. 2c, PD1, PD2, PD3, and PD4 are independent detection pads decomposed from original pads on the test board, when the pads of the optical device load flexible circuit board are covered on the pads of the test board, PD1 and PD5 are conducted, PD2 and PD6 are conducted, PD3 and PD7 are conducted, PD4 and PD8 are conducted, and since PD5, PD6, PD7, and PD8 are all grounded, at this time, pins 1,2,3, and 4 of the nor gate module U2 are respectively low, the logic of the nor gate module U2 is determined to be 0 input, and since the nor gate module U2 is a "nor gate" function (1 out 0, all 0 out 1), the output terminal q\ (pin 6) of the nor gate module U2 is 1 at this time, which indicates that all test points are well connected. At this time, when the second GPIO port GPIO2 of the MCU detects 1, the control state indicating unit STS outputs a state indicating signal, indicating that the flexible circuit board is well connected with the test board. As an example, the status indication unit may include an indication lamp which is controlled to be turned on when the second GPIO port GPIO2 of the MCU detects 1 and turned off when the second GPIO port GPIO2 of the MCU detects 0.
In the structures shown in fig. 2a, 2b, 2c and 2d, the second GPIO port GPIO2 of the MCU is a bi-directional input/output port, when the second GPIO port GPIO2 of the MCU detects 1, a high level is output, so that the triode Q3 is kept on, then the switch rliy 1 is powered on, the contact 3 pin and the contact 4 pin of the switch rliy 1 are connected, the switching is performed to the optical device load R4, and the voltage output by the power supply PWR flows to the optical device load R4 through the switch rliy 1 to supply power to the optical device load R4. And the high level of the second GPIO port GPIO2 of the MCU (or the third GPIO port GPIO3 of the MCU in the structure shown in fig. 3) is output to the 2 nd pin of the and gate module U1, and the and gate module U1 is a dual-input and gate circuit, i.e. "0 out, all 1 out 1", and at this time, the 4 th pin (output end) state of the and gate module U1 is only determined by the 1 st pin, and is determined by the output signal of the first GPIO port GPIO1 of the MCU. When pin 1 of the and gate module U1 is at a high level (output 1), pin 4 of the and gate module U1 outputs 1, since Vgs >0 of the NMOS transistor Q2 is turned on, and at this time, the drain and the source of the NMOS transistor Q2 are turned on, vds of the NMOS transistor Q2 is almost 0, and therefore the gate voltage of the PMOS transistor Q1 is 0, and since the source voltage of the PMOS transistor Q1 is VCC1, vgs <0 of the PMOS transistor Q1 is approximately equal to-VCC 1, the PMOS transistor Q1 is turned on, VCC2 is powered on, and since the switch rli 1 turns on the optical device load R4, the optical device load R4 is connected to the test board PWBA, and the test board PWBA is powered on. When pin 1 of the and gate module U1 is at a low level (output 0), pin 4 of the and gate module U1 outputs 0, and since the gate voltage of the NMOS transistor Q2 is equal to the source voltage, i.e., vgs=0 of the NMOS transistor Q2, the NMOS transistor Q2 is turned off, i.e., the drain and the source of the NMOS transistor Q2 are turned off. Because the first resistor R1 acts, the source voltage and the gate voltage of the PMOS transistor Q1 are equal at this time, that is, vgs=0 of the PMOS transistor Q1, so the PMOS transistor Q1 is also turned off, VCC1 cannot be transmitted to VCC2 through the PMOS transistor Q1, that is, VCC2 is powered off, the whole circuit of the subsequent stage is powered off, and the test board is powered off.
When any one bonding pad of the PD1, the PD2, the PD3 and the PD4 is in poor connection, for the NOR gate module U2, the input level is changed to 1, the 6 th pin of the NOR gate module U2 outputs 0, at the moment, the second GPIO port GPIO2 of the MCU detects 0 and outputs a low level signal 0 to the triode Q3 and the AND gate module U1, the triode Q3 is disconnected, the switch RLY1 is disconnected, meanwhile, the 4 th pin of the AND gate module U1 outputs 0, the PMOS tube Q1 is disconnected, the VCC2 is unpowered, and the whole test board is powered off. At this time, the abnormal disconnection locking state is achieved, and a corresponding indication signal can be sent out through the state indication circuit.
When the second GPIO port GPIO2 detects 0, a low level is output, or when VCC2 is not powered, the switch RLY1 is powered off, the contact 3 pin is connected with the contact 2 pin, the switch is switched to the discharge load R5, and the discharge load R5 accelerates the rapid discharge of the test board. At the same time, the optics load R4 will be de-energized because the contact 3 pin is disconnected from the contact 4 pin.
In the discharge detection unit, VCC 3=r3/(r2+r3) ×vcc2, where VCC3 is connected with an ADC interface of the MCU, when the ADC interface of the MCU detects that VCC3 is 0, that is, VCC2 is indicated as 0, at this time, the whole test board has no residual voltage, and at this time, the MCU may send a corresponding indication signal through the status indication circuit, for example, control the corresponding indicator light to be turned on, so as to prompt the operator to take down the current optical device load R4, and then ensure that the taking down of the current optical device load R4 and the connection of the next optical device load to be tested are all operated in the electroless state, so as to protect the optical device from damage. When the ADC detects that VCC3 is not 0, the residual voltage exists on the test board, and the MCU can send out a corresponding indication signal through the state indication circuit, for example, the corresponding indication lamp is controlled to be turned off.
For convenience of distinction, in a specific implementation, the state indicating circuit includes a first indicating module for indicating a discharge end state and a second indicating module for indicating an abnormal disconnection lock state.
Principle of action: as described above, the pad of the FPC is normally connected to PWBA, and all input signals of the nor gate module U2 are at logic 0 level, and at this time, the 6 th pin of the nor gate module U2 outputs logic 1 (high level signal) which is input to the base of the transistor Q3, the transistor Q3 is turned on, and the switch rli 1 is turned on to the optical device load R4. Meanwhile, the logic 1 output by the 6 th pin of the nor gate module U2 is transmitted to the second GPIO port GPIO2 of the MCU, and when the second GPIO port GPIO2 of the MCU detects 1, the logic 1 is output, so that the triode Q3 is kept closed continuously. At this time, the output of the 4 th pin of the AND gate module U1 is determined by the level of the first GPIO port GPIO1 of the MCU, when the first GPIO port GPIO1 of the MCU outputs logic 1, the PMOS tube Q1 is conducted, the test board is electrified, when the first GPIO port GPIO1 of the MCU outputs logic 0, the PMOS tube Q1 is disconnected, and the test board is unpowered. When the MCU detects that the test is finished, the first GPIO port GPIO1 of the MCU outputs logic 0, the PMOS tube Q1 is disconnected, the test board is powered off, meanwhile, the second GPIO port GPIO2 of the MCU outputs logic 0, the switch RLY1 is switched to be connected with the discharge load R5, the release of test residual voltage is accelerated, when the ADC interface of the MCU detects logic 0, the discharge of the test board is finished, the state indication unit STS outputs a corresponding indication signal, and an operator is prompted to be capable of carrying out the disassembly and assembly operation of the FPC. In this case, since the operation is performed in a non-electric state at a fixed time, it is possible to ensure that the optical device load does not have a problem of current surge.
When an operator performs misoperation (for example, the light device load R4 is pulled out after the discharge is not completed) or software SOFT is abnormal, the FPC is disassembled and assembled in a charged mode, at the moment, in PD1, PD2, PD3 and PD4, as long as 1 path of FPC bonding pads are separated from a test board, the input of the nor gate module U2 is detected to be logic 1, at the moment, the 6 th pin of the nor gate module U2 outputs logic 0 and is input to the base electrode of the triode Q3, at the moment, the triode Q3 is disconnected, the switch RLY1 is switched to the discharge load R5 in a power-off mode, and the light device load R4 is protected from hardware. Meanwhile, the second GPIO port GPIO2 of the MCU detects logic 0, at the moment, the first GPIO port GPIO1 of the MCU and the second GPIO port GPIO2 of the MCU both output low-level signals 0, and the logic 0 output by the second GPIO port GPIO2 of the MCU (or the third GPIO port GPIO3 of the MCU in the structure shown in fig. 3) is output to the base electrode of the triode Q3, so that the triode Q3 is continuously disconnected, and then the whole optical device test protection circuit is in an abnormal disconnection locking state, so that signal jump is prevented. And the status indication unit STS outputs an abnormality prompting signal for prompting the operator to perform abnormality processing. Because the logical detection of the nor gate module U2 is a hardware circuit, the response time of the abnormality is extremely short, so that the power supply of the test board can be effectively disconnected, and the protection purpose is achieved.
The circuit of each unit is the best mode, and other circuit design modes are allowed under the condition of realizing the same function. In a more crude design, the discharge detection unit and the status indication unit may also be optional constituent units.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention.
Claims (5)
1. The optical device test protection circuit is characterized by comprising a control unit, a connection detection unit, a switch enabling unit and a load switching unit, wherein the control unit is respectively and electrically connected with the connection detection unit and the load switching unit, the switch enabling unit is respectively and electrically connected with the connection detection unit and the load switching unit, and the load switching unit selectively switches on an optical device load or a discharge load; the switch enabling unit is configured with an interface for connecting a power supply, the connection detection unit is used for detecting the connection state of the optical device and the test board, and the control unit controls the switch enabling unit to switch on or off the power supply according to the connection state and controls the load switching unit to switch on the optical device load or the discharge load;
The connection detection unit comprises a first logic detection module and a second logic detection module, wherein the output end of the first logic detection module is connected with the switch enabling unit, the input end of the first logic detection module is connected with the control unit, the output end of the second logic detection module is connected with the control unit, and the input end of the second logic detection module is connected with the test board;
The second logic detection module is a NOR gate module, the output end of the NOR gate module is simultaneously connected with one input end of the first logic detection module, a second GPIO port of the control unit and the input end of the load switching unit through an isolation resistor, and the four input ends of the NOR gate module are respectively connected with four bonding pads of the test board;
The first logic detection module is an AND gate module comprising two input ends, and the other input end of the AND gate module is connected with a first GPIO port of the control unit;
The switch enabling unit comprises a PMOS tube, an NMOS tube and a first resistor, wherein the grid electrode of the PMOS tube is connected with the drain electrode of the NMOS tube, the source electrode of the PMOS tube is used for being connected with a power supply, the drain electrode of the PMOS tube is connected with the load switching unit, the source electrode of the NMOS tube is grounded, the grid electrode of the NMOS tube is connected with the output end of the first logic detection module, and the two ends of the first resistor are respectively connected with the source electrode of the PMOS tube and the drain electrode of the NMOS tube;
The load switching unit comprises a switch, a first diode, a triode and a fourth resistor, one end of the switch is connected with the switch enabling unit, the other end of the switch selectively connects with the optical device load or the discharge load, the negative electrode end of the first diode is connected with the positive electrode pin of the switch, the positive electrode end of the first diode is connected with the negative electrode pin of the switch and the collector electrode of the triode, the emitter electrode of the triode is grounded, and the base electrode of the triode is connected with the output end of the second logic detection module through the fourth resistor.
2. The optical device testing protection circuit of claim 1, wherein the second GPIO port of the control unit is configured as a bidirectional input/output port, the base of the triode is further connected to the second GPIO port of the control unit through the fourth resistor, and the control unit outputs a control signal to the triode through the second GPIO port according to the input signal of the second logic detection module to be continuously turned off or turned on;
Or the base electrode of the triode is connected with a third GPIO port of the control unit through the fourth resistor, the base electrode of the triode is connected with the output end of the second logic detection module through the second diode, and the control unit outputs a control signal to the triode through the third GPIO port according to the input signal of the second logic detection module to be continuously disconnected or closed.
3. The light device testing protection circuit according to any one of claims 1-2, further comprising a discharge detection unit and a status indication unit, wherein the discharge detection unit is electrically connected to the control unit and the switch enabling unit, respectively, the status indication unit is electrically connected to the control unit, the discharge detection unit is used for detecting a discharge end state, and the control unit controls the status indication unit to output a first indication signal according to the discharge end state.
4. The optical device testing protection circuit according to claim 3, wherein the discharge detection unit comprises a second resistor and a third resistor, one end of the second resistor is connected with the switch enabling unit, the other end of the second resistor is connected with one end of the third resistor, the other end of the third resistor is grounded, and an intersection point of the second resistor and the third resistor is connected with one ADC interface of the control unit.
5. An optical device testing system comprising a test board, and further comprising the optical device testing protection circuit of any one of claims 1-4, the test board providing a first pad for electrically connecting with an optical device load and a second pad for connecting with a connection detection unit, a discharge load being mounted on the test board.
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