CN118261092A - Emulation device - Google Patents

Abstract

The application provides a simulation device, which comprises a communication layer and a bottom layer, wherein the communication layer comprises a controller, the controller is used for being connected with an upper computer, the controller is also used for receiving initial data sent by the upper computer, the controller is used for carrying out preset processing on the initial data to obtain preset data, the controller is also used for sending the preset data, the initial data is used for representing specific content of simulation, and the preset processing at least comprises decoding processing; the bottom layer is connected with the communication layer, the bottom layer comprises a plurality of preset chips, the simulation functions of the preset chips are different, the preset chips in the bottom layer receive preset data sent by the communication layer, and the preset chips complete the simulation process of the preset chips according to the preset data. The simulation functions of the preset chips are different, so that the simulation function of the simulation device is more comprehensive, and the preset chips are chips which are independently researched and developed, so that the corresponding simulation chips do not need to be redesigned to perform simulation test, and the lower cost of the simulation device is ensured.

Description

Emulation device

Technical Field

The application relates to the field of semiconductors, in particular to a simulation device.

Background

With the rapid development of the semiconductor industry and the strong support of the country, many chip design companies emerge in recent years, however, the MCU (Micro Control Unit ) chips which are independently developed and designed by many enterprises can only perform digital simulation by using the netlist function of the FPGA (Field Programmable GATE ARRAY ), and there is no way to debug and simulate the simulation function of the chip, so that some companies can design a corresponding simulation chip additionally, but the cost of the mode is higher and the cost performance is lower.

Because the MCU chip of the autonomous research and development design has no corresponding simulator and can not be subjected to online debugging and simulation by engineers, the research and development progress of the scheme is retarded to a certain extent, so that the engineers can utilize the simulator to replace the MCU in the target system to simulate the operation of the MCU for convenience, and in the simulation process, the engineers can observe programs and data in the MCU through a desktop computer or other debugging interfaces and control the operation of the MCU.

However, the current simulators mainly have the following problems, namely, the first main simulators in the market mainly comprise ST-LINK, JTAG (Joint Test Action Group, joint test work organization), ULINK and the like, but are designed aiming at MCU chips of the types of STM32 and the like of ARM (Acorn RISC MACHINE) architecture, and the main simulators at present can not effectively perform online debugging and simulation on the MCU chips which are independently researched and designed; secondly, the MCU chip which is independently developed and designed can only utilize the FPGA or an additional design simulation chip to simulate and debug the MCU, but the simulation of the two modes has the problems of incomplete debugging function, higher cost and lower cost performance.

The above information disclosed in the background section is only for enhancement of understanding of the background art from the technology described herein and, therefore, may contain some information that does not form the prior art that is already known in the country to a person of ordinary skill in the art.

Disclosure of Invention

The application mainly aims to provide a simulation device to solve the problems of incomplete debugging function and high cost of a simulator in the prior art.

According to an aspect of the embodiment of the present invention, there is provided an emulation device, the emulation device including a communication layer and a bottom layer, where the communication layer includes a controller, the controller is configured to connect to a host computer, the controller is further configured to receive initial data sent by the host computer, and perform predetermined processing on the initial data by the controller to obtain predetermined data, the controller is further configured to send the predetermined data, the initial data is used to characterize specific content of emulation, and the predetermined processing includes at least decoding processing; the bottom layer is connected with the communication layer, the bottom layer comprises a plurality of preset chips, the simulation functions of the preset chips are different, the preset chips in the bottom layer receive the preset data sent by the communication layer, and the preset chips complete the simulation process of the preset chips according to the preset data.

Optionally, the predetermined chip includes a first chip, a second chip and a third chip, where the first chip is configured to perform a first simulation test according to the predetermined data, and a function of the first simulation test includes at least one of an SPI (SERIAL PERIPHERAL INTERFACE ) communication function, a USART (Universal Synchronous/Asynchronous Receiver/Transmitter) function and a BUZZER function; the second chip is used for performing a second simulation test according to the preset data, and the functions of the second simulation test comprise at least one of a comparator function, a PWM/PFD and a capture interrupt function; the third chip is used for performing a third simulation test according to the preset data, and the functions of the third simulation test comprise at least one of an operational amplifier function, an AD conversion function and a low-voltage detection function.

Optionally, the simulation device further includes a first bus, a second bus, and a third bus, where one end of the first bus is connected to the first chip, the other end of the first bus is connected to the communication layer, and the predetermined data in the communication layer passes through the first bus to the first chip; one end of the second bus is connected with the second chip, the other end of the second bus is connected with the communication layer, and the preset data in the communication layer passes through the second bus to the second chip; one end of the third bus is connected with the third chip, the other end of the third bus is connected with the communication layer, and the preset data in the communication layer passes through the third bus to the third chip.

Optionally, the bottom layer further includes a plurality of keys, a first communication interface, a display screen interface and a speaker device, where the keys are used for performing an interrupt operation in the process of simulating an interrupt function by the predetermined chip; the first communication interface comprises a plurality of first sub-communication interfaces, and the bottom layer is connected with the communication layer through the first communication interfaces; the display screen interface is used for externally connecting a display screen, so that a corresponding simulation process is displayed through the display screen; the loudspeaker device is used for sending out alarm information under the condition that the connection of the bottom layer is abnormal.

Optionally, the communication layer further includes a second communication interface and a third communication interface, where the second communication interface includes a plurality of second sub-communication interfaces, and the communication layer is connected to the first communication interface of the bottom layer through the second communication interface, so as to implement data transmission between the communication layer and the bottom layer; the communication layer is connected with the upper computer through the third communication interface, so that the initial data sent by the upper computer is received.

Optionally, the third communication interface includes a USB interface, and the plurality of second sub-communication interfaces includes at least one of an IIC (INTER INTEGRATED Circuit, integrated Circuit bus) interface and a GPIO (General Purpose Input/Output) interface.

Optionally, the communication layer further includes an indicator light and a reset button, where the indicator light is used to determine whether the power supply of the communication layer is abnormal; the reset key is used for resetting the communication layer.

Optionally, the communication layer further includes a program transmission interface, where the program transmission interface is used to download and/or upload a predetermined program of the controller, and the predetermined program is used to control the controller to perform simulation work.

Optionally, the controller is configured to transmit the predetermined data to the predetermined chip in the bottom layer for implementing the corresponding function according to the specific content of the predetermined data.

Optionally, the predetermined process further includes at least one of a process of resolving the effective information and a process of stitching.

In the embodiment of the application, the simulation device comprises a communication layer and a bottom layer, wherein the communication layer comprises a controller, the controller is used for being connected with an upper computer, the controller is also used for receiving initial data sent by the upper computer, the controller is used for carrying out preset processing on the initial data to obtain preset data, the controller is also used for sending the preset data, the initial data is used for representing specific content of simulation, and the preset processing at least comprises decoding processing; the bottom layer is connected with the communication layer, the bottom layer comprises a plurality of preset chips, the simulation functions of the preset chips are different, the preset chips in the bottom layer receive the preset data sent by the communication layer, and the preset chips complete the simulation process of the preset chips according to the preset data. Compared with the problems of incomplete debugging functions and higher cost of simulators in the prior art, the simulation device provided by the application has the advantages that the communication layer and the bottom layer are designed, wherein the communication layer comprises the controller, the controller is used for receiving initial data sent by the upper computer, at least carrying out decoding processing on the initial data, and sending the processed preset data to the preset chips in the bottom layer so as to realize simulation processes of different functions of the preset chips, and the simulation functions of the simulation device are ensured to be comprehensive due to the fact that the preset chips are all different, and the simulation process of the chips can be completed without redesigning the corresponding simulation chips due to the fact that the preset chips are independently developed chips.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

FIG. 1 shows a schematic diagram of a simulation apparatus according to an embodiment of the present application;

FIG. 2 illustrates a schematic diagram of an underlayer in an emulation device in accordance with an embodiment of the present application;

FIG. 3 is a schematic diagram of a communication layer in an emulation device according to an embodiment of the present application;

fig. 4 shows a schematic diagram of a host computer according to an embodiment of the application.

Wherein the above figures include the following reference numerals:

10. A communication layer; 20. a bottom layer; 30. an upper computer; 101. a controller; 102. a second communication interface; 103. a third communication interface; 104. an indicator light; 105. resetting a key; 106. program transmission interface; 107. a standby interface; 201. a predetermined chip; 202. a first chip; 203. a second chip; 204. a third chip; 205. a first bus; 206. a second bus; 207. a third bus; 208. a key; 209. a first communication interface; 210. a display screen interface; 211. a horn device; 212. a first PT interface; 213. a second PT interface; 214. a third PT interface; 301. a toolbar; 302. an engineering file area; 303. an engineering code area; 304. a result output area; 305. special register areas.

Detailed Description

It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.

In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the application herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, in the description and in the claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

As described in the background, the problem of incomplete debugging function and high cost of the prior art simulator is that in an exemplary embodiment of the present application, a simulation device is provided.

According to an embodiment of the present application, as shown in fig. 1 to 3, there is provided an emulation device, where the emulation device includes a communication layer 10 and a bottom layer 20, where the communication layer 10 includes a controller 101, where the controller 101 is configured to connect to an upper computer 30, where the controller 101 is further configured to receive initial data sent by the upper computer 30, where the controller 101 performs a predetermined process on the initial data to obtain predetermined data, where the controller 101 is further configured to send the predetermined data, where the initial data is used to characterize specific content of the emulation, and where the predetermined process at least includes a decoding process; the bottom layer 20 is connected to the communication layer 10, the bottom layer 20 includes a plurality of predetermined chips 201, the predetermined chips 201 in the bottom layer 20 receive the predetermined data transmitted from the communication layer 10, and the predetermined chips 201 perform the simulation process of the predetermined chips 201 according to the predetermined data.

The simulation device comprises a communication layer and a bottom layer, wherein the communication layer comprises a controller, the controller is used for being connected with an upper computer, the controller is also used for receiving initial data sent by the upper computer, the controller is used for carrying out preset processing on the initial data to obtain preset data, the controller is also used for sending the preset data, the initial data is used for representing specific content of simulation, and the preset processing at least comprises decoding processing; the bottom layer is connected with the communication layer, the bottom layer comprises a plurality of preset chips, the simulation functions of the preset chips are different, the preset chips in the bottom layer receive the preset data sent by the communication layer, and the preset chips complete the simulation process of the preset chips according to the preset data. Compared with the problems of incomplete debugging function and higher cost of the simulator in the prior art, the simulation device of the application ensures that the simulation function of the simulation device is complete due to the fact that the simulation functions of a plurality of preset chips are different, and the simulation process of the chip can be completed without redesigning the corresponding simulation chip because the preset chips are chips which are independently researched and developed, so that the problems of incomplete debugging function and higher cost of the simulator in the prior art are solved.

Specifically, as shown in fig. 4, fig. 4 is a block diagram of the upper computer 30, and as shown in fig. 4, the upper computer 30 includes a toolbar 301, an engineering file area 302, an engineering code area 303, a result output area 304, and a special register area 305. And carrying out online debugging and simulation on the preset chip through each functional area of the upper computer.

In a specific embodiment, the controller includes an MCU using an STM32F103 chip, although other chips are possible. In addition, the communication layer is a PC end connected with the upper computer.

In order to further ensure that the simulation function of the simulation device is more comprehensive, according to an embodiment of the present application, as shown in fig. 2, the predetermined chip 201 includes a first chip 202, a second chip 203, and a third chip 204, where the first chip 202 is configured to perform a first simulation test according to the predetermined data, and the function of the first simulation test includes at least one of an SPI communication function, a USART function, and a buzer function; the second chip 203 is configured to perform a second simulation test according to the predetermined data, where a function of the second simulation test includes at least one of a comparator function, a PWM/PFD, and a capture interrupt function; the third chip 204 is configured to perform a third simulation test according to the predetermined data, where the third simulation test includes at least one of an op amp function, an AD conversion function, and a low voltage detection function. Because the predetermined chip comprises the first chip, the second chip and the third chip, the first chip executes the first simulation test, the second chip executes the second simulation test, the third chip executes the third simulation test, and the first simulation test, the second simulation test and the third simulation test execute simulation tests with different functions respectively, the test function which can be realized by the predetermined chip is more comprehensive, and the simulation function of the simulation device is further ensured to be more comprehensive.

Of course, the predetermined chips are not limited to the first chip, the second chip, and the third chip, and the functions performed by the respective predetermined chips are not limited to the plurality of predetermined chips, but the predetermined chips of other functions may be provided according to actual situations, and the predetermined chips may be one, two, three, or more, and are specifically determined according to actual situations.

According to another embodiment of the present application, as shown in fig. 1, the simulation apparatus further includes a first bus 205, a second bus 206, and a third bus 207, wherein one end of the first bus 205 is connected to the first chip 202, the other end of the first bus 205 is connected to the communication layer 10, and the predetermined data in the communication layer 10 passes through the first bus 205 to the first chip 202; one end of the second bus 206 is connected to the second chip 203, the other end of the second bus 206 is connected to the communication layer 10, and the predetermined data in the communication layer 10 is transferred to the second chip 203 through the second bus 206; one end of the third bus 207 is connected to the third chip 204, the other end of the third bus 207 is connected to the communication layer 10, and the predetermined data in the communication layer 10 is transferred to the third chip 204 through the third bus 207. By arranging the first bus, the second bus and the third bus, the first chip can receive the preset data sent by the communication layer through the first bus, the second chip can receive the preset data sent by the communication layer through the second bus, the third chip can receive the preset data sent by the communication layer through the third bus, the first chip, the second chip and the third chip are all connected with the communication layer through separate buses, specific preset chips can be selected according to specific functions of the preset data, meanwhile, the preset chips with other functions can not receive the preset data, simulation test of the preset chips can be realized, and the simulation function of the simulation device is further guaranteed to be comprehensive.

In a specific embodiment, the first bus, the second bus, and the third bus include IIC lines.

According to another embodiment of the present application, as shown in fig. 2, the bottom layer 20 further includes a plurality of keys 208, a first communication interface 209, a display screen interface 210, and a speaker device 211, where the keys 208 are used for performing an interrupt operation during the interrupt function simulation of the predetermined chip 201; the first communication interface 209 includes a plurality of first sub-communication interfaces, and the bottom layer 20 is connected to the communication layer 10 through the first communication interface 209; the display screen interface 210 is used for externally connecting a display screen, so that the corresponding simulation process is displayed through the display screen; the speaker device 211 is used for sending out alarm information when the connection of the bottom layer 20 is abnormal. Through setting up above-mentioned button, above-mentioned communication interface, above-mentioned display screen interface and above-mentioned loudspeaker device for above-mentioned bottom can be through above-mentioned first communication interface connection above-mentioned communication layer, guaranteed that above-mentioned bottom can receive above-mentioned predetermined data, and then realize the simulation process of above-mentioned predetermined chip through above-mentioned predetermined data, further guaranteed that above-mentioned simulation device's simulation function is comparatively comprehensive.

In addition, the loudspeaker device also corresponds to the BUZZER function of the first chip, of course, the loudspeaker device can also realize other functions through setting up, in the above-mentioned embodiment, through setting up the loudspeaker device, make under the abnormal condition of above-mentioned bottom work, can send the above-mentioned alarm information, the security of having guaranteed the above-mentioned simulation device is higher, through setting up the above-mentioned display screen interface, make can more intuitively obtain the above-mentioned simulated data or other simulation processes through external display screen, specifically, the above-mentioned display screen mainly corresponds to the simulation function of the above-mentioned third chip, of course, the above-mentioned display screen is not limited to the above-mentioned function, can also realize other functions through setting up, the use experience of having guaranteed the above-mentioned simulation device is felt better.

Specifically, the first communication interface may include a power strip mode, and may be directly connected to the communication layer.

In a specific embodiment, the keys are not limited to the above functions, and the functions of the keys can be set according to actual requirements in an actual application process, and the number of the keys is not limited to five and can be determined according to actual conditions.

In addition, the construction mode of the bottom layer is universal and simple, and the simulation device of the MCU chip can be manufactured along with other chips which are independently researched and developed, namely, when a new MCU chip is designed, namely, a new preset chip is designed, and the simulation device of the MCU chip can be manufactured according to the same design concept.

In order to further ensure that the simulation function of the simulation device is more comprehensive, according to an embodiment of the present application, as shown in fig. 3, the communication layer 10 further includes a second communication interface 102 and a third communication interface 103, where the second communication interface 102 includes a plurality of second sub-communication interfaces, and the communication layer 10 is connected to the first communication interface 209 of the bottom layer 20 through the second communication interface 102, so as to implement data transmission between the communication layer 10 and the bottom layer 20; the communication layer 10 is connected to the host computer 30 through the third communication interface 103, so as to receive the initial data sent by the host computer 30. Through setting up above-mentioned second communication interface and above-mentioned third communication interface for above-mentioned communication layer can be through above-mentioned third communication interface connection host computer, has guaranteed that above-mentioned communication layer can receive above-mentioned initial data, in addition, above-mentioned communication layer can be through above-mentioned first communication interface of above-mentioned bottom of above-mentioned second communication interface connection, has guaranteed that above-mentioned bottom can receive above-mentioned predetermined data, and then has guaranteed that above-mentioned predetermined chip in the above-mentioned bottom can receive above-mentioned predetermined data, has further guaranteed that above-mentioned simulation device's simulation function is comparatively comprehensive and the cost is lower.

In addition, the second communication interface also comprises a power strip mode, so that the first communication interface can be connected more simply.

According to another embodiment of the present application, the third communication interface includes a USB interface, and the plurality of second sub-communication interfaces includes at least one of an IIC interface and a GPIO interface.

In a specific embodiment, the third communication interface USB interface is not limited to being connected to the communication layer and the host computer, and also provides 3.3V for the communication layer.

Specifically, the second communication interface and the first communication interface both adopt IIC communication and some common GPIO ports, and at the same time, on the bottom design, the IIC ports and some common GPIO ports are combined into one interface, i.e. a plug-and-play mode, so that the plug-and-play mode is convenient, and when the simulation device is used, the first communication interface and the second communication interface are directly in butt joint.

According to another embodiment of the present application, as shown in fig. 3, the communication layer 10 further includes an indicator light 104 and a reset button 105, wherein the indicator light 104 is used for determining whether the power supply of the communication layer 10 is abnormal; the reset key 105 is used for performing a reset process on the communication layer 10. Through setting up above-mentioned pilot lamp and above-mentioned button that resets, guaranteed under the power supply abnormal condition of above-mentioned communication layer, can audio-visual obtain abnormal information, further guaranteed that above-mentioned simulator's security is higher.

In addition, the reset key is used for resetting the communication layer through the reset key under the condition that the communication layer is abnormal, so that the abnormal communication layer can be simply processed.

According to an embodiment of the present application, as shown in fig. 3, the communication layer 10 further includes a program transmission interface 106, where the program transmission interface 106 is configured to perform downloading and/or uploading of a predetermined program of the controller 101, and the predetermined program is configured to control the controller 101 to perform a simulation operation. By setting the program transmission interface, the program of the communication layer can be downloaded and uploaded through the program transmission interface, so that the communication layer can normally complete simulation work.

In one embodiment, as shown in fig. 3, the communication layer 10 further includes a standby interface 107. The standby interface may be a GPIO debug interface, or of course, may be any other interface required, which is specifically determined according to the actual situation.

According to another embodiment of the present application, the controller is configured to transmit the predetermined data to the predetermined chip in the bottom layer for implementing a corresponding function according to a specific content of the predetermined data.

Specifically, the first chip, the second chip, and the third chip are all the same independently developed chips, and when the predetermined data needs to simulate specific functions, the first chip, the second chip, and the third chip are provided with different interfaces, as shown in fig. 2, including the first PT interface 212, the second PT interface 213, and the third PT interface 214. So that the simulation of different functions can be realized through different interfaces. In a specific embodiment, the first chip simulates the SPI communication function, the USART function, the BUZZER function, and the E0IF and E1IF interrupt functions of the MCU chip, so that a part of the normal GPIO ports of the first chip, that is, the first PT interface, is used as the IIC communication, the E0IF interrupt signal notification port, and the SPI communication interrupt signal notification port, the communication layer determines whether to enter an interrupt by reading the high and low levels of the corresponding pins, what type of interrupt the communication layer enters, the second chip simulates the comparator function, the PWM/PFD, the capture interrupt function, and so on of the MCU chip, and a part of the normal GPIO ports of the second chip, that is, the second PT interface, is used as the interrupt signal notification port for capturing an interrupt for IIC communication, and the interrupt principle is the same as that of the first chip, and details of the interrupt principle are not repeated herein, which are the third chip.

In a specific embodiment, the predetermined chip of the autonomous development design generally has several general GPIO ports, GPIO ports of an LCD (Liquid CRYSTAL DISPLAY ) and some GPIO ports with special functions, so that three autonomous development design MCU chips are adopted in the bottom layer design, that is, the first chip, the second chip and the third chip simulate the general GPIO port functions, the GPIO port functions of the LCD and the special GPIO port functions respectively, and GPIO debug ports, that is, the first PT interface corresponds to three autonomous development design MCU chips, that is, the first chip only draws corresponding GPIO ports, other GPIO ports are used for data communication in the communication layer or not used and not drawn, the second chip only draws corresponding GPIO ports, other GPIO ports are used for data communication in the communication layer or not used and not drawn, and the third chip only draws GPIO ports corresponding to three autonomous development design MCU chips, that is the first chip only draws corresponding GPIO ports, and other GPIO ports are used for data communication in the communication layer or not used for the communication layer.

According to still another embodiment of the present application, the above-mentioned predetermined processing further includes at least one of a process of resolving the effective information and a process of splicing.

Specifically, the simulation device can solve the problem that in the prior art, simulation cannot be carried out on a chip which is simulated by using an ST-LINK simulator and the like, and ensures that the efficiency of product design research and development by engineers is higher.

In the following, a specific simulation procedure of the above simulation apparatus will be described.

Firstly, the first communication interface of the bottom layer is connected with the second communication interface of the communication layer, and the third communication interface of the communication layer, namely a USB interface, is connected with the upper computer (PC end) by USB, and at the moment, whether the power supply of the equipment is normal can be judged by the indicator lamp of the communication layer;

Then, the program to be debugged and simulated is opened on the upper computer (PC end) and enters a debugging and simulation mode, an engineer can select to break or not break, select a single-step execution program or a full-speed execution program and the like, the communication layer receives the initial data sent by the upper computer (PC end), the decoding process is carried out according to a protocol, the effective information is intercepted, and then the relevant data is spliced again to obtain the preset data, the preset data is sent to the bottom layer through the second communication interface, in addition, in the decoding process, the value of which register the data is to be modified is judged, That is, which emulation function of the bottom layer is to be implemented, for example, an SPI communication function, data of a USB interface sent to the communication layer by the host computer (PC side) through the USB is decoded by the STM32F103 chip, that is, the controller, the decoded predetermined data includes an SPI register address, a value to be modified in the SPI register address, and an emulation function of which predetermined chip is determined from the first chip, the second chip, and the third chip, the STM32F103 chip, that is, the controller can determine that the SPI communication function is the emulation function of the first chip after decoding, The STM32F103 chip issues the relevant information such as the register address value and the value to be modified through the first bus, and because the first chip, the second chip and the third chip which are independently designed and configured by the bottom layer perform IIC communication through the first bus, the second bus, the third bus and the communication layer, respectively, the second chip and the third chip, that is, MCU chips which are not related to the SPI communication simulation, do not receive the predetermined data, the first chip decodes after receiving the predetermined data, and modifies the value of the corresponding register, the logic analyzer and other similar data analysis instruments can be connected to the first PT interface corresponding to the first chip, It can accurately judge whether the preset data accords with the logic described in the program, so as to judge whether the values in the related SPI registers are correct, meanwhile, the first chip can enter related interruption of SPI and pull up GPIO related to SPI interruption in the first communication interface, at this time, the controller of the communication layer can read the corresponding GPIO level through the second communication interface and pull up, the communication layer sends the information to the upper computer (PC end) through the USB interface, the upper computer (PC end) can pause the following data transmission after receiving the information, After waiting for the subsequent data, the first chip sends the modified register address and value to the communication layer through IIC1, the communication layer decodes the data to form data conforming to the USB communication protocol, and then sends the data to the upper computer (PC end), the upper computer (PC end) receives the data and starts to send other related data continuously, and an engineer can judge that the SPI in the first chip has the modified content of Guan Jicun devices through the content displayed in the special register area.

Finally, engineers continuously debug and simulate the problems in the program on line until the problems meet the requirements, and burn the program into a product researched and developed by the MCU chip, so that the research and development efficiency can be improved.

In the foregoing embodiments of the present invention, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.

From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

The simulation device comprises a communication layer and a bottom layer, wherein the communication layer comprises a controller, the controller is used for being connected with an upper computer, the controller is also used for receiving initial data sent by the upper computer, the controller is used for carrying out preset processing on the initial data to obtain preset data, the controller is also used for sending the preset data, the initial data is used for representing specific content of simulation, and the preset processing at least comprises decoding processing; the bottom layer is connected with the communication layer, the bottom layer comprises a plurality of preset chips, the simulation functions of the preset chips are different, the preset chips in the bottom layer receive the preset data sent by the communication layer, and the preset chips complete the simulation process of the preset chips according to the preset data. Compared with the problems of incomplete debugging function and higher cost of the simulator in the prior art, the simulation device of the application ensures that the simulation function of the simulation device is complete due to the fact that the simulation functions of a plurality of preset chips are different, and the simulation process of the chip can be completed without redesigning the corresponding simulation chip because the preset chips are chips which are independently researched and developed, so that the problems of incomplete debugging function and higher cost of the simulator in the prior art are solved.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. A simulation apparatus, characterized in that the simulation apparatus comprises:

The communication layer comprises a controller, wherein the controller is used for being connected with an upper computer, the controller is also used for receiving initial data sent by the upper computer, the controller is used for carrying out preset processing on the initial data to obtain preset data, the controller is also used for sending the preset data, the initial data is used for representing specific content of simulation, and the preset processing at least comprises decoding processing;

the base layer is connected with the communication layer, the base layer comprises a plurality of preset chips, the simulation functions of the preset chips are different, the preset chips in the base layer receive the preset data sent by the communication layer, and the preset chips complete the simulation process of the preset chips according to the preset data.

2. The emulation device of claim 1, wherein the predetermined chip comprises:

The first chip is used for performing a first simulation test according to the preset data, and the functions of the first simulation test comprise at least one of SPI communication function, USART function and BUZZER function;

The second chip is used for performing a second simulation test according to the preset data, and the functions of the second simulation test comprise at least one of a comparator function, a PWM/PFD and a capture interrupt function;

and the third chip is used for performing a third simulation test according to the preset data, and the functions of the third simulation test comprise at least one of an operational amplifier function, an AD conversion function and a low-voltage detection function.

3. The simulation device of claim 2, wherein the simulation device further comprises:

The first bus, one end of the first bus is connected with the first chip, the other end of the first bus is connected with the communication layer, the predetermined data in the communication layer passes through the first bus to the first chip;

One end of the second bus is connected with the second chip, the other end of the second bus is connected with the communication layer, and the preset data in the communication layer passes through the second bus to the second chip;

and one end of the third bus is connected with the third chip, the other end of the third bus is connected with the communication layer, and the preset data in the communication layer passes through the third bus to the third chip.

4. The emulation device of claim 1, wherein the bottom layer further comprises:

The keys are used for performing interrupt operation in the process of simulating interrupt functions of the preset chip;

the first communication interface comprises a plurality of first sub-communication interfaces, and the bottom layer is connected with the communication layer through the first communication interfaces;

the display screen interface is used for externally connecting a display screen, so that a corresponding simulation process is displayed through the display screen;

and the loudspeaker device is used for sending out alarm information under the condition that the connection of the bottom layer is abnormal.

5. The emulation device of claim 4, wherein the communication layer further comprises:

the second communication interface comprises a plurality of second sub communication interfaces, and the communication layer is connected with the first communication interface of the bottom layer through the second communication interfaces so as to realize data transmission between the communication layer and the bottom layer;

and the communication layer is connected with the upper computer through the third communication interface, so that the initial data sent by the upper computer is received.

6. The emulation device of claim 5, wherein the third communication interface comprises a USB interface and the plurality of second sub-communication interfaces comprises at least one of an IIC interface and a GPIO interface.

7. The emulation device of claim 1, wherein the communication layer further comprises:

the indicator lamp is used for judging whether the power supply of the communication layer is abnormal or not;

And the reset key is used for resetting the communication layer.

8. The emulation device of claim 1, wherein the communication layer further comprises:

And the program transmission interface is used for downloading and/or uploading a preset program of the controller, and the preset program is used for controlling the controller to perform simulation work.

9. The emulation device according to any one of claims 1 to 8, wherein the controller is configured to transmit the predetermined data to the predetermined chip in the base layer which realizes the corresponding function, according to a specific content of the predetermined data.

10. The simulation apparatus according to any one of claims 1 to 8, wherein the predetermined processing further includes at least one of a deblocking effective information processing and a stitching processing.