CN118249747A - High harmonic rejection ratio broadband injection locking double-frequency multiplier - Google Patents
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- H—ELECTRICITY
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- H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
- H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
- H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
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- H—ELECTRICITY
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Abstract
The application discloses a high harmonic rejection ratio broadband injection locking double-frequency multiplier, which adopts a multi-harmonic extraction transformer to amplify the signals of injectors for the second time and the third time, wherein the multi-harmonic extraction transformer comprises two groups of output inductance groups and one group of input inductance groups, the two groups of output inductance groups are coupled with the input inductance groups, the input ends of the input inductance groups are connected with the output ends of the two groups of injectors, the output ends of the two groups of injectors are respectively connected with one output end of a load pair.
Description
Technical Field
The invention relates to the technical field of radio frequency, in particular to a high-harmonic rejection ratio broadband injection locking double-frequency multiplier.
Background
Injection locked frequency multipliers are devices commonly used in electronic communication systems to lock the frequency of an input signal to a particular multiplied output, thus amplifying the frequency of the input signal to a higher multiplied output and effectively blocking interfering signals from other frequencies. Injection locked multipliers play an important role in phase locked loops and are also critical circuits in wireless communication systems. The conventional injection locking frequency multiplier is limited in practical application because of its harmonic rejection ratio difference, narrow bandwidth and invariable frequency multiplication ratio.
The existing method for improving the harmonic suppression ratio mainly suppresses harmonic signals with specific frequency by adding an isolator or a wave trap, but the method can increase the cost of power consumption, area and the like; the existing bandwidth improving method mainly increases the size of an injector transistor, but the increase of the transistor size can cause the parasitic capacitance to be overlarge so as to reduce the working frequency; the existing method for realizing the frequency multiplication ratio mainly introduces a harmonic mixer, but introduces nonlinear distortion and reduces the stability of the system.
As in the prior art, patent application number 201911029869.8 discloses a wideband injection locking frequency multiplier that employs multiple harmonic generators to generate second/third injection harmonics to achieve multiple frequency ratio multiplication, which increases the complexity of the structure and increases the power consumption of the system.
Disclosure of Invention
The invention aims to provide a high harmonic rejection ratio broadband injection locking double-frequency multiplier so as to solve the problems of complex structure and high system power consumption of the existing frequency multiplier.
The high-harmonic rejection ratio broadband injection locking double-frequency converter comprises an injector, a load pair and a multi-harmonic extraction transformer, wherein the multi-harmonic extraction transformer comprises two groups of output inductance groups and one group of input inductance groups, the two groups of output inductance groups are coupled with the input inductance groups, the output ends of the two groups of injectors are connected with the input ends of the input inductance groups, and the output ends of the two groups of injectors are respectively connected with one output end of the load pair;
The output inductor group comprises a first inductor L1 and a second inductor L2, one end of the first inductor L1 is connected with one end of the second inductor L2, the other end of the first inductor L1 and the other end of the second inductor L2 are connected with two capacitors in series, and the connecting ends of the two capacitors are grounded; the other end of the first inductor L1 and the other end of the second inductor L2 are the output ends of one group of output inductor groups;
The input inductance group comprises a third inductance L3 and a fourth inductance L4, one end of the third inductance L3 is connected with one end of the fourth inductance L4, the other end of the third inductance L3 is connected with the output end of one injector, and the other end of the fourth inductance L4 is connected with the output end of the other injector;
The other output inductance group comprises a fifth inductance L5 and a sixth inductance L6, one end of the fifth inductance L5 is connected with one end of the sixth inductance L6, and the other end of the fifth inductance L5 and the other end of the sixth inductance L6 are output ends of the other output inductance group; the connection between the fifth inductor L5 and the sixth inductor L6 is a bias voltage Vb3 connection point.
Preferably, the injector comprises an MOS tube, a capacitor and a resistor, wherein a grid electrode of the MOS tube is connected with one end of the capacitor and one end of the resistor, a source electrode of the MOS tube is grounded, a drain electrode of the MOS tube is connected with an input end of the input inductance group, and the other end of the capacitor is connected with an input signal; the other end of the resistor is a bias voltage connection point.
Preferably, the load pair includes a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6, where a drain of the third MOS transistor M3 is connected to a gate of the fourth MOS transistor M4, and a junction between the drain of the third MOS transistor M3 and the gate of the fourth MOS transistor M4 is used as an output end of the load pair;
The drain electrode of the fourth MOS tube M4 is connected with the grid electrode of the third MOS tube M3, and the joint of the drain electrode of the fourth MOS tube M4 and the grid electrode of the third MOS tube M3 is used as the other output end of the load pair;
the source electrode of the fifth MOS tube M5 is grounded, and the drain electrode of the fifth MOS tube M5 is respectively connected with the source electrode of the third MOS tube M3 and the source electrode of the fourth MOS tube M4;
The drain electrode of the sixth MOS tube M6 is connected with the grid electrode of the sixth MOS tube M6 and the grid electrode of the fifth MOS tube M5 respectively, the drain electrode of the sixth MOS tube M6 is connected with the power supply VDD, and the source electrode of the sixth MOS tube M6 is grounded.
Preferably, the first inductor L1 is coupled with the third inductor L3, and the coupling coefficient of the first inductor L1 and the third inductor L3 is k1; the second inductor L2 is coupled with the fourth inductor L4, and the coupling coefficient of the second inductor L2 and the fourth inductor L4 is k1.
Preferably, k1 takes a value of 0.3-0.5 for even harmonics in the injector injection current; for the odd harmonics in the injector injection current, k1 takes a value of 0.001.
Preferably, the third inductor L3 is coupled to the fifth inductor L5, and the coupling coefficient between the third inductor L3 and the fifth inductor L5 is k2; the fourth inductor L4 is coupled with the sixth inductor L6, and the coupling coefficient of the fourth inductor L4 and the sixth inductor L6 is k2.
Preferably, k2 takes a value of 0.001 for even harmonics in the injector injection current; for the odd harmonics in the injector injection current, k2 takes a value of 0.2-0.4.
Preferably, the first inductor L1 is coupled with the fifth inductor L5, and the coupling coefficient of the first inductor L1 and the fifth inductor L5 is k3; the second inductor L2 is coupled with the sixth inductor L6, and the coupling coefficient of the second inductor L2 and the sixth inductor L6 is k3.
Preferably, k3 has a value of 0.4 to 0.6.
Compared with the prior art, the invention has the following beneficial technical effects:
The application provides a high harmonic suppression ratio broadband injection locking double-frequency multiplier, which adopts a multi-harmonic extraction transformer to amplify signals injected by two groups of injectors for two times and three times, wherein the multi-harmonic extraction transformer comprises two groups of output inductance groups and one group of input inductance groups, the two groups of output inductance groups are coupled with the input inductance groups, the input ends of the input inductance groups are connected with the output ends of the two groups of injectors, and the output ends of the two groups of injectors are respectively connected with one output end of a load pair.
Preferably, the coupling of the load to the intermediate inductor increases the resonator impedance, thereby increasing the harmonic rejection ratio, and the proposed structure has a greater bandwidth and a higher harmonic rejection ratio than the conventional frequency multiplier structure.
Drawings
FIG. 1 is a schematic diagram of a high harmonic rejection ratio wideband injection locked dual tripler circuit in accordance with an embodiment of the present invention.
Fig. 2 is a schematic diagram of the inside of a resonant cavity when even harmonics of an injector injection current enter the resonant cavity in an embodiment of the present invention.
Fig. 3 is a schematic diagram of the interior of a resonant cavity when an odd harmonic of an injector injection current enters the resonant cavity in an embodiment of the present invention.
FIG. 4 is a simulation diagram of the operating frequency range in an embodiment of the present invention.
FIG. 5 is a simulation diagram of the harmonic rejection ratio in an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "one of the sets," "another of the sets," and the like in the description and the claims of the present invention and in the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.
As shown in fig. 1, the application provides a high-harmonic rejection ratio broadband injection locking double-frequency converter, which comprises an injector, a load pair and a multi-harmonic extraction transformer, wherein the multi-harmonic extraction transformer comprises two output inductance groups and one input inductance group, the two output inductance groups are coupled with the input inductance groups, the output ends of the two injectors are connected with the input ends of the input inductance groups, and the output ends of the two injectors are respectively connected with one output end of the load pair; the application amplifies the second harmonic and the third harmonic of the signals injected by the two groups of injectors through the multi-harmonic extraction transformer formed by the two groups of output inductance groups and the one group of input inductance groups, can realize frequency doubling and frequency tripling, and the bandwidths of the frequency doubling and the frequency tripling are overlapped with each other, so that the bandwidth is equivalently expanded.
In a specific embodiment of the present application, as shown in fig. 1, one output inductor group includes a first inductor L1 and a second inductor L2, one end of the first inductor L1 is connected with one end of the second inductor L2, two capacitors connected in series are connected between the other end of the first inductor L1 and the other end of the second inductor L2, and the connection ends of the two capacitors are grounded; the other end of the first inductor L1 and the other end of the second inductor L2 are output ends of one output inductor group.
The input inductance group comprises a third inductance L3 and a fourth inductance L4, one end of the third inductance L3 is connected with one end of the fourth inductance L4, the other end of the third inductance L3 is connected with the output end of one injector, and the other end of the fourth inductance L4 is connected with the output end of the other injector. The first inductor L1 is coupled with the third inductor L3, and the second inductor L2 is coupled with the fourth inductor L4; the third inductor L3 and the fourth inductor L4 are connected to the power supply VDD.
The other output inductance group comprises a fifth inductance L5 and a sixth inductance L6, one end of the fifth inductance L5 is connected with one end of the sixth inductance L6, and the other end of the fifth inductance L5 and the other end of the sixth inductance L6 are output ends of the other output inductance group; wherein, the fifth inductance L5 is coupled with the third inductance L3, and the sixth inductance L6 is coupled with the fourth inductance L4; the connection between the fifth inductor L5 and the sixth inductor L6 is a bias voltage Vb3 connection point.
In a specific embodiment of the present application, the injector includes a MOS transistor M, a capacitor C and a resistor R, where a gate of the MOS transistor M is connected to one end of the capacitor C and one end of the resistor R, a source of the MOS transistor M is grounded, a drain of the MOS transistor M is connected to an input end of the input inductance group, that is, the drain of the MOS transistor M is connected to the other end of the third inductance L3, and the other end of the capacitor is connected to an input signal; the other end of the resistor is a bias voltage connection point.
In a specific embodiment of the present application, as shown in fig. 1, one injector includes a first MOS transistor M1, a first capacitor C1, and a first resistor R1;
The grid electrode of the first MOS tube M1 is respectively connected with one end of the first capacitor C1 and one end of the first resistor R1, the source electrode of the first MOS tube M1 is grounded, and the drain electrode of the first MOS tube M1 is respectively connected with the drain electrode of the third MOS tube M3 and the other end of the third inductor L3; the other end of the first capacitor C1 is an input signal Vinj+ connection point; the other end of the first resistor R1 is a bias voltage Vb1 connection point.
As shown in fig. 1, the other injector includes a second MOS transistor M2, a second capacitor C2, and a second resistor R2, where a gate of the second MOS transistor M2 is connected to one end of the second capacitor C2 and one end of the second resistor R2, a source of the second MOS transistor M2 is grounded, and a drain of the second MOS transistor M2 is connected to a drain of the fourth MOS transistor M4 and the other end of the fourth inductor L4, respectively; the other end of the second capacitor C2 is an input signal Vinj-connection point; the other end of the second resistor R2 is a bias voltage Vb2 connection point.
As shown in fig. 1, the load pair includes a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6, where a drain of the third MOS transistor M3 is connected to a gate of the fourth MOS transistor M4, and a junction between the drain of the third MOS transistor M3 and the gate of the fourth MOS transistor M4 is used as an output end of the load pair;
The drain electrode of the fourth MOS tube M4 is connected with the grid electrode of the third MOS tube M3, and the joint of the drain electrode of the fourth MOS tube M4 and the grid electrode of the third MOS tube M3 is used as the other output end of the load pair;
the source electrode of the fifth MOS tube M5 is grounded, and the drain electrode of the fifth MOS tube M5 is respectively connected with the source electrode of the third MOS tube M3 and the source electrode of the fourth MOS tube M4;
The drain electrode of the sixth MOS tube M6 is connected with the grid electrode of the sixth MOS tube M6 and the grid electrode of the fifth MOS tube M5 respectively, the drain electrode of the sixth MOS tube M6 is connected with the power supply VDD, and the source electrode of the sixth MOS tube M6 is grounded.
When the Gao Xiebo suppression ratio broadband injection locking double frequency multiplier is used, a differential signal Vinj+ and a differential signal Vinj+ are respectively output from two injectors, the differential signal Vinj+ is injected from the grid electrode of the first MOS tube M1 of one injector, the differential signal Vinj-is injected from the grid electrode of the second MOS tube M2 of the other injector, and drain currents of the first MOS tube M1 and the second MOS tube M2 are expressed as follows by adopting a Fourier series formula:
In the above-mentioned method, the step of, For/>Drain currents of the first MOS transistor M1 and the second MOS transistor M2 at moment; /(I)Is the frequency of the injected signal; /(I)Fourier coefficient of each order harmonic of drain current,/>Represents the/>Order harmonics.
The second harmonic obtained after the transformer is extracted by the multiple harmonics is as follows:
the third harmonic obtained after the transformer is extracted by the multiple harmonics is as follows:
When (when) When not less than 1, fourier coefficient of each order harmonic of drain current/>Expressed as:
Wherein, For the period of the injected signal,/>For the conduction time of the first MOS tube M1 and the second MOS tube M2 in one period of the injection signal,/>The maximum peak-to-peak current output from the drain of the transistor.
The coupling coefficient of the first inductor L1 and the third inductor L3 is k1;
the coupling coefficient of the second inductor L2 and the fourth inductor L4 is k1;
the coupling coefficient of the third inductor L3 and the fifth inductor L5 is k2;
The coupling coefficient of the fourth inductor L4 and the sixth inductor L6 is k2;
the coupling coefficient of the first inductor L1 and the fifth inductor L5 is k3;
the coupling coefficient of the second inductor L2 and the sixth inductor L6 is k3;
in the above, for even harmonic in the injection current of the injector, the value of k1 is 0.3-0.5, the value of k2 is 0.001, and the value of k3 is 0.4-0.6; for the odd harmonics in the injector injection current, k1 takes on a value of 0.001, k2 takes on a value of 0.2-0.4, and k3 takes on a value of 0.4-0.6.
In one embodiment of the present invention, as shown in fig. 2, for even harmonics in the injector injection current, induced currents of opposite polarity are generated on the fifth inductor L5 and the sixth inductor L6, which cancel each other out; even harmonic waves in the injection current of the injector generate induction currents with the same polarity on the first inductor L1 and the second inductor L2, and the induction currents are mutually enhanced; at this time, the coupling coefficient K1 between the third inductance L3 and the first inductance L1 is large, and the coupling coefficient K1 between the fourth inductance L4 and the second inductance L2 is large; the coupling coefficient k2 between the third inductance L3 and the fifth inductance L5 is close to 0, and the coupling coefficient k2 between the fourth inductance L4 and the sixth inductance L6 is close to 0.
In another embodiment of the present invention, as shown in fig. 3, for the odd harmonics in the injector injection current, induced currents of the same polarity are generated on the fifth inductor L5 and the sixth inductor L6, and mutually enhance; induced currents with opposite polarities are generated on the first inductor L1 and the second inductor L2, and cancel each other. At this time, the coupling coefficient k1 between the third inductance L3 and the first inductance L1 approaches 0, and the coupling coefficient k1 between the fourth inductance L4 and the second inductance L2 approaches 0; the coupling coefficient k2 between the third inductance L3 and the fifth inductance L5 is large, and the coupling coefficient k2 between the fourth inductance L4 and the sixth inductance L6 is large.
Specifically, the MOS transistors adopted by the application are all N-type MOS transistors, so that the output voltage swing is increased, and the application has the characteristics of low voltage and low power consumption. In the load pair, the drain electrode of the fifth MOS tube M5 is respectively connected with the source electrode of the third MOS tube M3 and the source electrode of the fourth MOS tube M4, and the third MOS tube M3 and the fourth MOS tube M4 are connected in a cross coupling mode, so that negative resistance can be formed to supplement the energy consumed by the resonant cavity. The fifth MOS tube M5 is arranged as a tail current tube, so that the oscillation starting of the oscillator and the stable waveform output can be ensured. Through adjusting the sizes of the third MOS tube M3, the fourth MOS tube M4 and the fifth MOS tube M5, the oscillator meets the starting condition and has stable voltage swing.
In yet another embodiment of the present application, the present application performs a simulation experiment on the Gao Xiebo rejection ratio wideband injection-locked two-tripler described above:
the simulation experiment element adopts an SMIC 55nm RF CMOS process, and the simulation circuit is built based on CADENCE IC618 simulation experiment platform.
According to the simulation, a SPECTRE RF simulation tool is adopted to simulate and verify the high-harmonic suppression ratio broadband injection locking two-tripler, a specific circuit diagram is shown in fig. 1, the resistance values of a first resistor R1 and a second resistor R2 are 4kΩ, the capacitance values of a first capacitor C1 and a second capacitor C2 are 2pF, the capacitance values of a third capacitor C3 and a fourth capacitor C4 are 250fF, a first MOS tube M1, a second MOS tube M2, a third MOS tube M3 and a fourth MOS tube M4 are radio-frequency NMOS transistors (n12ll_ckt_rf) in an SMIC 55nm RF CMOS process, a fifth MOS tube M5 and a sixth MOS tube M6 are radio-frequency NMOS transistors (n12ll_ckt_rf) in the SMIC 55nm RF CMOS process, a given power supply voltage VDD is 1.2V, the working temperature is 27 ℃, and bias voltages Vb1 and Vb2 are 0.35V. As shown in fig. 4, a simulation diagram of an operating frequency range is shown, in which the abscissa represents an output frequency (GHz), the ordinate represents an input power (dBm), the square plot represents a frequency doubling, and the circular plot represents a frequency doubling. As shown by the simulation result of the working frequency, the bandwidth at the time of frequency doubling is 22.2GHz to 32.4GHz, the bandwidth at the time of frequency doubling is 25.2 GHz to 41.4GHz, and the total bandwidth is 22.2GHz to 41.4GHz; in the application, the frequency bands corresponding to different frequency multiplication modes are overlapped with each other, so that the bandwidth is equivalently enlarged; the harmonic rejection ratio simulation was performed for the circuit in the above specific embodiment, and as shown in fig. 5, the harmonic rejection ratio of the frequency multiplier of the present application is lower than-50 dBc in the operating frequency range.
The above-described embodiments of the apparatus are merely illustrative, and the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or plug-ins may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are referred to each other, and each embodiment is mainly described in a different manner from other embodiments. In particular, for system embodiments, the description is relatively simple as it is substantially similar to method embodiments, and reference is made to the section of the method embodiments where relevant. In the description of the present specification, reference to the terms "one embodiment," "another embodiment," "yet another embodiment," and the like, means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present specification. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.
Claims (9)
1. The high-harmonic rejection ratio broadband injection locking double-frequency converter is characterized by comprising an injector, a load pair and a multi-harmonic extraction transformer, wherein the multi-harmonic extraction transformer comprises two groups of output inductance groups and one group of input inductance groups, the two groups of output inductance groups are coupled with the input inductance groups, the output ends of the two groups of injectors are connected with the input ends of the input inductance groups, and the output ends of the two groups of injectors are respectively connected with one output end of the load pair;
The output inductor group comprises a first inductor L1 and a second inductor L2, one end of the first inductor L1 is connected with one end of the second inductor L2, the other end of the first inductor L1 and the other end of the second inductor L2 are connected with two capacitors in series, and the connecting ends of the two capacitors are grounded; the other end of the first inductor L1 and the other end of the second inductor L2 are the output ends of one group of output inductor groups;
The input inductance group comprises a third inductance L3 and a fourth inductance L4, one end of the third inductance L3 is connected with one end of the fourth inductance L4, the other end of the third inductance L3 is connected with the output end of one injector, and the other end of the fourth inductance L4 is connected with the output end of the other injector;
The other output inductance group comprises a fifth inductance L5 and a sixth inductance L6, one end of the fifth inductance L5 is connected with one end of the sixth inductance L6, and the other end of the fifth inductance L5 and the other end of the sixth inductance L6 are output ends of the other output inductance group; the connection between the fifth inductor L5 and the sixth inductor L6 is a bias voltage Vb3 connection point.
2. The high-harmonic rejection ratio broadband injection locking double-frequency multiplier according to claim 1, wherein the injector comprises a MOS tube, a capacitor and a resistor, wherein a grid electrode of the MOS tube is connected with one end of the capacitor and one end of the resistor, a source electrode of the MOS tube is grounded, a drain electrode of the MOS tube is connected with an input end of an input inductance group, and the other end of the capacitor is connected with an input signal; the other end of the resistor is a bias voltage connection point.
3. The high-harmonic rejection ratio broadband injection locking two-octave mixer according to claim 1, wherein the load pair comprises a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5 and a sixth MOS tube M6, wherein a drain electrode of the third MOS tube M3 is connected with a grid electrode of the fourth MOS tube M4, and a junction between the drain electrode of the third MOS tube M3 and the grid electrode of the fourth MOS tube M4 is used as an output end of the load pair;
The drain electrode of the fourth MOS tube M4 is connected with the grid electrode of the third MOS tube M3, and the joint of the drain electrode of the fourth MOS tube M4 and the grid electrode of the third MOS tube M3 is used as the other output end of the load pair;
the source electrode of the fifth MOS tube M5 is grounded, and the drain electrode of the fifth MOS tube M5 is respectively connected with the source electrode of the third MOS tube M3 and the source electrode of the fourth MOS tube M4;
The drain electrode of the sixth MOS tube M6 is connected with the grid electrode of the sixth MOS tube M6 and the grid electrode of the fifth MOS tube M5 respectively, the drain electrode of the sixth MOS tube M6 is connected with the power supply VDD, and the source electrode of the sixth MOS tube M6 is grounded.
4. The high harmonic rejection ratio wideband injection locked double frequency multiplier as claimed in claim 1, wherein the first inductor L1 is coupled with the third inductor L3, and the coupling coefficient of the first inductor L1 and the third inductor L3 is k1; the second inductor L2 is coupled with the fourth inductor L4, and the coupling coefficient of the second inductor L2 and the fourth inductor L4 is k1.
5. The high harmonic rejection ratio wideband injection locked tripler of claim 4, wherein k1 has a value of 0.3-0.5 for even harmonics in the injector injection current; for the odd harmonics in the injector injection current, k1 takes a value of 0.001.
6. The high harmonic rejection ratio wideband injection locked double frequency tripler as claimed in claim 1 wherein said third inductor L3 is coupled to a fifth inductor L5, the coupling coefficient of the third inductor L3 and the fifth inductor L5 being k2; the fourth inductor L4 is coupled with the sixth inductor L6, and the coupling coefficient of the fourth inductor L4 and the sixth inductor L6 is k2.
7. The high harmonic rejection ratio wideband injection locked tripler of claim 6, wherein k2 has a value of 0.001 for even harmonics in the injector injection current; for the odd harmonics in the injector injection current, k2 takes a value of 0.2-0.4.
8. The high harmonic rejection ratio wideband injection locked double frequency tripler as claimed in claim 1 wherein said first inductor L1 is coupled to a fifth inductor L5, said first inductor L1 and fifth inductor L5 having a coupling coefficient k3; the second inductor L2 is coupled with the sixth inductor L6, and the coupling coefficient of the second inductor L2 and the sixth inductor L6 is k3.
9. The high harmonic rejection ratio wideband injection locked tripler as recited in claim 8 wherein k3 has a value of 0.4-0.6.
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| CN202410670986.7A CN118249747B (en) | 2024-05-28 | 2024-05-28 | High harmonic rejection ratio broadband injection locking double-frequency multiplier |
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