CN118249626A - SLVS driver circuit with self-regulating differential mode voltage - Google Patents

SLVS driver circuit with self-regulating differential mode voltage Download PDF

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Publication number
CN118249626A
CN118249626A CN202410257846.7A CN202410257846A CN118249626A CN 118249626 A CN118249626 A CN 118249626A CN 202410257846 A CN202410257846 A CN 202410257846A CN 118249626 A CN118249626 A CN 118249626A
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China
Prior art keywords
pmos tube
tube
nmos
current mirror
circuit
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虞致国
崔超
顾晓峰
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Jiangnan University
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Jiangnan University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Logic Circuits (AREA)

Abstract

The invention discloses a differential mode voltage self-regulating SLVS driver circuit, and belongs to the technical field of integrated circuits. The circuit realizes the copy of the higher value of the positive and negative end output voltages of the SLVS driver, stable negative feedback is introduced into the driver, the higher value of the positive and negative end output voltages of the SLVS driver circuit is ensured to be stabilized at about 300mV, and the common mode voltage is stabilized at 200mV by common mode feedback, so that the differential mode voltage is simultaneously stabilized at 200mV, and the self-adjustment stability of the differential mode voltage of the SLVS driver is realized. And because the proposed structure directly compensates and adjusts the output voltage dynamically, if the terminal resistor has larger error due to the process resistance deviation or current bias, the stability of the differential mode voltage of 200mV on the terminal resistor can be still maintained. The proposed architecture has the simplicity of an analog feedback system, eliminates the requirements for high-precision resistors with high cost and post-process calibration, also eliminates the influence of current mirror mismatch or channel width modulation effect on copy precision, and can ensure dynamic stable adjustment of differential mode voltage of 200mV under the conditions of deviation of resistor resistance and the like under each process angle.

Description

SLVS driver circuit with self-regulating differential mode voltage
Technical Field
The invention relates to a differential mode voltage self-regulating SLVS driver circuit, and belongs to the technical field of integrated circuits.
Background
SLVS (Scalable Low-Voltage Signaling, scalable Low-voltage signal standard) is a communication protocol for high-speed serial data transmission, which uses Low-swing differential signal lines to transmit data. The protocol is used for a point-to-point data transmission mode and comprises a transmitting end and a receiving end, and the switching between states 0 and 1 needs to consume less electric charge, and has the characteristics of low power consumption, low error rate and crosstalk resistance.
The SLVS protocol defines transmission parameters and electrical characteristics of signals on a physical layer, and for an SLVS driver, a stable 200mV differential mode level is required, in the prior art, the SLVS driver uses a large-size transistor as a current source to provide 2mA of current, the current is usually obtained by current reference through current mirror copy amplification, the voltage drop of 100 Ω resistor flowing through a receiving end is ensured to be 200mV, the voltage is the differential mode voltage of the driver, but the level is greatly influenced by non-ideal factors such as process angle and the like, such as current mirror circuit copy deviation, resistance deviation, driving voltage variation, and the driver can have unstable differential mode voltage.
In order to solve the problem of lower differential mode voltage precision of the traditional SLVS driver in the prior art, one conventional method is to adopt resistor trimming to trim the resistor in the current reference in the design of the driver, but the process cost of the method is too high. Still another method is to control and adjust the resistance value of the resistor by adding a digital switch control signal to the current reference, so as to eliminate the influence of the process deviation of the resistor, and further ensure the accuracy of the current reference current, such as the SLVS driver design method disclosed in document (H.Hernandez,D.Carvalho,B.Sanches,etal.Current mode 1.2-Gbps SLVS transceiver for readout front-end ASIC[C]2017IEEE International Symposium on Circuits and Systems(ISCAS).IEEE,2017:1-4.). The method has the defects that an external signal is required to be added to adjust the resistance value of the resistor, and the influence of the mismatch of a current mirror or the effect of channel width modulation on the copy precision cannot be eliminated, so that the differential mode voltage of the SLVS driver cannot be ensured to be stable at 200mV.
Disclosure of Invention
In order to solve the problem of unstable differential mode voltage of an SLVS driver circuit, the invention designs the SLVS driver circuit with self-regulating differential mode voltage, and the differential mode voltage is stabilized by using a differential mode voltage detection feedback compensation circuit.
The invention provides a differential mode voltage self-regulating SLVS driver circuit, which is used for dynamically and stably regulating a load R LOAD to a constant value, and comprises a main body driving circuit, a first current mirror, a common mode voltage feedback regulating circuit and a differential mode voltage feedback regulating circuit; the differential mode voltage feedback regulating circuit is composed of a positive end and negative end output voltage higher value copy circuit, an operational amplifier and an MOS tube serving as a current source, wherein the positive end and negative end output voltage higher value copy circuit is composed of a second current mirror and three NMOS tubes.
Optionally, the main body driving circuit is composed of a second PMOS tube PM2, a third PMOS tube PM3, a first NMOS tube NM1 and a second NMOS tube NM 2; the first current mirror is composed of a third NMOS tube NM3 and a fourth NMOS tube NM 4; the common-mode voltage feedback regulating circuit consists of a first resistor R S1, a second resistor R S2, a first operational amplifier AMP1 and a first PMOS tube PM 1.
Optionally, the differential mode voltage feedback regulation circuit includes a positive and negative output voltage higher value copy circuit, a second operational amplifier AMP2, and an eighth NMOS transistor NM8 serving as a current source; the copy circuit with higher output voltage at the positive and negative ends consists of a fifth NMOS tube NM5, a sixth NMOS tube NM6, a seventh NMOS tube NM7 and a second current mirror; the source ends of the fifth NMOS tube NM5, the sixth NMOS tube NM6 and the seventh NMOS tube NM7 are grounded, the drain ends of the fifth NMOS tube NM5 and the sixth NMOS tube NM6 are connected with the input end of the second current mirror, and the gate ends of the fifth NMOS tube NM5 and the sixth NMOS tube NM6 are respectively connected with voltages V OP and V ON at two ends of a load in the SLVS driver circuit; the drain terminal and the gate terminal of the seventh NMOS transistor NM7 are connected, and are connected to the output terminal of the second current mirror.
Optionally, in the working process of the copy circuit with the higher output voltage of the positive and negative ends, the NMOS tube corresponding to the gate end accessed by the higher value in V OP and V ON is in a saturation region, and the NMOS tube corresponding to the gate end accessed by the lower value is cut off; the second current mirror works in a saturation region, and copies the current in the saturation region in the fifth NMOS tube NM5 and the sixth NMOS tube NM6 to the seventh NMOS tube NM7, so that the output V HIGH of the copy circuit with higher value of the output voltage of the positive and negative ends is the higher value of the output voltage values of the positive and negative ends of the SLVS driver.
Optionally, the second current mirror includes a basic structure, a cascode structure, and a wide swing structure current mirror.
Optionally, the current mirror of the basic structure consists of an eighth PMOS tube PM8 and a ninth PMOS tube PM 9; the source ends of the eighth PMOS tube PM8 and the ninth PMOS tube PM9 are connected with a power supply VDD, the gate ends of the eighth PMOS tube PM8 and the eighth PMOS tube PM8 are connected with the drain ends of the fifth NMOS tube NM5 and the sixth NMOS tube NM6, namely the drain ends of the ninth PMOS tube PM9 are connected with the drain ends and the gate ends of the seventh NMOS tube NM7, namely the output ends of the second current mirror.
Optionally, the current mirror of the cascode structure is composed of a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6 and a seventh PMOS tube PM 7; the source ends of the fourth PMOS tube PM4 and the fifth PMOS tube PM5 are connected with a power supply VDD, the gate ends of the fourth PMOS tube PM4 and the source end of the fifth PMOS tube PM6 are connected with the drain end of the fifth PMOS tube PM5 and the source end of the seventh PMOS tube PM7, the gate ends of the sixth PMOS tube PM6 and the seventh PMOS tube PM7 and the drain end of the sixth PMOS tube PM6 are connected with the drain ends of the fifth NMOS tube NM5 and the sixth NMOS tube NM6, namely the drain end of the seventh PMOS tube PM7 is connected with the drain end and the gate end of the seventh NMOS tube NM7, namely the output end of the second current mirror.
Optionally, the current mirror with the wide swing structure is composed of a tenth PMOS tube PM10, an eleventh PMOS tube PM11, a twelfth PMOS tube PM12 and a thirteenth PMOS tube PM 13; the source ends of the tenth PMOS tube PM10 and the eleventh PMOS tube PM11 are connected with a power supply VDD, the gate ends of the tenth PMOS tube PM10 and the eleventh PMOS tube PM11 are connected to the drain end of the twelfth PMOS tube PM12, and are connected with the drain ends of the fifth NMOS tube NM5 and the sixth NMOS tube NM6 at the same time, namely, the drain end of the tenth PMOS tube is connected with the source end of the twelfth PMOS tube, the drain end of the eleventh PMOS tube PM11 is connected with the source end of the thirteenth PMOS tube PM13, and the drain end of the thirteenth PMOS tube PM13 is connected with the drain end and the gate end of the seventh NMOS tube NM7, namely, the drain end of the second current mirror is used as the output end of the second current mirror. The gate terminal voltages V BIAS of PM12, PM13 are provided by voltage bias.
The application also provides a circuit for copying the higher value of the positive and negative output voltages, which is applied to realizing the copying of the higher value of the positive and negative output voltages V OP and V ON in the SLVS driver circuit, wherein the circuit for copying the higher value of the positive and negative output voltages consists of a current mirror and three NMOS tubes, and the source ends of the three NMOS tubes are grounded; the drain ends of the two NMOS tubes are connected with the input end of the current mirror, and the gate ends of the two NMOS tubes are respectively connected with voltages V OP and V ON at two ends of a load in the SLVS driver circuit; the drain end of the other NMOS tube is connected with the gate end and then connected with the output end of the current mirror.
Optionally, the structure of the current mirror includes a basic structure, a cascode structure, and a wide swing structure.
The invention has the beneficial effects that:
The invention realizes the copy of the higher value of the positive and negative output voltages of the SLVS driver, introduces stable negative feedback into the driver, ensures that the higher value of the positive and negative output voltages of the SLVS driver circuit is stabilized at about 300mV, and the common mode voltage is stabilized at 200mV by common mode feedback, so that the differential mode voltage is simultaneously stabilized at 200mV, and realizes the self-adjustment and stabilization of the differential mode voltage of the SLVS driver. And because the proposed structure directly compensates and adjusts the output voltage dynamically, if the terminal resistor has resistance deviation or larger error of current bias current due to the process, the stability of the differential mode voltage of 200mV on the terminal resistor can be still maintained. The proposed architecture has the simplicity of an analog feedback system, eliminates the requirements for high-precision resistors with high cost and post-process calibration, also eliminates the influence of current mirror mismatch or channel width modulation effect on copy precision, and can ensure dynamic stable adjustment of differential mode voltage of 200mV under the conditions of deviation of resistance values of various resistors and the like under various process angles.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of a conventional SLVS driver.
Fig. 2 is a schematic diagram of a single-ended differential circuit in accordance with an embodiment of the present application.
FIG. 3 is a schematic diagram of a circuit for copying the higher value of the output voltage of the positive and negative terminals provided by the invention.
FIG. 4 is a schematic diagram of a differential mode voltage self-regulating SLVS driver circuit provided by the present invention.
Fig. 5 is a schematic diagram of a circuit for copying a higher value of output voltage of a positive end and a negative end of a current mirror based on a cascode structure.
FIG. 6 is a schematic diagram of a circuit for copying the higher value of the output voltage of the positive and negative ends of the current mirror based on the basic structure.
Fig. 7 is a schematic diagram of a circuit for copying a higher value of output voltage of a positive end and a negative end of a current mirror based on a wide swing structure.
FIG. 8 is a waveform diagram illustrating the operation of the positive and negative output voltage higher value copy circuit of the present invention.
FIG. 9 is a simulated waveform diagram of the differential mode voltage self-regulating SLVS driver circuit of the present invention.
Fig. 10 is a simulated waveform diagram of a conventional SLVS driver circuit.
FIG. 11 is a simulated waveform diagram of the differential mode voltage self-regulating SLVS driver circuit of the present invention in the event of current bias misalignment.
Fig. 12 is a simulated waveform diagram of a conventional SLVS driver circuit in the case of current bias misalignment.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
The conventional SLVS driver circuit is first described as follows:
As shown in fig. 1, the conventional SLVS driver circuit includes a body driver circuit, a common mode voltage feedback regulation circuit, a current bias, a voltage bias, and a first current mirror; the main body driving circuit consists of a second PMOS tube PM2, a third PMOS tube PM3, a first NMOS tube NM1 and a second NMOS tube NM 2; the common-mode voltage feedback regulating circuit consists of a first resistor R S1, a second resistor R S2, a first operational amplifier AMP1 and a first PMOS tube PM 1; the current mirror is composed of a third NMOS transistor NM3 and a fourth NMOS transistor NM4 (for distinguishing from the current mirror in the copy circuit with higher positive and negative output voltages provided by the present application, in the following description, the current mirror in the conventional SLVS driver circuit is described with its constituent components, the third NMOS transistor NM3 and the fourth NMOS transistor NM4, and not described with the "current mirror"; the voltage bias is used to provide the first operational amplifier AMP1 with a constant voltage V REF_0P2V,VREF_0P2V = 0.2V; the current bias is used for providing constant current I REF to ensure that the current of NM3 is 2mA; the input voltages V IP and V IN of the body drive circuit are provided by single-ended to differential circuits.
In the scheme of the application, as shown in fig. 2, a full inverter is used in the positive column of two differential signals, and the negative column is one inverter less than the positive column, so that the positive and negative column signals are opposite. Because the negative column has one less inverter and the two columns have different signal delays, the negative column replaces the missing inverter with a customized transmission gate, and the transmission gate is kept normally on, and only provides delay for the circuit so as to ensure that the two delays of the differential output of the positive column and the negative column are basically the same.
The SLVS driver body shown in fig. 1 adopts an upper and lower dual current source mode, so that the feedback adjustment speed of the circuit is accelerated, the switching tube adopts the combination of PMOS and NMOS, the driver circuit has a common mode feedback loop, the stability of common mode voltage can be ensured, but the circuit lacks the design of a differential mode voltage stabilizing loop, so that the differential mode voltage can deviate from 200mV frequently. Even if trimming is added to the current reference to ensure the accuracy of I REF, the driving current of NM3 may still deviate through the copy of the current mirror, so the differential mode voltage of the driver of SLVS is difficult to ensure.
Embodiment one:
The embodiment provides a copy circuit with higher positive and negative output voltages, which can be applied to copy the higher voltage of positive and negative output voltages V OP and V ON in an SLVS driver circuit. The positive and negative end output voltage higher value copy circuit is composed of a current mirror (namely a second current mirror, and the current mirror appearing later in the application refers to the current mirror in the positive and negative end output voltage higher value copy circuit, namely the second current mirror) and three NMOS (N-channel metal oxide semiconductor) transistors, as shown in figure 3, the positive and negative end output voltage higher value copy circuit is composed of a fifth NMOS transistor NM5, a sixth NMOS transistor NM6, a seventh NMOS transistor NM7 and a current mirror; the source ends of the fifth NMOS tube NM5, the sixth NMOS tube NM6 and the seventh NMOS tube NM7 are grounded, the drain ends of the fifth NMOS tube NM5 and the sixth NMOS tube NM6 are connected with the input end of the current mirror, and the gate ends of the fifth NMOS tube NM5 and the sixth NMOS tube NM6 are respectively connected with voltages V OP and V ON at two ends of a load in the SLVS driver circuit; the drain terminal and the gate terminal of the seventh NMOS transistor NM7 are connected, and are connected to the output terminal of the current mirror.
Because the gate ends of the fifth NMOS tube NM5 and the sixth NMOS tube NM6 are respectively connected with the voltages V OP and V ON at the two ends of the load in the SLVS driver circuit, the gate end with the higher value of V OP and V ON can make the corresponding NMOS tube be in the saturation region, the gate end with the lower value can make the corresponding NMOS tube be cut off, the current mirror works in the saturation region, and the current in the saturation region in the fifth NMOS tube NM5 and the sixth NMOS tube NM6 can be copied to NM7, so that the output V HIGH of the copy circuit with the higher output voltage at the positive and negative ends is the higher value of the output voltage values at the positive and negative ends of the SLVS driver.
Embodiment two:
Based on the higher value copy circuit of positive and negative output voltages provided in the first embodiment, the present embodiment provides a differential mode voltage self-adjusting SLVS driver circuit, see fig. 4, which includes a main body driving circuit, a common mode voltage feedback adjustment circuit and a differential mode voltage feedback adjustment circuit; the differential mode voltage self-regulating circuit for the SLVS driver adds a differential mode voltage feedback regulation circuit relative to the conventional SLVS driver circuit shown in fig. 1; the differential mode voltage feedback adjustment circuit is implemented based on the positive and negative end output voltage higher value copy circuit provided in the first embodiment, that is, is composed of the positive and negative end output voltage higher value copy circuit, an operational amplifier and a MOS transistor serving as a current source, as shown in fig. 4, and includes the positive and negative end output voltage higher value copy circuit, the second operational amplifier AMP2 and the eighth NMOS transistor NM8 serving as a current source.
In the SLVS driver circuit with self-regulating differential mode voltage provided by the embodiment, the main body driving circuit consists of a second PMOS tube PM2, a third PMOS tube PM3, a first NMOS tube NM1 and a second NMOS tube NM 2; the common-mode voltage feedback regulating circuit consists of a first resistor R S1, a second resistor R S2, a first operational amplifier AMP1 and a first PMOS tube PM 1; the voltage across load R LOAD is noted as V OP and V ON, respectively.
The copy circuit with higher positive and negative output voltages is shown in fig. 3, and the copy circuit with higher positive and negative output voltages consists of a fifth NMOS tube NM5, a sixth NMOS tube NM6, a seventh NMOS tube NM7 and a current mirror, wherein V OP and V ON are respectively connected to the gate ends of NM5 and NM6, and the higher value of V OP and V ON is 300mV and the lower value is 100mV when SLVS works normally. The higher value access gate terminal in V OP and V ON will place the corresponding NMOS in saturation region, and the lower value access gate terminal will turn off the corresponding NMOS. The current mirror works in the saturation region, and can copy the current in the saturation region in the fifth NMOS tube NM5 and the sixth NMOS tube NM6 to the seventh NMOS tube NM7.
The current formula of the NMOS transistor working in the saturation region under the condition of neglecting the channel width modulation effect is as follows:
wherein mu n is the electron mobility of the NMOS tube, C ox is the gate oxide capacitance of the MOS tube, The width-to-length ratio of the MOS transistor is V GS, the gate-source voltage of the NMOS transistor and V TH, the threshold voltage of the NMOS transistor.
The current formula generated after NM5 or NM6 is conducted is as follows:
Wherein the source terminals of NM5 and NM6 are grounded, V GS is the gate terminal voltage of NM5 or NM6, V OP is the positive output of the SLVS driver, connected to the gate terminal of NM5, V ON is the negative output of the SLVS driver, connected to the gate terminal of NM6, V MAX(OP,ON) represents the larger value of the gate terminal voltage in NM5 and NM6, Is the aspect ratio of NM5 and NM 6.
Since the source of NM7 is grounded, NM7 produces a current formula:
Wherein the source terminal of NM7 is grounded, V GS is the gate terminal voltage of NM7, because the drain terminal of NM7 is connected with the gate terminal, the gate terminal voltage is V HIGH, Is the aspect ratio of NM 7.
From the current mirror copy effect, it is possible to obtain:
I1＝I2 (4)
The NM5, NM6 and NM7 can be obtained by making the sizes the same The method further comprises the following steps:
VHIGH＝VMAX(OP,ON) (5)
I.e., the output V HIGH of the positive and negative output voltage higher value copy circuit is the higher value of the positive and negative output voltage values of the SLVS driver.
The output V HIGH of the copy circuit with higher output voltage at the positive and negative ends is connected to the negative input end of the second operational amplifier AMP2, and the positive input end of the second operational amplifier AMP2 is connected to the reference voltage V REF_0P3V =300 mV. The NM3 provides bias current, the width-to-length ratio of NM3 and NM4 is regulated, the current of NM3 can be set to be about 80% of the standard current, namely about 1.6mA, the value can be set, the NM3 current is set to be more than 50% and less than 100% of the standard current, and the rest current is regulated and controlled by a differential mode voltage negative feedback circuit.
Example III
Based on various implementation manners of the current source, the embodiment provides a copy circuit with higher output voltage at the positive and negative ends of a current mirror based on a common-source common-gate structure, which consists of the current mirror with the common-source common-gate structure and three NMOS tubes, as shown in fig. 5, the copy circuit with higher output voltage at the positive and negative ends adopts the common-source common-gate structure. The PMOS transistors PM4, PM5, PM6 and PM7 constitute a cascode current mirror, i.e. a schematic block diagram of the current mirror corresponding to fig. 3 and 4. The source ends of PM4 and PM5 are connected with a power supply VDD, the gate ends of PM4 and PM5 and the drain end of PM4 are connected with the source end of PM6, the drain end of PM5 is connected with the source end of PM7, the gate ends of PM6 and PM7 and the drain end of PM6 are connected with the drain ends of NM5 and NM6, the ends correspond to the input ends of the current 4 mirrors in the figures 3 and 4, and the drain end of PM7 corresponds to the output ends of the current mirrors in the figures 3 and 4.
Correspondingly, based on the positive and negative terminal output voltage higher value copy circuit provided by the embodiment, the embodiment also provides a differential mode voltage self-adjusting SLVS driver circuit, namely, the positive and negative terminal output voltage higher value copy circuit in the circuit shown in fig. 4 is replaced by the positive and negative terminal output voltage higher value copy circuit shown in fig. 5 provided by the embodiment.
Example IV
The embodiment provides a copy circuit with higher output voltage at the positive and negative ends of a current mirror based on a basic structure, which consists of the current mirror with the basic structure and three NMOS tubes, as shown in fig. 6, the current mirror with the higher output voltage at the positive and negative ends adopts the basic structure. The PMOS transistors PM8, PM9 constitute a basic current mirror, i.e. a schematic block diagram of the current mirror corresponding to fig. 3 and 4. The source terminals of PM8 and PM9 are connected to the power supply VDD, the gate terminals of PM8 and PM9, and the drain terminal of PM8 are connected to the drain terminals of NM5 and NM6, which correspond to the input terminals of the current mirror of fig. 3 and 4, and the drain terminal of PM9 corresponds to the output terminal of the current mirror of fig. 3 and 4.
Correspondingly, based on the positive and negative terminal output voltage higher value copy circuit provided by the embodiment, the embodiment also provides a differential mode voltage self-regulating circuit always facing the SLVS driver, namely the positive and negative terminal output voltage higher value copy circuit in the circuit shown in fig. 4 is replaced by the positive and negative terminal output voltage higher value copy circuit shown in fig. 6 provided by the embodiment.
Example five
The embodiment provides a copy circuit with higher output voltage at the positive and negative ends of a current mirror based on a wide-swing structure, which consists of a current mirror with a wide-swing structure and three NMOS (N-channel metal oxide semiconductor) tubes, as shown in fig. 7, wherein the current mirror with the higher output voltage at the positive and negative ends adopts the wide-swing current mirror structure. The PMOS transistors PM10, PM11, PM12 and PM13 constitute a wide-swing current mirror, i.e. the schematic block diagrams of the current mirrors in fig. 3 and 4. The source terminals of PM10 and PM11 are connected to the power supply VDD, the gate terminals of PM10 and PM11 are connected to the drain terminal of PM12, and are simultaneously connected to the drain terminals of NM5 and NM6, which correspond to the input terminals of the current mirror of fig. 3 and 4, the drain terminal of PM10 is connected to the source terminal of PM12, the drain terminal of PM11 is connected to the source terminal of PM13, and the drain terminal of PM13 corresponds to the output terminal of the current mirror of fig. 3 and 4. The gate terminal voltages V BIAS of PM12, PM13 are provided by voltage bias.
Correspondingly, based on the positive and negative terminal output voltage higher value copy circuit provided by the embodiment, the embodiment also provides a differential mode voltage self-adjusting SLVS driver circuit, namely, the positive and negative terminal output voltage higher value copy circuit in the circuit shown in fig. 4 is replaced by the positive and negative terminal output voltage higher value copy circuit shown in fig. 7 provided by the embodiment.
For the above embodiment, the following description is given of the principle of the differential mode voltage feedback adjustment circuit added to the differential mode voltage self-adjustment circuit for SLVS driver according to the present application, where the principle is as follows:
as shown in fig. 4, based on the loop negative feedback regulation principle, when the value of V HIGH is higher than the reference voltage 300mV, it indicates that the current flowing into the SLVS driver is greater than 2mA, the output of the second operational amplifier AMP2 decreases, i.e., the gate terminal voltage of the access NM8 decreases, and the NM8 current decrease regulates the current flowing into the SLVS driver to 2mA; when the value of V HIGH is lower than the reference voltage 300mV, indicating that the current flowing into the SLVS driver is less than 2mA, the output of the second operational amplifier AMP2 is raised, i.e. the gate terminal voltage at which NM8 is connected is raised, and NM6 current is increased to regulate the current flowing into the SLVS driver to 2mA. The positive and negative terminals output higher voltage copy circuit, the second operational amplifier AMP2 and the sixth NMOS tube NM8 form a differential mode voltage feedback regulating circuit, and the differential mode voltage is regulated and stabilized at 200mV. Under the condition of each process angle, the differential mode voltage feedback regulating circuit regulates the output swing to about 200mV through a unique feedback loop of a detection circuit with higher output voltage of the positive end and the negative end of the differential mode voltage feedback regulating circuit and a common mode feedback circuit.
FIG. 8 is a simulated waveform of the positive and negative output voltage higher value copy circuit, V OP and V ON are differential voltage inputs of 300mV and 100mV, and the output V HIGH of the positive and negative output voltage higher value copy circuit can copy the higher value of the voltages in V OP and V ON, namely 300mV, more accurately.
Fig. 9 is a simulation waveform of a SLVS driver circuit with self-adjusting differential mode voltage, the circuit structure adopts the structure of fig. 4, the current mirror adopts the cascode current mirror of fig. 5, the value of I REF is set to 80% of the standard value and is 80 μa, NM4 to NM3 are amplified by 20 times of current, the theoretical value of NM3 current is 1.6mA, and the current of NM4 can compensate the sum of the currents of NM4 and NM3 to 2mA through differential mode voltage negative feedback compensation. V IN and V IP are differential voltage inputs, V OP and V ON are differential outputs of the driver, and their difference is 198.78mV as can be seen from the simulated waveforms. The differential mode voltage stabilizes at about 200 mV.
Fig. 10 is a simulation waveform of a conventional SLVS driver circuit, the circuit structure adopts the structure of fig. 1, the value of I REF is set to be 100 μa, NM4 to NM3 are amplified 20 times of current, the theoretical value of NM3 current is 2mA, and the theoretical value of differential mode voltage is 2mA, but because the copy error of a current mirror caused by the channel width modulation effect is included, the actual current of NM3 is not 2mA, and the actual differential mode voltage error is larger. V IN and V IP are differential voltage inputs, V OP and V ON are differential outputs of the driver, and the difference value of the differential voltage inputs and the differential voltage inputs is 166.10mV as seen from a simulation waveform diagram, and the differential voltage error of the feedback loop without differential mode voltage is larger.
FIG. 11 is a simulated waveform of the SLVS driver circuit with self-regulated differential mode voltage under the condition of inaccurate bias current, the circuit structure adopts the structure of FIG. 4, the current mirror adopts the common-source common-gate current mirror of FIG. 5, the value of I REF is set to 64 mu A as 64% of the standard value, NM4 to NM3 are amplified by 20 times of current, the theoretical value of NM3 current is 1.28mA, and NM4 current can compensate the sum of NM4 and NM3 current to 2mA through differential mode voltage negative feedback compensation. V IN and V IP are differential voltage inputs, V OP and V ON are differential outputs of the driver, and their difference is 198.85mV as can be seen from the simulated waveforms. The differential mode voltage is still stable around 200mV in the case of bias current misalignment.
Fig. 12 is a simulation waveform of a conventional SLVS driver circuit in the case of inaccurate bias current, the circuit structure adopts the structure of fig. 1, and in the case of inaccurate reference value of the analog current, the value of I REF is set to 80% of the standard value of 100 μa, NM4 to NM3 are amplified 20 times of current, the theoretical value of NM3 current is 1.6mA, the theoretical value of differential mode voltage is 160mV, and there is a large offset. V IN and V IP are differential voltage inputs, V OP and V ON are differential outputs of the driver, and as can be seen from the simulation waveform diagram, their difference is 139.20mV, and because there is no differential mode voltage feedback loop, the current mirror copy error and the current bias inaccuracy cause the error to be superimposed, resulting in a larger differential mode voltage error.
Some steps in the embodiments of the present invention may be implemented by using software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims (10)

1. The SLVS driver circuit with the self-regulating differential mode voltage is characterized by being used for dynamically and stably regulating a load R LOAD with the constant differential mode voltage, and comprises a main body driving circuit, a first current mirror, a common mode voltage feedback regulating circuit and a differential mode voltage feedback regulating circuit; the differential mode voltage feedback regulating circuit is composed of a positive end and negative end output voltage higher value copy circuit, an operational amplifier and an MOS tube serving as a current source, wherein the positive end and negative end output voltage higher value copy circuit is composed of a second current mirror and three NMOS tubes.
2. The SLVS driver circuit of claim 1, wherein the main driving circuit is composed of a second PMOS tube PM2, a third PMOS tube PM3, a first NMOS tube NM1, and a second NMOS tube NM 2; the first current mirror is composed of a third NMOS tube NM3 and a fourth NMOS tube NM 4; the common-mode voltage feedback regulating circuit consists of a first resistor R S1, a second resistor R S2, a first operational amplifier AMP1 and a first PMOS tube PM 1.
3. The SLVS driver circuit according to claim 2, wherein the differential mode voltage feedback regulation circuit includes a positive and negative output voltage higher value copy circuit, a second operational amplifier AMP2, and an eighth NMOS transistor NM8 serving as a current source; the copy circuit with higher output voltage at the positive and negative ends consists of a fifth NMOS tube NM5, a sixth NMOS tube NM6, a seventh NMOS tube NM7 and a second current mirror; the source ends of the fifth NMOS tube NM5, the sixth NMOS tube NM6 and the seventh NMOS tube NM7 are grounded, the drain ends of the fifth NMOS tube NM5 and the sixth NMOS tube NM6 are connected with the input end of the second current mirror, and the gate ends of the fifth NMOS tube NM5 and the sixth NMOS tube NM6 are respectively connected with voltages V OP and V ON at two ends of a load in the SLVS driver circuit; the drain terminal and the gate terminal of the seventh NMOS transistor NM7 are connected, and are connected to the output terminal of the second current mirror.
4. The SLVS driver circuit of claim 3, wherein during operation of the positive and negative output voltage higher value copy circuit, NMOS transistors corresponding to the gate terminal connected with higher value in V OP and V ON are in saturation region, and NMOS transistors corresponding to the gate terminal connected with lower value are turned off; the second current mirror works in a saturation region, and copies the current in the saturation region in the fifth NMOS tube NM5 and the sixth NMOS tube NM6 to the seventh NMOS tube NM7, so that the output V HIGH of the copy circuit with higher value of the positive and negative end output voltage is the higher value of the positive and negative end voltage output values of the SLVS driver.
5. The differential mode voltage self-regulating SLVS driver circuit of claim 4, wherein said second current mirror comprises a basic structure, a cascode structure, and a wide swing structure current mirror.
6. The differential mode voltage self-regulating SLVS driver circuit according to claim 5, wherein the current mirror of the basic structure is composed of an eighth PMOS tube PM8 and a ninth PMOS tube PM 9; the source ends of the eighth PMOS tube PM8 and the ninth PMOS tube PM9 are connected with a power supply VDD, the gate ends of the eighth PMOS tube PM8 and the eighth PMOS tube PM8 are connected with the drain ends of the fifth NMOS tube NM5 and the sixth NMOS tube NM6, namely the drain ends of the ninth PMOS tube PM9 are connected with the drain ends and the gate ends of the seventh NMOS tube NM7, namely the output ends of the second current mirror.
7. The SLVS driver circuit of claim 5, wherein the cascode current mirror is comprised of a fourth PMOS tube PM4, a fifth PMOS tube PM5, a sixth PMOS tube PM6, and a seventh PMOS tube PM 7; the source ends of the fourth PMOS tube PM4 and the fifth PMOS tube PM5 are connected with a power supply VDD, the gate ends of the fourth PMOS tube PM4 and the source end of the fifth PMOS tube PM6 are connected, the drain end of the fifth PMOS tube PM5 is connected with the source end of the seventh PMOS tube, the gate ends of the sixth PMOS tube PM6 and the seventh PMOS tube PM7 are connected with the drain ends of the fifth NMOS tube NM5 and the sixth NMOS tube NM6, namely the drain end of the seventh PMOS tube PM7 is connected with the drain end and the gate end of the seventh NMOS tube NM7, namely the drain end of the seventh PMOS tube PM6 is used as the output end of the second current mirror.
8. The SLVS driver circuit of claim 5, wherein the wide swing current mirror is composed of a tenth PMOS tube PM10, an eleventh PMOS tube PM11, a twelfth PMOS tube PM12 and a thirteenth PMOS tube PM 13; the source ends of the tenth PMOS tube PM10 and the eleventh PMOS tube PM11 are connected with a power supply VDD, the gate ends of the tenth PMOS tube PM10 and the eleventh PMOS tube PM11 are connected with the drain end of the twelfth PMOS tube PM12, and are simultaneously connected with the drain ends of the fifth NMOS tube NM5 and the sixth NMOS tube NM6, namely the drain end of the eleventh PMOS tube PM11 is connected with the source end of the thirteenth PMOS tube PM13, and the drain end of the thirteenth PMOS tube PM13 is connected with the drain end and the gate end of the seventh NMOS tube NM7, namely the drain end of the second current mirror; the drain end of the tenth PMOS tube PM10 is connected with the source end of the twelfth PMOS tube PM12, the drain end of the eleventh PMOS tube PM11 is connected with the source end of the thirteenth PMOS tube PM13, and the gate end voltages V BIAS of the twelfth PMOS tube PM12 and the thirteenth PMOS tube PM13 are provided by voltage bias.
9. The circuit is applied to the copy of the higher voltage value in the positive and negative output voltages V OP and V ON in the SLVS driver circuit, and consists of a current mirror and three NMOS tubes, wherein the source ends of the three NMOS tubes are grounded; the drain ends of the two NMOS tubes are connected with the input end of the current mirror, and the gate ends of the two NMOS tubes are respectively connected with voltages V OP and V ON at two ends of a load in the SLVS driver circuit; the drain end of the other NMOS tube is connected with the gate end and then connected with the output end of the current mirror.
10. The positive and negative output voltage higher value copy circuit of claim 9, wherein the structure of the current mirror comprises a basic structure, a cascode structure, and a wide swing structure.
CN202410257846.7A 2024-03-07 2024-03-07 SLVS driver circuit with self-regulating differential mode voltage Pending CN118249626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202410257846.7A CN118249626A (en) 2024-03-07 2024-03-07 SLVS driver circuit with self-regulating differential mode voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202410257846.7A CN118249626A (en) 2024-03-07 2024-03-07 SLVS driver circuit with self-regulating differential mode voltage

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CN118249626A true CN118249626A (en) 2024-06-25

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