CN118102811A

CN118102811A - Display panel and display device

Info

Publication number: CN118102811A
Application number: CN202410245424.8A
Authority: CN
Inventors: 王冀星; 陈友春; 马鸿博; 王红丽; 梁珂; 徐晶晶; 倪子博; 刘鹏
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2024-03-04
Filing date: 2024-03-04
Publication date: 2024-05-28

Abstract

The embodiment of the disclosure provides a display panel and a display device, which are applied to the technical field of display and can solve the problem that small black spots appear on the surface of an anode of the display panel. A display panel comprises a display area and a peripheral area, wherein the peripheral area comprises a first peripheral area and a second peripheral area; the display panel includes: the display device comprises a substrate, a first source drain metal layer, a first passivation layer and a blocking dam, wherein the blocking dam is positioned in a peripheral area and surrounds a display area, and the first source drain metal layer extends to the first peripheral area and extends to one side of the blocking dam away from the display area; the first passivation layer is positioned in the first peripheral area and covers the part of the first source drain metal layer, which is positioned at the side of the barrier dam, which is far away from the display area; the display panel further includes: the second passivation layer is positioned on one side of the first passivation layer away from the substrate and is positioned in the first peripheral region, and the second passivation layer covers the part of the first passivation layer positioned on one side of the barrier dam away from the display region; the display panel is applied to a display device.

Description

Display panel and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

Display panels, such as OLED (Organic Light-Emitting Diode) display panels, or QLED (Quantum Dot LIGHT EMITTING Diodes) display panels, have been increasingly used in various display devices such as mobile phones, tablets, computers, televisions, etc. due to their self-luminescence characteristics.

When the stacked film layers of the display panel are prepared, the film layers which are prepared in the front are often excessively etched due to the deviation of the preparation process, the metal film layers stacked below the excessively etched film layers are easily leaked, the materials of the leaked metal film layers and the materials of the anode layers of the display panel are subjected to chemical reaction and are separated out on the anode surface, so that small black spots appear on the anode surface of the display panel, and the display effect of the display panel is affected.

Disclosure of Invention

The technical problems solved by some embodiments of the present disclosure are: how to prevent the metal film layer of the display panel from being leaked, and reduce the probability of small black spots on the surface of the anode of the display panel.

In order to solve the above technical problems, some embodiments of the present disclosure provide a display panel, including a display area and a peripheral area located around the display area, the peripheral area including a first peripheral area and a second peripheral area, the second peripheral area including a binding area; the display panel includes: the display device comprises a substrate, a first source drain metal layer arranged on one side of the substrate, a first passivation layer arranged on one side of the first source drain metal layer away from the substrate, and a blocking dam arranged on one side of the first passivation layer away from the substrate, wherein the blocking dam is positioned in a peripheral area and surrounds a display area; the first source drain metal layer extends to the first peripheral region and extends to one side of the barrier dam away from the display region; the first passivation layer comprises a first part positioned in the first peripheral region, and the first part of the first passivation layer covers a part of the first source drain metal layer positioned at one side of the barrier dam away from the display region; the display panel further includes: the second passivation layer is positioned on one side of the first passivation layer away from the substrate and comprises a first part positioned in the first peripheral region, and the first part of the second passivation layer covers the part of the first passivation layer positioned on one side of the barrier dam away from the display region.

The beneficial effects of some embodiments of the present disclosure are: the part of the first passivation layer in the first peripheral area, which is positioned on the side of the barrier dam, is covered with the first part of the first passivation layer, the part of the first passivation layer in the first peripheral area, which is positioned on the side of the barrier dam, is covered with the first part of the second passivation layer, and double-layer protection is formed on the part of the first source drain metal layer, which is positioned on the side of the barrier dam, is covered with the first part of the first passivation layer, so that the metal layer of the display panel, such as the bare drain of the first source drain metal layer, is effectively prevented, and the probability of occurrence of small black spots on the anode surface of the display panel is reduced.

In some embodiments, a first portion of the first passivation layer extends from a surface of a portion of the first source drain metal layer located on a side of the barrier dam away from the display region to a surface of the substrate.

In some embodiments, the barrier dam includes a first barrier dam and a second barrier dam, the second barrier dam being remote from the display area relative to the first barrier dam.

In some embodiments, the first source drain metal layer extends to the second peripheral region and to a side of the second barrier dam away from the display region; the first passivation layer further comprises a second portion located in the second peripheral region, and the second portion of the first passivation layer covers a portion of the first source drain metal layer located between the first barrier dam and the second barrier dam; the second passivation layer further includes a second portion located at the second peripheral region, the second portion of the second passivation layer covering a portion of the first passivation layer located between the first barrier dam and the second barrier dam.

In some embodiments, the first source-drain metal layer includes a plurality of first voltage signal lines extending along a first direction, the plurality of first voltage signal lines being located in the display region and extending to the first peripheral region; the first source drain metal layer further comprises a first voltage signal bus, the first voltage signal bus is located in the first peripheral area, the first voltage signal bus semi-surrounds the display area, the outer side of the first voltage signal bus is located at one side, far away from the display area, of the second barrier dam, and the first voltage signal bus is connected with a plurality of first voltage signal lines; the first source drain metal layer further comprises two first voltage signal connecting wires, the two first voltage signal connecting wires are located in the second peripheral area, and the two first voltage signal connecting wires are respectively connected with two ends of the first voltage signal bus; the first voltage signal connecting line extends from one side of the first barrier dam close to the display area to one side of the second barrier dam far away from the display area; the first part of the first passivation layer covers the part of the first voltage signal bus line located at one side of the second barrier dam away from the display area, and the second part of the first passivation layer covers the part of the first voltage signal connection line located between the first barrier dam and the second barrier dam; the first portion and the second portion of the second passivation layer cover portions of the first passivation layer in the peripheral region.

In some embodiments, the display panel further includes a second source drain metal layer between the first passivation layer and the second passivation layer, the second source drain metal layer extending to a side of the second barrier dam adjacent to the display region, the second source drain metal layer being connected to the first source drain metal layer at the peripheral region; the display panel further comprises an anode layer positioned on one side of the second passivation layer far away from the substrate, the anode layer comprises a lap anode positioned in the peripheral area, and the lap anode is connected with a part of the second source drain metal layer extending to one side of the second barrier dam close to the display area; the display panel further comprises a cathode layer positioned on one side of the anode layer away from the substrate, and the overlapping anode is connected with a part of the cathode layer positioned in the peripheral area.

In some embodiments, the display panel further includes a first planarization layer located on a side of the first passivation layer away from the substrate, the first planarization layer being located at least in the display region; the second source drain metal layer is positioned on one side of the first flat layer far away from the substrate; the display panel also comprises a second flat layer which is positioned on one side of the second source drain metal layer far away from the substrate, and the second flat layer is at least positioned in the display area; the second passivation layer is positioned on one side of the second flat layer away from the substrate, the second passivation layer also comprises a third part positioned in the display area, and the third part of the second passivation layer comprises at least one passivation fault; the anode layer also comprises at least one anode positioned in the display area, and the orthographic projection of the anode on the substrate is positioned in the orthographic projection of the passivation fault on the substrate; the display panel further comprises a pixel defining layer located on a side of the anode layer away from the substrate, the pixel defining layer comprising at least one pixel opening; the pixel opening is arranged corresponding to the anode; the display panel comprises a groove penetrating from the pixel defining layer to the second flat layer, and the groove is positioned on at least one side of the pixel opening; the edge part of the passivation fault extends out from the side wall of the groove, and a gap is formed between one surface of the edge part of the passivation fault, which is close to the substrate, and the bottom of the groove.

In some embodiments, the display panel further includes a light emitting layer on a side of the anode layer remote from the substrate, the light emitting layer including a light emitting portion located within the pixel opening; the cathode layer is positioned on one side of the light-emitting layer and the pixel defining layer away from the substrate; the display panel further includes a first carrier common layer between the anode layer and the light emitting layer, and/or a second carrier common layer between the light emitting layer and the cathode layer; the first carrier common layer and/or the second carrier common layer is/are located in the groove and is/are disconnected at the edge portion of the passivation fault extending out, and the cathode layer is/are located in the groove and is/are disconnected at the edge portion of the passivation fault extending out.

In some embodiments, the light emitting layer includes a first light emitting layer, a connection layer, and a second light emitting layer that are sequentially stacked, the first light emitting layer being adjacent to the anode layer, a portion of the connection layer located in the groove being broken at an edge portion where the passivation layer protrudes.

In some embodiments, the display panel further includes a first encapsulation layer on a side of the cathode layer remote from the substrate; the second packaging layer is positioned on one side of the first packaging layer away from the substrate; the third packaging layer is positioned on one side of the second packaging layer far away from the substrate; the boundary of the second packaging layer is positioned at one side of the first blocking dam close to the display area, and the first packaging layer and the third packaging layer cover the display area and the peripheral area.

In some embodiments, the material of the first passivation layer is silicon nitride, and the thickness is 2500 to 3000 angstroms.

In some embodiments, the material of the second passivation layer is silicon nitride, and the thickness is 500 to 2500 angstroms.

Some embodiments of the present disclosure also provide a display device including the display panel described above.

Some embodiments of the present disclosure apply the display panel described above to a display device, reducing the probability of small black spots occurring in the display area of the display device.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic diagrams, not limiting the actual size of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure.

FIG. 1 is a plan view of a display panel in some embodiments;

FIG. 2 is a cross-sectional view taken along section line C-C of FIG. 1;

FIG. 3 is another cross-sectional view taken along section line C-C of FIG. 1;

FIG. 4A is a plan view of a display panel in some embodiments of the present disclosure;

FIG. 4B is a signal trace plan view of a left bezel area of a display panel according to some embodiments of the present disclosure;

FIG. 5 is a plan view of the film structure of the second peripheral region of FIG. 4A;

FIG. 6 is a cross-sectional view taken along section line D-D in FIG. 5;

FIG. 7 is a cross-sectional view taken along section line E-E in FIG. 4A;

FIG. 8 is a cross-sectional view taken along section line F-F in FIG. 4A;

Fig. 9 is an enlarged view of the groove location of fig. 8.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "examples," "particular examples," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present between the layer or element and the other layer or substrate.

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

As shown in fig. 1, the display panel 100 includes a display area AA and a peripheral area BB disposed around the display area AA, and a barrier Dam is disposed around the display area AA and located in the peripheral area BB; in some embodiments, the film layer of the display panel 100 includes a substrate, an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer dielectric layer, a first source drain metal layer, a first passivation layer, a first planarization layer, a second source drain metal layer, a second planarization layer, a second passivation layer, an anode layer, a pixel defining layer, a light emitting layer, a cathode layer, and an encapsulation layer, which are sequentially stacked on one side of the substrate. Some of the films are continuous whole laid films, some of the films are patterned films, some of the films are only positioned in the display area AA, some of the films extend from the display area AA to the peripheral area BB, some of the films comprise a part positioned in the display area AA and a part positioned in the peripheral area BB, and the two parts are separated; the substrate is used as a base layer for bearing all the film layers, and the orthographic projection boundaries of the film layers on the substrate are different.

As shown in fig. 2, fig. 2 is a cross-sectional view taken along a section line CC in fig. 1, and fig. 2 only shows the structure related to the first source drain metal layer, but not all the layers provided in the peripheral region. In some examples, the film layer disposed in the peripheral area BB of the display panel 100 is: the display device comprises a substrate 1, a first source drain metal layer SD1 arranged on one side of the substrate 1, and a first passivation layer PVX1 arranged on one side of the first source drain metal layer SD1 far away from the substrate 1, wherein in a peripheral area BB, the first passivation layer PVX1 is positioned on one side of a barrier Dam far away from a display area AA, namely, the first passivation layer PVX1 is positioned on the periphery of the barrier Dam, and the barrier Dam is arranged on one side of the first source drain metal layer SD1 far away from the substrate 1.

In preparing each film layer of the display panel 100, for example, the portion of the first source drain metal layer SD1 in the peripheral area BB extends to the side of the barrier Dam away from the display area AA, the portion of the first source drain metal layer SD1 extending to the side of the barrier Dam away from the display area AA is provided with the first passivation layer PVX1 in a stacked manner on the side of the barrier Dam away from the display area AA, and the first passivation layer PVX1 covers the portion of the first source drain metal layer SD1 extending to the side of the barrier Dam away from the display area AA. When preparing a subsequent film layer, for example, when preparing the second source-drain metal layer SD2 and/or the second passivation layer PVX2, patterning the second source-drain metal layer SD2 and/or the second passivation layer PVX2 is needed, etching off a portion of the second source-drain metal layer SD2 and/or the second passivation layer PVX2, which is located on a side of the barrier Dam away from the display area AA, where during etching, over etching is easily performed on the first passivation layer PVX1, which is located on a side of the barrier Dam away from the display area AA, so that the barrier Dam covered by the first passivation layer PVX1 is exposed from the first source-drain metal layer SD1, where the material of the first source-drain metal layer SD1 is, for example, a titanium-aluminum-titanium (Ti-AL-Ti) film layer, which is stacked; when the anode layer Ano of the display panel 100 is prepared, for example, silver is used as an anode material, in the process of etching the anode layer Ano pattern, because the first source drain metal layer SD1 is exposed, aluminum ions of the first source drain metal layer SD1 are separated out in etching solution and enter into the etching solution, and the aluminum ions of the first source drain metal layer SD1 reach the anode layer Ano of the display area AA of the display panel 100 along with the etching solution, and silver ions of the anode layer Ano are replaced with aluminum ions of the first source drain metal layer SD1 in the etching solution and are separated out on the anode surface, so that small black spots appear on the anode surface of the display panel 100, and the display effect of the display panel 100 is affected.

Based on this, as shown in fig. 1 and 3, some embodiments of the present disclosure provide a display panel 100 including a display area AA and a peripheral area BB located around the display area AA, the peripheral area BB including a first peripheral area BB1 and a second peripheral area BB2, the second peripheral area BB2 including a bonding area BB2-2. The display panel 100 includes: the display device comprises a substrate 1, a first source drain metal layer SD1 arranged on one side of the substrate 1, a first passivation layer PVX1 arranged on one side of the first source drain metal layer SD1 far away from the substrate 1, and a barrier Dam arranged on one side of the first passivation layer PVX1 far away from the substrate 1, wherein the barrier Dam is positioned in a peripheral area BB and surrounds a display area AA; the first source-drain metal layer SD1 extends to the first peripheral region BB1 and to a side of the barrier Dam away from the display region AA; the first passivation layer PVX1 comprises a first portion PVX1-1 located in the first peripheral region BB1, and the first portion PVX1-1 of the first passivation layer covers a portion of the first source drain metal layer SD1 located at one side of the barrier Dam away from the display region AA; the display panel 100 further includes: the second passivation layer PVX2, the second passivation layer PVX2 is located at a side of the first passivation layer PVX1 away from the substrate 1, and includes a first portion PVX2-1 located at the first peripheral region BB1, and the first portion PVX2-1 of the second passivation layer covers a portion of the first portion PVX1-1 of the first passivation layer located at a side of the barrier Dam away from the display region AA.

As shown in fig. 1, the display panel 100 includes a display area AA, the display area AA of the display panel 100 includes a plurality of sub-pixels, for example, arranged in an array, the sub-pixels are the smallest units of the display panel 100 for displaying a picture, each sub-pixel may display a single color, for example, red (R), green (G) or blue (B), each sub-pixel includes a light emitting device and a pixel driving circuit for driving the light emitting device to emit light, and the pixel driving circuit may be electrically connected by a plurality of TFTs (thin film transistors) and Cst (storage capacitors). In each sub-pixel, the light emitting device is electrically connected to a corresponding pixel driving circuit below, specifically, an anode of the light emitting device is electrically connected to the corresponding pixel driving circuit, so that an anode voltage inputted into the display panel 100 is transmitted to the anode of the light emitting device through the pixel driving circuit, and at the same time, a cathode voltage is transmitted to a cathode of the light emitting device, thereby forming an electric field between the anode and the cathode, and driving the light emitting device to emit light.

Illustratively, as shown in fig. 1, the display panel 100 includes a peripheral area BB located around the display area AA, the peripheral area BB may include a first peripheral area BB1 and a second peripheral area BB2, the first peripheral area BB1 may include at least one of an upper frame area, a left frame area, and a right frame area of the display panel 100, the second peripheral area BB2 may include a lower frame area of the display panel 100, and illustratively, the left frame area and the right frame area of the display panel 100 are disposed opposite to each other in a first direction X, the upper frame area and the lower frame area are disposed opposite to each other in a second direction Y, and the first direction X and the second direction Y intersect; the first direction X is, for example, a row direction in which a plurality of sub-pixels are arranged, and the second direction Y is, for example, a column direction in which a plurality of sub-pixels are arranged, and the first direction X and the second direction Y are perpendicular. The second peripheral area BB2, for example, the lower frame area may include an electrode bending area BB2-1 and a binding area BB2-2, and the binding area BB2-2 may be used for binding a flexible circuit board and is folded to the back of the display panel 100 through the electrode bending area BB2-1, so that the width of the second peripheral area BB2, for example, the lower frame area is reduced, and the requirement of the current display panel 100 for a narrow frame is met.

Illustratively, as shown in fig. 3, at a first peripheral region BB1 of the display panel 100, for example, an upper bezel region, a left bezel region, a right bezel region of the display panel 100, the display panel 100 is provided with: the substrate 1, the first source drain metal layer SD1 arranged on one side of the substrate 1, the first part PVX1-1 of the first passivation layer arranged on one side of the first source drain metal layer SD1 far away from the substrate 1, the barrier Dam arranged on one side of the first part of the first passivation layer PVX1 far away from the substrate 1, and the first part PVX2-1 of the second passivation layer arranged on one side of the first part of the first passivation layer PVX1 far away from the substrate 1.

It should be noted that, the film layer stack in the peripheral area BB of the display panel 100 is different from the film layer stack in the display area AA, the display area AA of the display panel 100 performs the image display, the film layer stack in the display area AA may include the film layer stack of the pixel driving circuit of each sub-pixel and the film layer stack of the light emitting device corresponding to the pixel driving circuit, the peripheral area BB of the display panel 100 does not need to perform the image display, and may be used to arrange a plurality of signal traces, and the film layer stack in the peripheral area BB may include the film layer stack of the plurality of signal traces.

Illustratively, at the first peripheral area BB1 of the display panel 100, for example, the upper frame area, the left frame area, and the right frame area of the display panel 100, the substrate 1 may be a base of stacking the film layers of the display panel 100, and the substrate 1 may be rigid or flexible. The barrier Dam is disposed around the display area AA and located in the peripheral area BB, and is used for blocking overflow of the organic layer in the display area AA during the preparation process, and can effectively prevent corrosion of the film layer inside the display panel 100 caused by external water and oxygen.

Illustratively, at a first peripheral region BB1 of the display panel 100, for example, an upper frame region, a left frame region, and a right frame region of the display panel 100, the first source drain metal layer SD1 extends to a side of the barrier Dam away from the display region AA; the first source and drain metal layer SD1 in the first peripheral region BB1 may be used to dispose signal traces, the material of the first source and drain metal layer SD1 may be a composite material, for example, a titanium-aluminum-titanium (Ti-AL-Ti) composite material, the first portion PVX1-1 of the first passivation layer covers a portion of the first source and drain metal layer SD1 located at a side of the barrier Dam away from the display region AA, the first portion PVX1-1 of the first passivation layer is also located under the barrier Dam, and the first portion PVX2-1 of the second passivation layer covers a portion of the first portion PVX1-1 of the first passivation layer located at a side of the barrier Dam away from the display region AA.

In some embodiments of the present disclosure, in a first peripheral area BB1 of the display panel 100, for example, an upper frame area, a left frame area, and a right frame area of the display panel 100, by covering a first portion PVX1-1 of the first passivation layer with a portion of the first passivation layer located at a side of the barrier Dam away from the display area AA, and covering a first portion PVX1-1 of the second passivation layer with a portion of the first passivation layer PVX1-1 located at a side of the barrier Dam away from the display area AA, a double-layer protection is formed for a portion of the first source drain metal layer SD1 located at a side of the barrier Dam away from the display area AA, so that over-etching of a combined film layer formed by the first passivation layer PVX1 and the second passivation layer PVX2 during a patterning process of a subsequent film layer is effectively avoided, thereby avoiding bare-etching of the metal layer of the display panel 100, for example, the first source drain metal layer SD1, and a bare-black dot on the surface of the display panel 100 are reduced.

In some embodiments, as shown in fig. 3, the first portion PVX1-1 of the first passivation layer extends from the surface of the portion of the first source drain metal layer SD1 located at the side of the barrier Dam away from the display area AA onto the surface of the substrate 1, i.e., the first portion PVX1-1 of the first passivation layer covers the upper surface and the side surface of the portion of the first source drain metal layer SD1 located at the side of the barrier Dam away from the display area AA, and the end of the first portion PVX1-1 of the first passivation layer located at the side of the barrier Dam away from the display area AA extends onto the surface of the substrate 1, and the first passivation layer PVX1 contacts the substrate 1. The first portion PVX2-1 of the second passivation layer covers a portion of the first portion PVX1-1 of the first passivation layer on a side of the barrier Dam remote from the display area AA. Such setting is located the better cover of part that barrier Dam kept away from display area AA one side with first source drain metal layer SD1, prevents that the steam in the air from getting into display panel 100 and causing the corruption to the rete in the display panel 100, influences display panel 100's life, can prevent simultaneously better when preparing subsequent rete with the metal rete, for example first source drain metal layer SD1 naked hourglass, reduces display panel 100's the probability that little black spot appears on the positive pole surface.

In some embodiments, as shown in fig. 1 and 3, the barrier Dam includes a first barrier Dam1 and a second barrier Dam2, the second barrier Dam2 is distant from the display area AA with respect to the first barrier Dam1, the height of the second blocking Dam (Dam 2) is higher than that of the first blocking Dam (Dam 1), so that overflow of the relevant organic layers in the preparation process can be better blocked; the barrier Dam may be manufactured using other film layers in the display panel 100, simplifying the manufacturing process.

In some embodiments, as shown in fig. 5 and 6, the first source-drain metal layer SD1 extends to the second peripheral area BB2 and to a side of the second barrier Dam2 away from the display area AA; the first passivation layer PVX1 further includes a second portion PVX1-2 located in the second peripheral region BB2, the second portion PVX1-2 of the first passivation layer covering a portion of the first source drain metal layer SD1 located between the first barrier Dam1 and the second barrier Dam 2; the second passivation layer PVX2 further includes a second portion PVX2-2 located at the second peripheral region BB2, the second portion PVX2-2 of the second passivation layer covering a portion of the first passivation layer PVX1 located between the first barrier Dam1 and the second barrier Dam 2.

As shown in fig. 5, at a second peripheral area BB2 of the display panel 100, for example, a lower frame area of the display panel 100, the first source drain metal layer SD1 extends downward from the left and right frame areas of the display panel 100 to the lower frame area of the display panel 100, and the first source drain metal layer SD1 is divided into left and right portions at the lower frame area and extends to a side of the second barrier Dam2 away from the display area AA; the second portion PVX1-2 of the first passivation layer covers a portion of the first source drain metal layer SD1 located between the first barrier Dam1 and the second barrier Dam2, the second portion PVX2-2 of the second passivation layer covers a portion of the second portion PVX1-2 of the first passivation layer located between the first barrier Dam1 and the second barrier Dam2, double-layer protection is formed on the part of the first source drain metal layer SD1 located between the first blocking Dam1 and the second blocking Dam2, so that overetching of a combined film layer formed by the first passivation layer PVX1 and the second passivation layer PVX2 in the subsequent film layer patterning treatment process is effectively avoided, and the metal layer of the display panel 100, such as the bare drain of the first source drain metal layer SD1, is prevented, and the probability of occurrence of small black spots on the anode surface of the display panel 100 is reduced.

It should be noted that, the second peripheral area BB2 of the display panel 100, for example, the lower frame area of the display panel 100, the side of the second barrier Dam2 away from the display area AA includes an electrode bending area BB2-1 and a binding area BB2-2, and the binding area BB2-2 can be used for binding a flexible circuit board and folding the flexible circuit board to the back of the display panel 100 through the electrode bending area BB2-1, so as to meet the current requirement of the narrow frame of the display panel 100. At this time, the electrode bending region BB2-1 of the lower frame region of the display panel 100 needs to have better bending performance, because the first passivation layer PVX1 and the second passivation layer PVX2 are both made of inorganic materials and have higher hardness and strength, if the second portion PVX1-2 of the first passivation layer covers the first source/drain metal layer SD1 in the second peripheral region BB2 to the portion of the second barrier Dam2 far from the display region AA, the second portion PVX2-2 of the second passivation layer covers the second portion PVX1-2 of the first passivation layer to the portion of the second barrier Dam2 far from the display region AA, the side of the second barrier Dam2 far from the display region AA will have higher hardness and strength, and in the process of the electrode bending region BB2-1, a larger stress will be generally generated, which may cause damage to some film layers of the electrode bending region BB2-1, and therefore, in the lower frame region of the display panel 100, the second barrier Dam2 extends to the portion of the second barrier Dam2 far from the display region AA, the second barrier Dam2 usually covers the relevant film SD1 in the lower frame region 100, and the metal bending region SD1 is not guaranteed to be exposed.

In some embodiments, as shown in fig. 3, 4A, 5 and 6, fig. 3 may be a cross-sectional view taken according to a cross-sectional line CC in fig. 1, or may be a cross-sectional view taken according to a cross-sectional line EE in fig. 4A, and fig. 3 is intended to illustrate a positional relationship of the first source drain metal layer SD1, the first passivation layer PVX1, the second passivation layer PVX2 and the barrier Dam. The first source drain metal layer SD1 is located under the first barrier Dam1 and the second barrier Dam2, the first source drain metal layer SD1 includes a plurality of first voltage signal lines SD1-1 extending in the first direction X, the plurality of first voltage signal lines SD1-1 are located in the display area AA and extend to the first peripheral area BB1, and the plurality of first voltage signal lines SD1-1 extend between the first barrier Dam1 and the second barrier Dam2, for example. The first source/drain metal layer SD1 further includes a first voltage signal bus SD1-2, where the first voltage signal bus SD1-2 is located in the first peripheral region BB1, and the first voltage signal bus SD1-2 semi-surrounds the display region AA, that is, the first voltage signal bus SD1-2 is located in the upper frame region, the left frame region, and the right frame region, so as to surround the upper side, the left side, and the right side of the display region AA. The outer side of the first voltage signal bus SD1-2 is located at one side of the second barrier Dam2 away from the display area AA, and the first voltage signal bus SD1-2 is connected with a plurality of first voltage signal lines SD 1-1. The first source-drain metal layer SD1 further includes two first voltage signal connection lines SD1-3, the two first voltage signal connection lines SD1-3 are located in the second peripheral area BB2, and the two first voltage signal connection lines SD1-3 are connected to two ends of the first voltage signal bus SD1-2 respectively. The first voltage signal connection line SD1-3 extends from a side of the first barrier Dam1 near the display area AA to a side of the second barrier Dam2 far from the display area AA.

The first portion PVX1-1 of the first passivation layer covers a portion of the first voltage signal bus SD1-2 located at a side of the second barrier Dam2 remote from the display area AA, and the second portion PVX1-2 of the first passivation layer covers a portion of the first voltage signal connection line SD1-3 located between the first barrier Dam1 and the second barrier Dam 2; the first portion PVX2-1 and the second portion of the second passivation layer cover a portion of the first passivation layer PVX1 located in the peripheral region BB.

As illustrated in fig. 4A and 4B, the first source drain metal layer SD1 may be used to provide signal traces, for example, a portion of the first source drain metal layer SD1 located in the display area AA may be provided with a plurality of first voltage signal lines SD1-1 extending along a first direction X, for example, a lateral VSS signal line, the plurality of first voltage signal lines SD1-1 extending along the first direction X to the first peripheral area BB1, and the plurality of first voltage signal lines SD1-1 extending along the first direction X between a first barrier Dam1 and a second barrier Dam2 of the first peripheral area BB1, for example, the first voltage signal lines SD1-1 extending from the display area AA to the left and right frame areas. In the first peripheral area BB1, a first voltage signal bus SD1-2, for example, a VSS signal bus, may be disposed, and a plurality of first voltage signal lines SD1-1 are connected to the first voltage signal bus SD1-2, and the first voltage signal bus SD1-2 surrounds the display area AA in the first peripheral area BB1, for example, in the upper frame area, the left frame area, and the right frame area of the display panel 100, and illustratively, an inner side of the first voltage signal bus SD1-2 is located between the first barrier Dam1 and the second barrier Dam2, and an outer side of the first voltage signal bus SD1-2 is located on a side of the second barrier Dam2 away from the display area AA. The ends of the plurality of first voltage signal lines SD1-1 extending between the first barrier Dam1 and the second barrier Dam2 are connected to the inside of the first voltage signal bus lines SD 1-2. The first voltage signal bus SD1-2 extends to the edge of the second peripheral area BB2 along the second direction Y in the left frame area and the right frame area; in the second peripheral area BB2 of the display panel 100, the first source drain metal layer SD1 may be provided with two first voltage signal connection lines SD1-3, where the two first voltage signal connection lines SD1-3 are respectively connected to two ends of the first voltage signal bus SD1-2 extending from the left border area and the right border area to the edge of the second peripheral area BB2, and the two first voltage signal connection lines SD1-3 extend from one side of the first barrier Dam1 near the display area AA to one side of the second barrier Dam2 far from the display area AA along the second direction Y, that is, the orthographic projection of the first voltage signal connection line SD1-3 on the substrate 1 sequentially spans the orthographic projections of the first barrier Dam1 and the second barrier Dam2 on the substrate 1.

Illustratively, as shown in fig. 3, in the first peripheral area BB1, the first portion PVX1-1 of the first passivation layer covers a portion of the first voltage signal bus SD1-2 located on a side of the second barrier Dam2 away from the display area AA; the first portion PVX2-1 of the second passivation layer covers a portion of the first portion PVX1-1 of the first passivation layer extending to a side of the second barrier Dam2 remote from the display area AA.

Illustratively, as shown in fig. 6, in the second peripheral region BB2, the second portion PVX1-2 of the first passivation layer covers the portions of the two first voltage signal connection lines SD1-3 of the first source-drain metal layer SD1 between the first barrier Dam1 and the second barrier Dam 2; the second portion PVX2-2 of the second passivation layer covers a portion of the second portion of the first passivation located between the first barrier Dam1 and the second barrier Dam 2.

In some embodiments, as shown in fig. 7, the display panel 100 further includes a second source-drain metal layer SD2 between the first passivation layer PVX1 and the second passivation layer PVX2, the second source-drain metal layer SD2 extending to a side of the second barrier Dam2 near the display area AA, the second source-drain metal layer SD2 being connected to the first source-drain metal layer SD1 at the peripheral area BB; the display panel 100 further includes an anode layer Ano located at a side of the second passivation layer PVX2 away from the substrate 1, the anode layer Ano includes a lap anode Ano-1 located at the peripheral region BB, and the lap anode Ano-1 is connected to a portion of the second source drain metal layer SD2 extending to a side of the second barrier Dam2 near the display region AA; the display panel 100 further includes a cathode layer Cad located on a side of the anode layer Ano remote from the substrate 1, and overlapping the anode Ano-1 is connected to a portion of the cathode layer Cad located in the peripheral region BB.

Illustratively, as shown in fig. 7, in the first peripheral area BB1 of the display panel 100, there are laminated in order from bottom to top: the substrate 11, the buffer layer 12, the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer dielectric layer ILD, the first source drain metal layer SD1, the first passivation layer first part PVX1-1, the first flat layer PLN1, the second source drain metal layer SD2, the second flat layer PLN2, the second passivation layer first part PVX2-1, the overlap anode Ano-1, the pixel defining layer PDL, the spacer PS, the cathode layer Cad and the encapsulation layer TFE, wherein the substrate 11, the buffer layer 12, the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer dielectric layer ILD form a base 1, the first barrier Dam1 is made of the pixel defining layer PDL and the spacer PS, the second barrier Dam2 is made of the first flat layer PLN1, the second flat layer PLN2, the pixel defining layer PDL and the spacer PS, the first barrier Dam1 and the second barrier Dam2 may be made of other film layers, for example, the first barrier Dam1 is formed by the second flat layer PLN2 and the pixel defining layer PDL, and the second barrier Dam2 is formed by the first flat layer PLN1, the second flat layer PLN2 and the pixel defining layer PDL, which are not limited herein.

The second source-drain metal layer SD2 may be used to provide signal traces, for example, the second source-drain metal layer SD2 includes a longitudinal first voltage signal line SD2-1 extending along the second direction Y, for example, a longitudinal VSS signal line, and a plurality of signal lines of the second source-drain metal layer SD2 extend from the display area AA to the peripheral area BB along the second direction. In the peripheral area BB, the second source drain metal layer SD2 extends to one side of the second barrier Dam2 close to the display area AA, the second source drain metal layer SD2 is connected with the part of the first source drain metal layer SD1 on one side of the second barrier Dam2 close to the display area AA, as shown in FIG. 4A, the longitudinal first voltage signal line SD2-1 extends to one side of the second barrier Dam2 close to the display area AA in the upper frame area, and is connected with the first voltage signal bus SD1-2 through a via hole; the longitudinal first voltage signal line SD2-1 also extends to a side of the second barrier Dam2 in the lower frame area near the display area AA, and is connected to the first voltage signal connection line SD1-3 (VSS signal connection line) through a via hole.

In some embodiments, the longitudinal first voltage signal lines SD2-1 are further disposed in the left frame region and the right frame region of the first peripheral region BB1, and illustratively, the longitudinal first voltage signal lines SD2-1 are located between the first barrier Dam1 and the second barrier Dam2, and the ends of one longitudinal first voltage signal line SD2-1 extending to the left frame region or the right frame region with the plurality of first voltage signal lines SD1-1 are connected through vias. In other embodiments, the plurality of longitudinal first voltage signal lines SD2-1 and the plurality of first voltage signal lines SD1-1 are disposed to cross each other in the display area AA, and at the overlapping position of the two, the longitudinal first voltage signal lines SD2-1 and the first voltage signal lines SD1-1 are connected through vias.

Through the arrangement, the second source drain metal layer SD2 and the first source drain metal layer SD1 are connected in the peripheral area BB/the display area AA, a net-shaped voltage signal transmission net can be formed between the first source drain metal layer SD1 and the second source drain metal layer SD2, so that a first voltage signal can be transmitted to a plurality of first voltage signal lines SD1-1 through the first voltage signal bus SD1-2 and transmitted to a plurality of longitudinal first voltage signal lines SD2-1, the layer change transmission of a first voltage signal (VSS) is realized, and the subsequent VSS signal can be transmitted to a cathode layer conveniently. Meanwhile, the arrangement is favorable for reducing the resistance of the signal wire, reducing the loss of signal transmission and improving the uniformity of signals.

Illustratively, the anode layer Ano of the display panel 100 includes a plurality of anodes Ano-2 located in the display area AA and a bridging anode Ano-1 located in the first peripheral area BB1 of the display panel 100, the plurality of anodes Ano-2 and the bridging anode Ano-1 are arranged in the same layer, the bridging anode Ano-1 is disconnected from the anode Ano-2 of the display area AA of the display panel 100, and functions independently, the cathode layer Cad of the display panel 100 is a continuous film layer laid over the entire display area AA and the peripheral area BB, as shown in FIG. 7, the boundary of the cathode layer Cad is closer to the edge of the display panel 100 than the boundary of the pixel defining layer PDL, and the edge portion of the cathode layer Cad is in contact with the bridging anode Ano-1. The overlap anode Ano-1 is used for connecting the second source drain metal layer SD2 and the cathode layer Cad, i.e. the overlap anode Ano-1 is connected with the portion of the second source drain metal layer SD2 extending to the side of the second barrier Dam2 near the display area AA, the overlap anode Ano-1 is connected with the portion of the cathode layer Cad extending to the first peripheral area BB1, therefore, the signal transmitted by the second source drain metal layer SD2 is transmitted to the cathode layer Cad located in the peripheral area BB through the overlap anode Ano-1, and the cathode layer Cad located in the display area AA is connected to the voltage signal, and through such a structure, the electrical connection between the cathode layer Cad in the display area AA of the display panel 100 and the VSS signal lines of the first source drain metal layer SD1 and the second source drain metal layer SD2 in the first peripheral area BB1 is realized.

It should be noted that, in other embodiments, the boundary of the cathode layer Cad may be close to the display area AA relative to the boundary of the pixel defining layer PDL, the cathode layer Cad need not extend to a position directly contacting the overlap anode Ano-1, and the cathode layer Cad may pass through a via in the pixel defining layer PDL to connect with the overlap anode Ano-1, so as to electrically connect the cathode layer Cad of the display area AA of the display panel 100 with the VSS signal lines of the first source-drain metal layer SD1 and the second source-drain metal layer SD2 of the first peripheral area BB 1. Therefore, the manner of enabling the cathode layer Cad of the display area AA of the display panel 100 to be connected to the VSS signal lines of the first source-drain metal layer SD1 and the second source-drain metal layer SD2 of the first peripheral area BB1 falls within the scope of some embodiments of the present disclosure, which is not exemplified herein.

Meanwhile, the signal traces in the peripheral area BB of the display panel 100 may be set to different schemes according to specific situations, for example, the VSS signal lines may be set only in the first source drain metal layer SD1, or may be set in the first source drain metal layer SD1, the second source drain metal layer SD2, and the third source drain metal layer, and the first source drain metal layer SD1 may be set only with the VSS signal lines, or may be set with other signal lines, for example, the VDD signal lines, etc., so some embodiments of the disclosure are not limited too much herein, and the setting schemes of the various signal lines fall within the protection scope of some embodiments of the disclosure.

In some embodiments, as shown in fig. 8, the display panel 100 further includes a first flat layer PLN1 located on a side of the first passivation layer PVX1 away from the substrate 1, where the first flat layer PLN1 is located at least in the display area AA; the second source-drain metal layer SD2 is located at a side of the first planar layer PLN1 away from the substrate 1; the display panel 100 further includes a second flat layer PLN2 located on a side of the second source-drain metal layer SD2 away from the substrate 1, where the second flat layer PLN2 is located at least in the display area AA; the second passivation layer PVX2 is positioned on the side, away from the substrate 1, of the second flat layer PLN2, the second passivation layer PVX2 also comprises a third part PVX2-3 positioned in the display area AA, and the third part PVX2-3 of the second passivation layer comprises at least one passivation layer PVX2-31; the anode layer Ano further comprises at least one anode Ano-2 positioned in the display area AA, and the orthographic projection of the anode Ano-2 on the substrate 1 is positioned in the orthographic projection of the passivation fault PVX2-31 on the substrate 1; the display panel 100 further includes a pixel defining layer PDL located on a side of the anode layer Ano remote from the substrate 1, the pixel defining layer PDL including at least one pixel opening PDL-1; the pixel opening PDL-1 is arranged corresponding to the anode Ano-2; the display panel 100 includes a groove 4 penetrated from the pixel defining layer PDL to the second flat layer PLN2, the groove 4 being located at least one side of the pixel opening PDL-1; the edge portion pv2 of the passivation layer PVX2-31 protrudes from the side wall of the groove 4, and a gap 41 is provided between the side of the passivation layer PVX2-31, which is close to the substrate 1, and the bottom of the groove 4.

Illustratively, as shown in fig. 8, in the display area AA of the display panel 100, there are laminated in order from bottom to top: the substrate 11, the buffer layer 12, the active layer ACT, the first Gate insulating layer GI1, the first Gate metal layer Gate1, the second Gate insulating layer GI2, the second Gate metal layer Gate2, the interlayer dielectric layer ILD, the first source drain metal layer SD1, the first passivation layer third portion PVX1-3, the first flat layer PLN1, the second source drain metal layer SD2, the second flat layer PLN2, the second passivation layer third portion PVX2-3, the anode layer Ano, the pixel defining layer PDL, the light emitting layer EL, the spacer PS, the cathode layer Cad, and the encapsulation layer TFE, wherein the substrate 11, the buffer layer 12, the first Gate insulating layer GI1, the second Gate insulating layer GI2, the interlayer dielectric layer ILD constitute the substrate 1, the anode layer Ano, the pixel defining layer, the light emitting layer EL, and the cathode layer Cad are collectively referred to as light emitting device layers 3, the light emitting device layers 3 include at least one light emitting device, that is, the pixel defining layer includes at least one pixel opening PDL-1, the anode layer Ano includes at least one anode layer Ano-2 is disposed in the at least one pixel opening PDL-1, and the anode layer Ano-2 is disposed in the at least one pixel opening 1-EL-1 corresponding to the at least one light emitting layer 1 opening 1-EL-1.

The third portion PVX2-3 of the second passivation layer comprises a plurality of passivation faults PVX2-31, the orthographic projection of one anode Ano-2 on the substrate 1 is located within the orthographic projection of one passivation fault PVX2-31 on the substrate 1, i.e. one anode Ano-2 is located at a side of one passivation fault PVX2-31 remote from the substrate 1, and the boundary of the passivation fault PVX2-31 extends outwards with respect to the boundary of the anode Ano-2. By providing this, the anode can be formed on a flat surface, and the flatness of the anode can be improved.

The display panel 100 includes a groove 4 in which the pixel defining layer PDL penetrates to the second flat layer PLN2, the groove 4 being located at least one side of the pixel opening PDL-1; the edge portion pv2 of the passivation layer PVX2-31 protrudes from the side wall of the recess 4, i.e. the recess 4 exposes the protruding edge portion pv2 of the passivation layer PVX2-31, and a gap 41 is provided between the side of the protruding edge portion pv2 of the passivation layer PVX2-31 close to the substrate 1 and the bottom of the recess 4.

In the process of manufacturing the groove 4, since the pixel defining layer PDL and the second flat layer PLN2 are both organic film layers, for example, a photolithography process may be used to manufacture the groove in the pixel defining layer PDL and the second flat layer PLN2, the passivation layer PVX2-31 is an inorganic film layer, during the process of manufacturing the groove 4, the pixel defining layer PDL and the second flat layer PLN2 are removed to expose the edge portion pv2 of the passivation layer PVX2-31, the inorganic film layer is not removed by the photolithography process, so that the edge portion pv2 of the passivation layer PVX2-31 is retained in the groove 4, the developing solution reacts with the material of the second flat layer PLN2 around the edge portion pv2 of the passivation layer PVX2-31, that is, the developing solution reacts with the material of the second flat layer PLN2 located at the side of and below the edge portion pv2 of the passivation layer PVX2-31 until etching to a set depth, and finally, a gap 41 is formed between the side of the edge portion pv2 of the third portion PVX2-3 of the second passivation layer, which is close to the substrate 1, and the bottom of the groove 4, as shown in fig. 9, and from the structure of the groove 4 finally obtained, the side wall of the groove 4 is composed of the pixel defining layer PDL and the second flat layer PLN2, the bottom of the groove 4 is composed of the second flat layer PLN2, and the edge portion pv2 of the passivation layer PVX2-31 protrudes from the side wall of the groove 4, which can be understood as a portion of the passivation layer PVX2-31 protruding inside the groove 4.

The steps for preparing the groove by adopting the photoetching technology are as follows:

s1, placing a mask on one side of the pixel defining layer PDL far away from the substrate 1, and exposing the pixel defining layer PDL and the second flat layer PLN 2.

For example, the mask includes an opening exposing an area of the pixel defining layer PDL where the groove 4 is to be formed, and the area of the pixel defining layer PDL and the second flat layer PLN2 exposed by the opening is exposed by means of optical irradiation.

S2, forming grooves 4 in the pixel defining layer PDL and the second flat layer PLN2 using a developing solution.

The exposed portions of the pixel defining layer PDL and the second flat layer PLN2 are removed by a developing solution, and the unexposed portions remain, and during the developing process, the developing solution does not etch the edge portion pv2 of the passivation layer PVX2-31, and side etching may be caused on the side of the edge portion pv2 of the passivation layer PVX2-31 near the substrate 1 (below the passivation layer PVX 2-31), thereby forming a gap 41 between the side of the edge portion pv2 of the passivation layer PVX2-31 near the substrate 1 and the bottom of the groove 4. The etching depth of the second flat layer PLN2 is controlled by controlling the duration of the developing process.

In some embodiments, the display panel 100 further includes a light emitting layer EL located at a side of the anode layer Ano remote from the substrate 1, the light emitting layer EL including a light emitting portion EL1 located within the pixel opening; the cathode layer Cad is located on the side of the light-emitting layer EL and the pixel defining layer PDL away from the substrate 1; the display panel 100 further includes a first carrier common layer between the anode layer Ano and the light emitting layer EL, and/or a second carrier common layer between the light emitting layer EL and the cathode layer Cad; the portion of the first carrier common layer and/or the second carrier common layer located in the groove 4 is broken at the edge portion pv2 where the passivation layer PVX2-31 protrudes, and the portion of the cathode layer Cad located in the groove 4 is broken at the edge portion pv2 where the passivation layer PVX2-31 protrudes.

The light emitting device layer 3 includes an anode layer Ano and a cathode layer Cad, and a light emitting layer EL interposed between the anode layer Ano and the cathode layer Cad, and a first carrier common layer, such as at least one of a hole injection layer, a hole transport layer, and an electron blocking layer, located between the anode layer Ano and the light emitting layer EL, and/or a second carrier common layer, such as at least one of an electron injection layer, an electron transport layer, and a hole blocking layer, located between the light emitting layer EL and the cathode layer Cad, in the display panel 100, since materials of the light emitting layers of the sub-pixels of different colors are different, the light emitting layers EL of different colors are generally manufactured respectively using high-precision metal masks; unlike the process of producing the light-emitting layer EL, the film layers between the anode layer Ano and the light-emitting layer EL and between the cathode layer Cad and the light-emitting layer EL are of a full-layer communication structure, i.e., the film layers between the anode layer Ano and the light-emitting layer EL and between the cathode layer Cad and the light-emitting layer EL in the different color sub-pixels are common, and are usually produced in full layers. A voltage is applied to the anode and the cathode to generate an electric field between the anode and the cathode, so that holes in the anode and electrons in the cathode can be driven to recombine in the light emitting layer, thereby causing the display panel 100 to emit light.

Because the first carrier common layer, the second carrier common layer and the cathode layer Cad are made of the whole layer, a gap 41 is formed between one surface of the edge part pv2 of the passivation layer PVX2-31, which is close to the substrate 1, and the bottom of the groove 4 at the position of the groove 4, that is, the edge part pv2 of the passivation layer PVX2-31 protrudes in the groove 4, the first carrier common layer and/or the second carrier common layer is disconnected at the position, the cathode layer Cad is also disconnected at the position, the crosstalk of light emitted between two adjacent pixels is prevented, and the display effect is improved.

In some embodiments, the light emitting layer EL includes a first light emitting layer, a connection layer, and a second light emitting layer, which are sequentially stacked, the first light emitting layer being adjacent to the anode layer Ano, and a portion of the connection layer located within the groove 4 being broken at an edge portion pv2 where the passivation layer PVX2-31 protrudes. The first light-emitting layer and the second light-emitting layer are connected together through an intermediate connecting layer, such as a charge generation layer, to form a serial light-emitting device, so as to form a display panel 100, and compared with the conventional display panel 100, the serial display panel 100 has extremely high current light-emitting power efficiency, and the current light-emitting power efficiency can be increased in multiples along with the number of the serial light-emitting layers; at the same current density, the tandem display panel 100 is similar to the aging mechanism of the conventional display panel 100, but since the initial luminance of the tandem display panel 100 can become very large at a very small driving current, the lifetime of the tandem display panel 100 is much longer than that of the conventional display panel 100 if converted to the same initial luminance. The number of the tandem light emitting layers is not limited to 2, and a plurality of tandem light emitting layers may be provided, and the number of the tandem light emitting layers is not limited here.

In some embodiments, as shown in fig. 1, 7 and 8, the display panel 100 further includes a first encapsulation layer TFE1 located on a side of the cathode layer Cad away from the substrate 1; a second encapsulation layer TFE2 located on a side of the first encapsulation layer TFE1 remote from the substrate 1; a third encapsulation layer TFE3 located on a side of the second encapsulation layer TFE2 remote from the substrate 1; the boundary of the second encapsulation layer TFE2 is located at one side of the first barrier Dam1 near the display area AA, and the first encapsulation layer TFE1 and the third encapsulation layer TFE3 cover the display area AA and the peripheral area BB. The encapsulation layer TFE covers the side of the light emitting device layer 3 away from the substrate 1, and encapsulates the display panel 100, so as to prevent moisture and oxygen in the external environment from entering the display panel 100, and damage the organic material in the light emitting device layer 3, thereby shortening the lifetime of the display panel 100.

As shown in fig. 7 and 8, the common packaging technologies include cover plate packaging, laser glass packaging, surface packaging and film packaging, where the film packaging is exemplified by film packaging, and the packaged films are divided into a first packaging layer TFE1, a second packaging layer TFE2 and a third packaging layer TFE3, where the materials of the first packaging layer TFE1 and the third packaging layer TFE3 are inorganic materials, and the preparation process generally adopts a plasma chemical vapor deposition process, and the materials and the preparation process determine that the inorganic film is a film with uniform film thickness; the material of the second encapsulation layer TFE2 is an organic material, and has fluidity, and the preparation process generally adopts an inkjet printing process, and the material and the preparation process determine that the second encapsulation layer TFE2 is a thin film with a flat surface and uneven film thickness. The barrier Dam is used to block the related organic layers, such as the second encapsulation layer TFE2 from overflowing during the preparation process, so that the boundary of the second encapsulation layer TFE2 may be located at one side of the first barrier Dam1 near the display area AA, the inorganic materials of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may better avoid the moisture and oxygen in the external environment from entering the display panel 100, and the boundary of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may extend to the edge of the cutting groove to cover the display area AA and the peripheral area BB of the display panel 100.

As shown in fig. 1, fig. 4A and fig. 7, at least one cutting groove Slit is disposed at the edge of the display panel 100 near the boundary of the display panel 100, the cutting groove Slit is disposed around the display area and is located at the periphery of the barrier Dam, and is also located at the periphery of the encapsulation layer, at least one groove is formed at the boundary of the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer dielectric layer ILD, a first flat layer PLN1 is formed on the surface of the edge of the interlayer dielectric layer ILD, the first flat layer PLN1 is embedded in the grooves of the first gate insulating layer GI1, the second gate insulating layer GI2 and the interlayer dielectric layer ILD, and at least one cutting groove Slit is made, and the number of the cutting grooves Slit may be determined according to the need, which is not limited herein; the side that many cutting groove Slit kept away from substrate 11 sets up pixel definition layer PDL, and cutting groove Slit utilizes the organic layer, for example first flat layer PLN1 preparation, and the side that many cutting groove Slit kept away from substrate 11 sets up pixel definition layer PDL, can effectively utilize the buffer performance of organic layer, produces stress when preventing the cutting, damages display panel 100.

In some embodiments, the material of the first passivation layer PVX1 is silicon nitride, and the thickness is 2500 to 3000 angstroms; the second passivation layer PVX2 is made of silicon nitride and has a thickness of 500-2500 angstroms. The thickness range prevents the first passivation layer PVX1 and the second passivation layer PVX2 from being excessively etched to cause bare leakage of the metal film layers such as the first source drain metal layer SD1 below the first passivation layer PVX1 and the second passivation layer PVX2 in the process of manufacturing the display panel 100, and ensures the thinning requirement of the display panel 100.

Some embodiments of the present disclosure also provide a display device including the display panel 100 described above. By applying the display panel 100 described above to a display device such as a mobile phone, a tablet, a computer, a television, etc., the probability of occurrence of small black spots in the display area of the display device is reduced.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art who is skilled in the art will recognize that changes or substitutions are within the technical scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A display panel comprising a display area and a peripheral area surrounding the display area, the peripheral area comprising a first peripheral area and a second peripheral area, the second peripheral area comprising a binding area;

The display panel includes:

a substrate;

the first source-drain metal layer is arranged on one side of the substrate;

The first passivation layer is arranged on one side of the first source drain metal layer, which is far away from the substrate;

The blocking dam is arranged on one side, far away from the substrate, of the first passivation layer, is positioned in the peripheral area and is arranged around the display area; the first source drain metal layer extends to the first peripheral region and extends to one side of the barrier dam away from the display region; the first passivation layer comprises a first part positioned in the first peripheral region, and the first part of the first passivation layer covers a part of the first source drain metal layer, which is positioned at one side of the barrier dam, which is far away from the display region;

The display panel further includes: and the second passivation layer is positioned on one side of the first passivation layer away from the substrate and comprises a first part positioned in the first peripheral region, and the first part of the second passivation layer covers the part, positioned on one side of the barrier dam away from the display region, of the first part of the first passivation layer.

2. The display panel of claim 1, wherein a first portion of the first passivation layer extends from a surface of a portion of the first source drain metal layer on a side of the barrier dam remote from the display region to the substrate surface.

3. The display panel of claim 1, wherein the barrier dam comprises a first barrier dam and a second barrier dam, the second barrier dam being remote from the display area relative to the first barrier dam.

4. The display panel of claim 3, wherein the first source drain metal layer extends to a second peripheral region and to a side of the second barrier dam away from the display region;

the first passivation layer further comprises a second portion located in the second peripheral region, and the second portion of the first passivation layer covers a portion of the first source drain metal layer located between the first barrier dam and the second barrier dam;

The second passivation layer further includes a second portion located at the second peripheral region, the second portion of the second passivation layer covering a portion of the first passivation layer located between the first barrier dam and the second barrier dam.

5. The display panel of claim 4, wherein the first source drain metal layer includes a plurality of first voltage signal lines extending in a first direction, the plurality of first voltage signal lines being located in the display region and extending to the first peripheral region;

The first source drain metal layer further comprises a first voltage signal bus, the first voltage signal bus is located in the first peripheral area, the first voltage signal bus semi-surrounds the display area, the outer side of the first voltage signal bus is located at one side, far away from the display area, of the second barrier dam, and the first voltage signal bus is connected with the plurality of first voltage signal lines;

The first source-drain metal layer further comprises two first voltage signal connecting wires, the two first voltage signal connecting wires are located in the second peripheral area, and the two first voltage signal connecting wires are respectively connected with two ends of the first voltage signal bus; the first voltage signal connecting line extends from one side of the first barrier dam close to the display area to one side of the second barrier dam away from the display area;

a first part of the first passivation layer covers a part of the first voltage signal bus line, which is positioned at one side of the second barrier dam away from the display area, and a second part of the first passivation layer covers a part of the first voltage signal connection line, which is positioned between the first barrier dam and the second barrier dam;

the first portion and the second portion of the second passivation layer cover a portion of the first passivation layer located in the peripheral region.

6. The display panel of claim 3, further comprising: a second source drain metal layer located between the first passivation layer and the second passivation layer, the second source drain metal layer extending to a side of the second barrier dam adjacent to the display region; the second source drain metal layer is connected with the first source drain metal layer in the peripheral area;

an anode layer positioned on one side of the second passivation layer away from the substrate; the anode layer comprises a lap anode positioned in the peripheral area, and the lap anode is connected with a part of the second source-drain metal layer extending to one side of the second barrier dam close to the display area;

a cathode layer located on a side of the anode layer remote from the substrate; the overlap anode is connected to a portion of the cathode layer located in the peripheral region.

7. The display panel of claim 6, further comprising:

The first flat layer is positioned on one side of the first passivation layer away from the substrate, and the first flat layer is at least positioned in the display area; the second source-drain metal layer is positioned on one side of the first flat layer away from the substrate;

the second flat layer is positioned on one side of the second source drain metal layer away from the substrate, the second flat layer is at least positioned in the display area, and the second passivation layer is positioned on one side of the second flat layer away from the substrate;

The second passivation layer further includes a third portion located in the display region, the third portion of the second passivation layer including at least one passivation fault; the anode layer further comprises at least one anode located in the display area, and the orthographic projection of the anode on the substrate is located in the orthographic projection of the passivation fault on the substrate;

A pixel defining layer on a side of the anode layer remote from the substrate, the pixel defining layer including at least one pixel opening; the pixel opening is arranged corresponding to the anode;

The display panel comprises a groove penetrating from the pixel defining layer to the second flat layer, wherein the groove is positioned on at least one side of the pixel opening; the edge part of the passivation fault extends out of the side wall of the groove, and a gap is formed between one surface of the edge part of the passivation fault, which is close to the substrate, and the bottom of the groove.

8. The display panel of claim 7, further comprising:

a light emitting layer located at a side of the anode layer away from the substrate, the light emitting layer including a light emitting portion located in the pixel opening; the cathode layer is positioned on one side of the light-emitting layer and the pixel defining layer away from the substrate;

the display panel further includes: a first carrier common layer between the anode layer and the light emitting layer, and/or a second carrier common layer between the light emitting layer and the cathode layer;

The portion of the first carrier common layer and/or the second carrier common layer located in the groove is broken at the edge portion of the passivation fault extending, and the portion of the cathode layer located in the groove is broken at the edge portion of the passivation fault extending.

9. The display panel according to claim 8, wherein the light-emitting layer includes a first light-emitting layer, a connection layer, and a second light-emitting layer which are sequentially stacked, the first light-emitting layer is adjacent to the anode layer, and a portion of the connection layer in the groove is broken at an edge portion where the passivation layer protrudes.

10. The display panel of claim 6, further comprising:

the first packaging layer is positioned on one side of the cathode layer away from the substrate;

the second packaging layer is positioned on one side of the first packaging layer away from the substrate;

the third packaging layer is positioned on one side of the second packaging layer away from the substrate;

The boundary of the second packaging layer is positioned at one side of the first blocking dam close to the display area, and the first packaging layer and the third packaging layer cover the display area and the peripheral area.

11. The display panel of claim 1, wherein the first passivation layer is silicon nitride and has a thickness of 2500 angstroms to 3000 angstroms.

12. The display panel of claim 1, wherein the second passivation layer is silicon nitride and has a thickness of 500 to 2500 angstroms.

13. A display device comprising the display panel according to any one of claims 1 to 12.