CN110649069B - Display panel and manufacturing method thereof - Google Patents
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- CN110649069B CN110649069B CN201910822476.6A CN201910822476A CN110649069B CN 110649069 B CN110649069 B CN 110649069B CN 201910822476 A CN201910822476 A CN 201910822476A CN 110649069 B CN110649069 B CN 110649069B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/80—Constructional details
- H10K59/88—Dummy elements, i.e. elements having non-functional features
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- H—ELECTRICITY
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
Abstract
The present disclosure provides a display panel and a manufacturing method of the display panel, the display panel includes a plurality of sub-pixels arranged in an array, the sub-pixels include: the thin film transistor comprises an interlayer insulating layer and a source drain electrode arranged on the interlayer insulating layer; a planarization layer covering the thin film transistor; the pixel definition layer is arranged on one side, far away from the thin film transistor, of the flat layer, and a first through hole penetrating through the pixel definition layer and the flat layer is formed in the surface of the pixel definition layer; the first passivation protection layer is arranged on one side, far away from the flat layer, of the pixel definition layer and is filled into the first connecting hole so as to enable the pixel definition layer adjacent to the sub-pixels to be separated from the flat layer, and therefore moisture and oxygen are prevented from invading the display device of the display panel through the pixel definition layer and the flat layer, the signal resistance of the display panel is improved, meanwhile, the packaging range of the display panel packaging layer can be reduced, and therefore the frame width of the display panel is reduced.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display panel and a manufacturing method of the display panel.
Background
With the rapid development of display technology, various light and thin flat display panels have been introduced. Device lifetime is an important consideration in the industrialization of Display panels such as Liquid Crystal Display (LCD) and Organic Light-Emitting Diode (OLED), which are adversely affected by moisture and oxygen. If the moisture and oxygen can be effectively blocked, the generation of black spots can be suppressed, and the service life of the display panel can be greatly prolonged, which depends on the effective encapsulation of the device.
The conventional display panel may cover the thin film encapsulation layer to block permeation of moisture, oxygen, and the like from the outside. The conventional thin film encapsulation layer has a configuration in which inorganic layers and organic layers are alternately stacked. However, in general, a thin film encapsulation layer is integrally formed with a display panel, for example, the thin film encapsulation layer encapsulates a buffer layer, a thin film transistor, a planarization layer, and a plurality of display devices such as LCD or OLED on a substrate, and moisture and oxygen can still penetrate into the interior of the display devices through the film layers such as organic layers of the display panel, causing the display devices to rapidly decay.
In summary, the conventional display panel has a problem that moisture and oxygen invade into the display device due to imperfect film encapsulation. Therefore, it is desirable to provide a display panel and a method for manufacturing the display panel to improve the defect.
Disclosure of Invention
The embodiment of the disclosure provides a display panel and a manufacturing method of the display panel, which are used for solving the problem that water vapor and oxygen invade a display device due to the fact that the existing display panel is incomplete in film packaging.
The embodiment of the present disclosure provides a display panel, including a plurality of sub-pixels arranged in an array, where the sub-pixels include:
the thin film transistor comprises an interlayer insulating layer and a source drain electrode arranged on the interlayer insulating layer;
a planarization layer covering the thin film transistor;
the pixel defining layer is arranged on one side, far away from the thin film transistor, of the flat layer, and a first through hole penetrating through the pixel defining layer and the flat layer is formed in the surface of the pixel defining layer; and
the first passivation protection layer is arranged on one side, far away from the flat layer, of the pixel definition layer and is filled into the first through hole so as to block the pixel definition layer adjacent to the sub-pixel from the flat layer.
According to an embodiment of the disclosure, the display panel further includes an encapsulation layer, the first passivation layer covers the sidewall and the bottom of the first via hole, and forms a hollow portion, and the encapsulation layer fills the hollow portion.
According to an embodiment of the present disclosure, the display panel further includes a second passivation layer, a gap is formed between the source and drain electrodes of any adjacent sub-pixel, the second passivation layer covers the gap, and the first passivation layer is in contact with the second passivation layer through the first through hole.
According to an embodiment of the present disclosure, two ends of the second passivation layer extend to the surface of the source/drain electrode of the adjacent sub-pixel.
According to an embodiment of the present disclosure, a projection of the first passivation protection layer on the interlayer insulating layer in the thickness direction of the display panel coincides with a projection of the second passivation protection layer on the interlayer insulating layer in the thickness direction of the display panel.
According to an embodiment of the present disclosure, the first passivation layer and the second passivation layer are made of silicon oxide, silicon nitride, or a mixture thereof.
According to an embodiment of the present disclosure, the display panel further includes support pillars spaced apart from each other on a side of the first passivation layer away from the pixel defining layer.
The embodiment of the disclosure further provides a manufacturing method of a display panel, including:
providing a flexible substrate, and forming a thin film transistor on the flexible substrate, wherein the thin film transistor comprises an interlayer insulating layer and a source drain electrode arranged on the interlayer insulating layer;
sequentially forming a flat layer, an anode wiring layer and a pixel defining layer on the thin film transistor;
etching the flat layer and the pixel definition layer to form a first through hole penetrating through the flat layer and the pixel definition layer; and
depositing and patterning a first passivation protection layer on the pixel defining layer, and filling the first passivation protection layer into the first through hole.
According to an embodiment of the disclosure, before the planarization layer is deposited and formed, a second passivation protection layer is deposited and formed on the thin film transistor, and the second passivation protection layer covers a gap formed between adjacent source and drain electrodes.
According to an embodiment of the present disclosure, a projection of the first passivation protection layer on the interlayer insulating layer in the thickness direction of the display panel coincides with a projection of the second passivation protection layer on the interlayer insulating layer in the thickness direction of the display panel.
The beneficial effects of the disclosed embodiment are as follows: according to the display panel, the first passivation protection layer is arranged on the pixel definition layer, and the first passivation protection layer is filled into the first through hole penetrating through the pixel definition layer and the flat layer, so that the pixel definition layer and the flat layer adjacent to the sub-pixel are isolated, and therefore water vapor and oxygen are prevented from invading display devices such as thin film transistors of the display panel through the pixel definition layer and the flat layer.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some of the disclosed embodiments, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the disclosure;
fig. 2 is a schematic flow chart illustrating a manufacturing method of a display panel according to a second embodiment of the disclosure.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the disclosure may be practiced. Directional phrases used in this disclosure, such as [ upper ], [ lower ], [ front ], [ back ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terms used are used for the purpose of illustration and understanding of the present disclosure, and are not used to limit the present disclosure. In the drawings, elements having similar structures are denoted by the same reference numerals.
The disclosure is further described with reference to the following drawings and specific embodiments:
the first embodiment is as follows:
the present disclosure provides a display panel, which is described in detail with reference to fig. 1.
As shown in fig. 1, fig. 1 is a schematic cross-sectional structure diagram of a display panel 100 according to an embodiment of the disclosure, where the display panel 100 includes a first flexible substrate 110, a first buffer layer 120, a second flexible substrate 111, a second buffer layer 121, and a plurality of sub-pixels stacked in sequence, only two adjacent sub-pixels a1 and a2 are shown in fig. 1, and each of the sub-pixels includes a thin film transistor 130, a planarization layer 140, an anode wiring layer 150, a pixel definition layer 160, and a first passivation protection layer 170.
Specifically, as shown in fig. 1, the thin film transistor 130 includes a channel layer 131, a first gate insulating layer 132 covering the channel layer 131, a first gate line layer 133 disposed on the first gate insulating layer 132, a second gate insulating layer 134 covering the first gate line layer 133, a second gate line layer 135 disposed on the second gate insulating layer 134, an interlayer insulating layer 136 covering the second gate line layer 135, and a source-drain electrode 137 disposed on the interlayer insulating layer 136, where the source-drain electrode 137 is in contact with the channel layer 131 through a via hole penetrating through the interlayer insulating layer 136, the second gate insulating layer 134, and the first gate insulating layer 132.
In this embodiment, the planarization layer 140 covers the thin film transistor 130, and the anode wiring layer 150 is disposed on the planarization layer 140 and contacts the source/drain electrode 137 through a second via hole penetrating the planarization layer 140. The pixel defining layer 160 is disposed on a side of the planarization layer 140 away from the thin film transistor 130, a first via hole 161 penetrating through the pixel defining layer 160 and the planarization layer 140 is formed from a surface of the pixel defining layer 160, and the first passivation layer 170 is disposed on a side of the pixel defining layer 160 away from the planarization layer 140 and fills the first via hole 170 to block the pixel defining layer 160 and the planarization layer 140 of the adjacent sub-pixel.
As shown in fig. 1, the pixel defining layer 160 and the planarization layer 140 of the adjacent sub-pixels a1 and a2 are disconnected by the first connection hole 161, and the first passivation layer 170 filling the first connection hole 161 covers the sidewall and the bottom of the first connection hole to block the pixel defining layer 160 and the planarization layer 140 of the adjacent sub-pixels, so as to prevent moisture and oxygen from invading the thin film transistor 130 and other display devices of the display panel 100 through the pixel defining layer 160 and the planarization layer 140, and improve the reliability of the display panel 100.
In this embodiment, the display panel 100 further includes an encapsulation layer (not shown), the first passivation layer 170 covers the sidewalls and the bottom of the first through hole 161 and forms a hollow portion 171, and the encapsulation layer fills the hollow portion 171.
In this embodiment, as shown in fig. 1, the display panel 100 further includes a second passivation layer 180, a gap is formed between the source/drain electrodes 137 of any adjacent sub-pixels, the second passivation protection layer 180 covers the gap, the first passivation protection layer 170 contacts the second passivation protection layer 180 through the first connection hole 161, the first passivation layer 170 fills the bottom of the first via hole 161 and the gap between the source and drain electrodes 137 of the adjacent sub-pixels to be covered by the second passivation layer 180, and the edges of the pixel defining layer 160 and the planarization layer 140 are covered by the first passivation layer 170 and the second passivation layer 180, so that the reliability of the package of the display panel 100 is improved, the range of the encapsulation layer beyond the display area of the display panel 100 can be effectively reduced, which is helpful for reducing the frame width of the display panel 100.
In some embodiments, two ends of the second passivation layer 180 further extend to the surfaces of the source and drain electrodes 137 of the adjacent sub-pixels, respectively, and the source and drain electrodes 137 are covered by the second passivation layer 180, so that the fox-searching thin film transistor 130 can be prevented from being invaded by water vapor and oxygen.
Preferably, a projection of the first passivation protection layer 170 on the interlayer insulating layer 136 along the thickness direction of the display panel 100 coincides with a projection of the second passivation protection layer 180 on the interlayer insulating layer 136 along the thickness direction of the display panel 100. Because the projections of the first passivation protection layer 170 and the second passivation protection layer 180 are overlapped, when the patterning process is performed on the first passivation protection layer 170 and the second passivation protection layer 180, the same mask plate can be adopted to respectively expose the first passivation protection layer 170 and the second passivation protection layer 180, so that the manufacturing and the use of the mask plate are reduced, the actual production cost is effectively reduced, and the production efficiency is improved.
Preferably, the first passivation layer and the second passivation layer are made of silicon oxide, silicon nitride or a mixture thereof, and the waterproof performance of the materials is utilized to effectively prevent water vapor and oxygen from entering the display device of the display panel 100.
In this embodiment, the display panel 100 further includes supporting pillars 190, the supporting pillars 190 are disposed at intervals on a side of the first passivation layer 170 away from the pixel defining layer 160, and the supporting pillars 190 are used for supporting a mask plate required when a light emitting layer of the display panel 100 is formed by evaporation. In some embodiments, the cross-sectional shape of the support posts 190 includes trapezoidal and rectangular.
The embodiment of the present disclosure provides a display panel 100, wherein a first passivation layer 170 is disposed on a pixel defining layer 160, and the first passivation layer 170 is filled into a first through hole 161 penetrating through the pixel defining layer 160 and a planarization layer 140 to block the pixel defining layer 160 and the planarization layer 140 of adjacent sub-pixels, so as to prevent moisture and oxygen from invading display devices such as a thin film transistor 130 of the display panel 100 through the pixel defining layer 160 and the planarization layer 140, and improve the reliability of the display panel 100, and at the same time, the packaging range of the packaging layer of the display panel 100 can be reduced, thereby reducing the frame width of the display panel 100.
Example two:
the embodiment of the disclosure further provides a method for manufacturing a display panel, which is described in detail below with reference to fig. 1 and 2.
As shown in fig. 2, fig. 2 is a schematic flow chart of a manufacturing method of a display panel according to an embodiment of the disclosure, the method including:
step S10: providing a flexible substrate 110, forming a thin film transistor 130 on the flexible substrate 110, wherein the thin film transistor 130 includes an interlayer insulating layer 136 and a source-drain electrode 137 disposed on the interlayer insulating layer 136.
Specifically, a first buffer layer 120, a second flexible substrate 111 and a second buffer layer 121 are further formed on the flexible substrate 110, the thin film transistor further includes a channel layer 131, a first gate insulating layer 132 covering the channel layer 131, a first gate line layer 133 disposed on the first gate insulating layer 132, a second gate insulating layer 134 covering the first gate line layer 133, and a second gate line layer 135 disposed on the second gate insulating layer 134, and the source-drain electrode 137 is in contact with the channel layer 131 through a via hole penetrating through the interlayer insulating layer 136, the second gate insulating layer 134 and the first gate insulating layer 132.
Step S20: a planarization layer 140, an anode wiring layer 150, and a pixel defining layer 160 are sequentially formed on the thin film transistor 130. The anode wiring layer 150 is disposed on the planarization layer 140 and contacts the source/drain electrodes 137 through via holes penetrating the planarization layer 140.
Step S30: the planarization layer 140 and the pixel definition layer 160 are etched to form a first via hole 161 penetrating through the planarization layer 140 and the pixel definition layer 160. As shown in fig. 1, the first via hole 161 separates the pixel defining layer 160 and the planarization layer 140 on the thin film transistor 130 to form a plurality of independent portions, each corresponding to one thin film transistor 130, that is, each corresponding to one sub-pixel.
Step S40: a first passivation protection layer 170 is deposited and patterned on the pixel defining layer 160, and the first passivation protection layer 170 is filled in the first via hole 161.
As shown in fig. 1, the first passivation layer 170 covers the sidewalls and the bottom of the first via hole 161 to block the adjacent pixel defining layer 160 and the flat layer 140, so as to prevent moisture and oxygen from entering the thin film transistor 130 of the display panel 100 and other display devices through the film layers such as the pixel defining layer 160 and the flat layer 140, thereby improving the reliability of the display panel 100.
In this embodiment, the display panel 100 further includes an encapsulation layer (not shown), the first passivation layer 170 covers the sidewalls and the bottom of the first through hole 161 and forms a hollow portion 171, and the encapsulation layer fills the hollow portion 171.
In this embodiment, before the planarization layer 140 is deposited, a second passivation protection layer 180 is deposited on the thin film transistor 130, the second passivation protection layer 180 covers a gap formed between adjacent source and drain electrodes 137, the first passivation protecting layer 170 contacts the second passivation protecting layer 180 through the first connecting hole 161, the first passivation layer 170 fills the bottom of the first via hole 161 and the gap between the source and drain electrodes 137 of the adjacent sub-pixels to be covered by the second passivation layer 180, and the edges of the pixel defining layer 160 and the planarization layer 140 are covered by the first passivation layer 170 and the second passivation layer 180, so that the reliability of the package of the display panel 100 is improved, the range of the encapsulation layer beyond the display area of the display panel 100 can be effectively reduced, which is helpful for reducing the frame width of the display panel 100.
In some embodiments, two ends of the second passivation layer 180 further extend to the surfaces of the source and drain electrodes 137 of the adjacent sub-pixels, respectively, and the source and drain electrodes 137 are covered by the second passivation layer 180, so that the fox-searching thin film transistor 130 can be prevented from being invaded by water vapor and oxygen.
Preferably, a projection of the first passivation protection layer 170 on the interlayer insulating layer 136 along the thickness direction of the display panel 100 coincides with a projection of the second passivation protection layer 180 on the interlayer insulating layer 136 along the thickness direction of the display panel 100. Because the projections of the first passivation protection layer 170 and the second passivation protection layer 180 are overlapped, when the patterning process is performed on the first passivation protection layer 170 and the second passivation protection layer 180, the same mask plate can be adopted to respectively expose the first passivation protection layer 170 and the second passivation protection layer 180, so that the manufacturing and the use of the mask plate are reduced, the actual production cost is effectively reduced, and the production efficiency is improved.
Preferably, the first passivation layer and the second passivation layer are made of silicon oxide, silicon nitride or a mixture thereof, and the waterproof performance of the materials is utilized to effectively prevent water vapor and oxygen from entering the display device of the display panel 100.
In this embodiment, the manufacturing method further includes: support posts 190 are coated and patterned on the first passivation layer 170, the support posts 190 are disposed at intervals on a side of the first passivation layer 170 away from the pixel defining layer 160, and the support posts 190 are used for supporting a mask plate required for forming a light emitting layer of the display panel 100 by evaporation. In some embodiments, the cross-sectional shape of the support post includes trapezoidal and rectangular.
The embodiment of the present disclosure provides a method for manufacturing a display panel 100, wherein a first passivation layer 170 is disposed on a pixel defining layer 160, and the first passivation layer 170 is filled into a first connecting hole 161 penetrating through the pixel defining layer 160 and a planarization layer 140, so as to block the pixel defining layer 160 and the planarization layer 140 of adjacent sub-pixels, thereby preventing water vapor and oxygen from invading display devices such as a thin film transistor 130 of the display panel 100 through the pixel defining layer 160 and the planarization layer 140, and while improving the reliability of the display panel 100, the encapsulation range of the encapsulation layer of the display panel 100 can be reduced, thereby reducing the frame width of the display panel 100.
In summary, although the present disclosure has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present disclosure, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, so that the scope of the present disclosure is defined by the appended claims.
Claims (5)
1. A display panel comprising a plurality of sub-pixels arranged in an array, the sub-pixels comprising:
the thin film transistor comprises an interlayer insulating layer and a source drain electrode arranged on the interlayer insulating layer;
a planarization layer covering the thin film transistor;
the pixel defining layer is arranged on one side, far away from the thin film transistor, of the flat layer, and a first through hole penetrating through the pixel defining layer and the flat layer is formed in the surface of the pixel defining layer;
the first passivation protection layer is arranged on one side, far away from the flat layer, of the pixel definition layer and is filled into the first through hole so as to block the pixel definition layer and the flat layer of the adjacent sub-pixels; and
a second passivation layer, wherein a gap is formed between the source and drain electrodes of any adjacent sub-pixel, the second passivation layer covers the gap, and the first passivation layer is in contact with the second passivation layer through the first through hole;
the display panel further comprises an encapsulation layer, the first passivation protection layer covers the side wall and the bottom of the first connecting hole and forms a hollow part, and the hollow part is filled in the encapsulation layer.
2. The display panel according to claim 1, wherein both ends of the second passivation protection layer extend to the source and drain electrode surfaces of the adjacent sub-pixels.
3. The display panel according to claim 1, wherein a projection of the first passivation protection layer on the interlayer insulating layer in the thickness direction of the display panel coincides with a projection of the second passivation protection layer on the interlayer insulating layer in the thickness direction of the display panel.
4. The display panel of claim 1, wherein the first passivation protection layer and the second passivation protection layer are made of silicon oxide, silicon nitride or a mixture thereof.
5. The display panel of claim 1, further comprising support posts spaced apart on a side of the first passivation protection layer away from the pixel definition layer.
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| CN113745252B (en) * | 2021-08-31 | 2023-07-04 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN114695494A (en) * | 2022-03-23 | 2022-07-01 | 深圳市华星光电半导体显示技术有限公司 | OLED display panel and manufacturing method thereof |
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| KR20070059683A (en) * | 2005-12-07 | 2007-06-12 | 삼성에스디아이 주식회사 | A method for preparing a flat panel display device and a flat panel display device prepared using the method |
| CN109037277A (en) * | 2018-07-17 | 2018-12-18 | 深圳市华星光电技术有限公司 | A kind of preparation method and OLED display panel, display device of OLED display panel |
| CN110112317A (en) * | 2019-05-23 | 2019-08-09 | 京东方科技集团股份有限公司 | Display device, flexible display panels and its manufacturing method |
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| KR20070059683A (en) * | 2005-12-07 | 2007-06-12 | 삼성에스디아이 주식회사 | A method for preparing a flat panel display device and a flat panel display device prepared using the method |
| CN109037277A (en) * | 2018-07-17 | 2018-12-18 | 深圳市华星光电技术有限公司 | A kind of preparation method and OLED display panel, display device of OLED display panel |
| CN110112317A (en) * | 2019-05-23 | 2019-08-09 | 京东方科技集团股份有限公司 | Display device, flexible display panels and its manufacturing method |
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