CN118074701B - Automatic edge detection voltage level conversion circuit - Google Patents

Abstract

The invention provides an automatic edge detection voltage level conversion circuit, which comprises an automatic edge locking detection module and a bidirectional transmission gate module; the bidirectional transmission gate module is provided with a first signal end, a second signal end and a control end, wherein the first signal end is used for inputting or outputting a first signal A, and the second signal end is used for inputting or outputting a second signal B; the automatic edge locking detection module is provided with a first detection end, a second detection end and a judgment signal output end, wherein the first detection end is connected with the first signal end, the second detection end is connected with the second signal end, and the judgment signal output end is connected with the control end. The invention can automatically identify and configure the transmission direction of the bidirectional transmission gate module, and has simple circuit and easy realization.

Description

Automatic edge detection voltage level conversion circuit

Technical Field

The invention relates to the technical field of bus communication, in particular to an automatic edge detection voltage level conversion circuit.

Background

The development of very large scale integrated circuit technology has enabled complex systems on chip, where modules of different functions, such as analog circuits, digital circuits, passive components, etc., are integrated into a single chip. Different functional modules have different performances and constraints, and can be operated with different voltages to realize the optimal performance-power consumption ratio. In current system-on-chip designs, it is common to have two or more voltage domains in a single chip. In order to solve the problem of uncoordinated input-output logic to achieve normal communication between different voltage domains inside a chip, a voltage level conversion circuit is required to convert a logic signal from one voltage level to another voltage level.

As shown in fig. 1, the conventional bidirectional voltage level conversion circuit generates 2 paths of control signals sa_out and sb_out through two inverters INV3a and INV3b for controlling the transmission direction of bidirectional voltage level conversion. The existing bidirectional voltage level conversion circuit realizes bidirectional voltage level conversion, but needs to set additional direction signals to control the transmission direction, and has complex circuit structure and difficult realization.

Disclosure of Invention

The present invention has been made in view of the above problems, and an object of the present invention is to provide an automatic edge detection voltage level conversion circuit capable of automatically identifying and configuring a transmission direction of a bidirectional transmission gate module, which is simple and easy to implement.

The invention discloses an automatic edge detection voltage level conversion circuit, which specifically comprises an automatic edge locking detection module and a bidirectional transmission gate module;

The bidirectional transmission gate module is provided with a first signal end, a second signal end and a control end, wherein the first signal end is used for inputting or outputting a first signal A, and the second signal end is used for inputting or outputting a second signal B; the automatic edge locking detection module is provided with a first detection end, a second detection end and a judgment signal output end, wherein the first detection end is connected with the first signal end, the second detection end is connected with the second signal end, and the judgment signal output end is connected with the control end.

Further, the automatic edge locking detection module automatically detects the rising edge of the voltage level of the first signal end or the second signal end, generates a judgment signal after judging the transmission direction of the bidirectional transmission gate module, inputs the judgment signal to the control end of the bidirectional transmission gate module, and controls the transmission direction of the bidirectional transmission gate module.

Further, the automatic edge locking detection module comprises a power supply voltage generation module, a first signal end edge detection module and a second signal end edge detection module;

The power supply voltage generating module respectively generates a first power supply voltage VDD and a second power supply voltage VDD1, the first signal end edge detecting module is provided with a first detecting end, a first judging signal output end, a first power supply input end and a second power supply input end, and the first power supply input end and the second power supply input end respectively receive the first power supply voltage VDD and the second power supply voltage VDD1; the second signal end edge detection module is provided with a second detection end, a second judgment signal output end, a third power input end and a fourth power input end, and the third power input end and the fourth power input end respectively receive a first power voltage VDD and a second power voltage VDD1; the first judging signal output end of the first signal end edge detection module and the second judging signal output end of the second signal end edge detection module jointly form a judging signal output end of the automatic edge locking detection module.

Further, the power supply voltage generating module comprises a low dropout linear regulator LDO1, a switch S1 and a first capacitor C1;

The voltage output end of the low dropout linear regulator LDO1 generates a first power supply voltage VDD, the first end of the switch S1 is connected with the first power supply voltage VDD, the control end of the switch S1 receives a switch control signal, the second end of the switch S1 is connected with the first end of the first capacitor C1 and is used as the output end of the power supply voltage generating module for generating a second power supply voltage VDD1, and the second end of the first capacitor C1 is grounded.

Further, the first signal-end edge detection module includes a second capacitor C2a, a first inverter INV1a, a second inverter INV1b, a third inverter INV1C, a fourth inverter INV1D, a fifth inverter INV1e, a first transistor PM1, a second transistor NM1a, a third transistor NM1b, and a first D flip-flop DFF1;

The input end of the first inverter INV1a is used as the first detection end of the first signal end edge detection module, the first signal A is received, the output end of the first inverter INV1a is connected with the grid electrode of the first transistor PM1 and the grid electrode of the second transistor NM1a, the source electrode of the first transistor PM1 receives the second power supply voltage VDD1, the drain electrode of the first transistor PM1 is connected with the drain electrode of the second transistor NM1a, the drain electrode of the third transistor NM1b and the input end of the second inverter INV1b, the source electrode of the second transistor NM1a and the source electrode of the third transistor NM1b are grounded, the output end of the second inverter INV1b is connected with the input end of the third inverter INV1C, the output end of the third inverter INV1C is connected with the input end of the fourth inverter INV1D and the clock end of the first D trigger DFF1, the output end of the fourth inverter INV1D is connected with the first end of the second capacitor C2a and the input end of the fifth inverter INV1e, the source electrode of the second capacitor NM1b is connected with the first data output end of the first trigger signal F1 b is judged, the output end of the third inverter die of the third capacitor DFF 1D is connected with the first data output end of the first trigger signal of the first signal end of the first trigger output end of the third inverter NM1b is judged; the first transistor PM1 is a PMOS transistor, and the second transistor NM1a and the third transistor NM1b are NMOS transistors.

Further, the second signal-end edge detection module includes a third capacitor C2b, a sixth inverter INV2a, a seventh inverter INV2b, an eighth inverter INV2C, a ninth inverter INV2D, a tenth inverter INV2e, a fourth transistor PM2, a fifth transistor NM2a, a sixth transistor NM2b, and a second D flip-flop DFF2;

The input end of the sixth inverter INV2a is used as the second detection end of the second signal end edge detection module, the second signal B is received, the output end of the sixth inverter INV2a is connected with the grid electrode of the fourth transistor PM2 and the grid electrode of the fifth transistor NM2a, the source electrode of the fourth transistor PM2 receives the second power supply voltage VDD1, the drain electrode of the fourth transistor PM2 is connected with the drain electrode of the fifth transistor NM2a, the drain electrode of the sixth transistor NM2B and the input end of the seventh inverter INV2B, the source electrode of the fifth transistor NM2a and the source electrode of the sixth transistor NM2B are grounded, the output end of the seventh inverter INV2B is connected with the input end of the eighth inverter INV2C, the output end of the eighth inverter INV2C is connected with the clock end of the second D trigger DFF2, the output end of the ninth inverter INV2D is connected with the first end of the third capacitor C2B and the input end of the tenth inverter INV2e, the output end of the third capacitor C2B is connected with the output end of the second trigger signal F2B, and the output end of the reset signal of the second inverter INV2B is connected with the second trigger end of the second signal B is judged.

Further, the fourth transistor PM2 is a PMOS transistor, and the fifth transistor NM2a and the sixth transistor NM2b are NMOS transistors.

Further, the bidirectional transmission gate module includes an eleventh inverter INV3a, a twelfth inverter INV3d, a first gate inverter INV3b, and a second gate inverter INV3c;

the input end of the eleventh inverter INV3a is used as a first signal end of the bidirectional transmission gate module, the output end of the eleventh inverter INV3a is connected with the input end of the first gating inverter INV3b, the output end of the first gating inverter INV3b is connected with a second signal end, the control end of the first gating inverter INV3b is used as a first control end of the bidirectional transmission gate module, and the first judgment signal SA_out is received; the input end of the twelfth inverter INV3d is used as the second signal end of the bidirectional transmission gate module, the output end of the twelfth inverter INV3d is connected with the input end of the second gating inverter INV3c, the output end of the second gating inverter INV3c is connected with the first signal end, the control end of the second gating inverter INV3c is used as the second control end of the bidirectional transmission gate module, the second judgment signal sb_out is received, and the first control end and the second control end of the bidirectional transmission gate module jointly form the control end of the bidirectional transmission gate module.

Further, when the first judging signal sa_out is at a high level and the second judging signal sb_out is at a low level, the first gating inverter INV3b is controlled to operate, the second gating inverter INV3c is not operated, the bidirectional transmission gate module is controlled to be in a first transmission direction, and signals are transmitted from the first signal end to the second signal end; when the first judging signal sa_out is at a low level and the second judging signal sb_out is at a high level, the first gating inverter INV3b is controlled to be inactive and the second gating inverter INV3c is controlled to be active, and the bidirectional transmission gate module is controlled to be in a second transmission direction, so that signals are transmitted from the second signal terminal to the first signal terminal.

Further, the first gate inverter INV3b and the second gate inverter INV3c include a thirteenth inverter INV4a, a fourteenth inverter INV4b, a seventh transistor PM4b, an eighth transistor PM4c, a ninth transistor NM4b, and a tenth transistor NM4c, respectively;

The input end of the thirteenth inverter INV4a is used as the control end of the gating inverter, the output end of the thirteenth inverter INV4a is connected with the input end of the fourteenth inverter INV4b and the gate of the seventh transistor PM4b, the output end of the fourteenth inverter INV4b is connected with the gate of the ninth transistor NM4b, the gate of the eighth transistor PM4c is connected with the gate of the tenth transistor NM4c and is used as the input end of the gating inverter, the source of the eighth transistor PM4c is connected with the second power supply voltage, the drain of the eighth transistor PM4c is connected with the source of the seventh transistor PM4b, the drain of the seventh transistor PM4b is connected with the drain of the ninth transistor NM4b and is used as the output end of the gating inverter, the source of the ninth transistor NM4b is connected with the drain of the tenth transistor NM4c, and the source of the tenth transistor NM4c is grounded.

Further, the seventh transistor PM4b and the eighth transistor PM4c are PMOS transistors, and the ninth transistor NM4b and the tenth transistor NM4c are NMOS transistors.

The beneficial effects of the invention are as follows:

(1) The invention provides an automatic edge detection voltage level conversion circuit, which can automatically identify and configure the transmission direction of a bidirectional transmission gate module by utilizing an automatic edge locking detection module, and is simple in circuit and easy to realize.

(2) The invention provides an automatic edge locking detection module, which has simple circuit, can automatically identify and configure the transmission direction of a bidirectional transmission gate module only by adopting a transistor, an inverter and a D trigger, and is easy to realize.

(3) The application provides a gating inverter which only adopts four transistors and two inverters, and has simple circuit and easy realization.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a circuit diagram of a conventional bidirectional voltage level conversion circuit;

FIG. 2 is a block diagram of an automatic edge detection voltage level conversion circuit according to the present invention;

FIG. 3 is a circuit diagram of an automatic edge detection voltage level shifter circuit according to the present invention;

FIG. 4 is a diagram showing waveforms of an automatic edge lock detection module according to the present invention;

FIG. 5 is a circuit diagram of a gated inverter according to the present invention;

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two, but does not exclude the case of at least one.

The invention will be further described with reference to the drawings and the specific examples.

Examples

As shown in fig. 2, the present application provides an automatic edge detection voltage level conversion circuit. The automatic edge detection voltage level conversion circuit specifically comprises an automatic edge locking detection module and a bidirectional transmission gate module.

The bidirectional transmission gate module is provided with a first signal end, a second signal end and a control end, wherein the first signal end is used for inputting or outputting a first signal A, and the second signal end is used for inputting or outputting a second signal B; the automatic edge locking detection module is provided with a first detection end, a second detection end and a judgment signal output end, wherein the first detection end is connected with the first signal end, the second detection end is connected with the second signal end, and the judgment signal output end is connected with the control end.

The automatic edge locking detection module automatically detects the voltage level edge of the first signal end or the second signal end, generates a judging signal after judging the transmission direction of the bidirectional transmission gate module, and inputs the judging signal to the control end of the bidirectional transmission gate module to control the transmission direction of the bidirectional transmission gate module.

Specifically, when the first signal A is input, the voltage level of the first signal end changes, and after the automatic edge locking detection module detects the rising edge of the voltage level of the first signal end, the bidirectional transmission gate module is controlled to be in a first transmission direction, so that signals are transmitted from the first signal end to the second signal end; when the second signal B is input, the voltage level of the second signal end changes, and after the automatic edge locking detection module detects the rising edge of the voltage level of the second signal end, the bidirectional transmission gate module is controlled to be in a second transmission direction, so that signals are transmitted from the second signal end to the first signal end.

In the application, the automatic edge detection voltage level conversion circuit utilizes the automatic edge locking detection module, can automatically identify and configure the transmission direction of the bidirectional transmission gate module, and has simple circuit and easy realization.

Examples

As shown in fig. 3, the present application further provides a circuit configuration diagram of an automatic edge detection voltage level conversion circuit.

The automatic edge locking detection module comprises a power supply voltage generation module, a first signal end edge detection module and a second signal end edge detection module. The power supply voltage generating module respectively generates a first power supply voltage VDD and a second power supply voltage VDD1, and the first signal end edge detecting module is provided with a first detecting end, a first judging signal output end, a first power supply input end and a second power supply input end, wherein the first power supply input end and the second power supply input end respectively receive the first power supply voltage VDD and the second power supply voltage VDD1. The second signal end edge detection module is provided with a second detection end, a second judgment signal output end, a third power input end and a fourth power input end, and the third power input end and the fourth power input end respectively receive a first power voltage VDD and a second power voltage VDD1. The first judging signal output end of the first signal end edge detection module and the second judging signal output end of the second signal end edge detection module jointly form a judging signal output end of the automatic edge locking detection module.

The first signal end edge detection module detects a voltage level edge of the first signal end based on the first power supply voltage VDD and the second power supply voltage VDD1, and generates a first judgment signal sa_out. The second signal end edge detection module detects the voltage level edge of the second signal end based on the first power supply voltage VDD and the second power supply voltage VDD1, and generates a second judgment signal sb_out.

Specifically, the power supply voltage generating module includes a low dropout linear regulator LDO1, a switch S1, and a first capacitor C1.

The voltage output end of the low dropout linear regulator LDO1 generates a first power supply voltage VDD, a first end of the switch S1 is connected with the first power supply voltage VDD, a control end of the switch S1 receives a switch control signal, a second end of the switch S1 is connected with the first end of the first capacitor C1 and is used as an output end of the power supply voltage generating module for generating a second power supply voltage VDD1, and a second end of the first capacitor C1 is grounded.

The first signal-end edge detection module includes a second capacitor C2a, a first inverter INV1a, a second inverter INV1b, a third inverter INV1C, a fourth inverter INV1D, a fifth inverter INV1e, a first transistor PM1, a second transistor NM1a, a third transistor NM1b, and a first D flip-flop DFF1.

The input end of the first inverter INV1a is used as the first detection end of the first signal end edge detection module, the output end of the first inverter INV1a is connected with the gate of the first transistor PM1 and the gate of the second transistor NM1a, the source of the first transistor PM1 receives the second power supply voltage VDD1, the drain of the first transistor PM1 is connected with the drain of the second transistor NM1a, the drain of the third transistor NM1b and the input end of the second inverter INV1b, the source of the second transistor NM1a and the source of the third transistor NM1b are grounded, the output end of the second inverter INV1b is connected with the input end of the third inverter INV1C, the output end of the third inverter INV1C is connected with the input end of the fourth inverter INV1D and the clock end of the first D trigger DFF1, the output end of the fourth inverter INV1D is connected with the first end of the second capacitor C2a and the input end of the fifth inverter INV1e, the source of the second capacitor C2b is connected with the first end of the third trigger DFF 1b, the output end of the second inverter DFF 1b is connected with the first data output end of the first trigger signal is judged, and the output end of the third trigger signal is connected with the first end of the third capacitor DFF 1b is connected with the first output end of the first trigger signal end of the first trigger output end of the third trigger signal is judged.

In a preferred embodiment, the first transistor PM1 is a PMOS transistor, and the second transistor NM1a and the third transistor NM1b are NMOS transistors.

The second signal-end edge detection module includes a third capacitor C2b, a sixth inverter INV2a, a seventh inverter INV2b, an eighth inverter INV2C, a ninth inverter INV2D, a tenth inverter INV2e, a fourth transistor PM2, a fifth transistor NM2a, a sixth transistor NM2b, and a second D flip-flop DFF2.

The input end of the sixth inverter INV2a is used as the second detection end of the second signal end edge detection module, the second signal B is received, the output end of the sixth inverter INV2a is connected with the gate of the fourth transistor PM2 and the gate of the fifth transistor NM2a, the source of the fourth transistor PM2 receives the second power supply voltage VDD1, the drain of the fourth transistor PM2 is connected with the drain of the fifth transistor NM2a, the drain of the sixth transistor NM2B and the input end of the seventh inverter INV2B, the source of the fifth transistor NM2a and the source of the sixth transistor NM2B are grounded, the output end of the seventh inverter INV2B is connected with the input end of the eighth inverter INV2C, the output end of the eighth inverter INV2C is connected with the input end of the ninth inverter INV2D and the clock end of the second D flip-flop DFF2, the output end of the ninth inverter INV2D is connected with the first end of the third capacitor C2 e and the input end of the tenth inverter INV2e, the source of the third capacitor C2B is connected with the output end of the second flip-flop DFF 2B, the output end of the reset signal is connected with the second signal B is connected with the output end of the second flip-flop DFF 2D, and the output end of the reset signal is judged.

In a preferred embodiment, the fourth transistor PM2 is a PMOS transistor, and the fifth transistor NM2a and the sixth transistor NM2b are NMOS transistors.

When the automatic edge locking detection module does not work, the reset signal Rst is controlled to be at a low level, the first D trigger DFF1 and the second D trigger DFF2 are reset, the first judgment signal SA_out and the second judgment signal SB_out are caused to be at a low level, and the bidirectional transmission gate module is controlled to be closed.

When the automatic edge locking detection module works, the reset signal Rst is controlled to be in a high level, and the first D trigger DFF1 and the second D trigger DFF2 work; meanwhile, the switch S1 is controlled to be turned on for a preset time through the switch control signal, the switch S1 is turned on briefly, and the first power supply voltage VDD of the low dropout linear regulator LDO1 charges the first capacitor C1, so that the second power supply voltage VDD1 is equal to the first power supply voltage VDD.

When the first signal a is input, the voltage level of the first signal end is changed from low level to high level, the first transistor PM1 is turned on, the signal A2 generated by the drain electrode of the first transistor PM1 is changed to high level, the signal sa_in of high level is generated after being shaped by the two-stage inverter, and is input to the clock end of the first D flip-flop DFF1, and then the first judgment signal sa_out generated by the first D flip-flop DFF1 is changed to high level; in addition, after the signal sa_in is shaped by the two-stage inverter, the third transistor NM1B is controlled to be turned on, the signal A2 is pulled down, the second power voltage VDD1 is discharged due to the conduction of the first transistor PM1, the second power voltage VDD1 is pulled down, the signal B2 is at a low level, the second determination signal sb_out is at a low level, and the operation waveform diagram is shown in fig. 4.

Similarly, when the second signal B is input, the voltage level of the second signal terminal changes from low level to high level, the fourth transistor PM2 is turned on, the signal B2 generated by the drain of the fourth transistor PM2 changes to high level, the signal sb_in generated by the shaping of the two-stage inverter is input to the clock terminal of the second D flip-flop DFF2, and the second judgment signal sb_out generated by the second D flip-flop DFF2 changes to high level; in addition, after the signal sb_in is shaped by the two-stage inverter, the sixth transistor NM2B is controlled to be turned on, the signal B2 is pulled down, and the second power voltage VDD1 is discharged due to the conduction of the fourth transistor PM2, the second power voltage VDD1 is pulled down, so that the signal A2 is at a low level, and the first determination signal sa_out is at a low level.

When the first judging signal SA_out is at a high level and the second judging signal SB_out is at a low level, controlling the bidirectional transmission gate module to be in a first transmission direction, and transmitting signals from the first signal end to the second signal end; when the first judging signal SA_out is at a low level and the second judging signal SB_out is at a high level, the bidirectional transmission gate module is controlled to be in a second transmission direction, and signals are transmitted from the second signal end to the first signal end.

Further, as shown in fig. 3, the automatic edge detection voltage level conversion circuit further includes a bidirectional transmission gate module. The bidirectional transmission gate module specifically includes an eleventh inverter INV3a, a twelfth inverter INV3d, a first gate inverter INV3b, and a second gate inverter INV3c.

The input end of the eleventh inverter INV3a is used as a first signal end of the bidirectional transmission gate module, the output end of the eleventh inverter INV3a is connected with the input end of the first gating inverter INV3b, the output end of the first gating inverter INV3b is connected with a second signal end, the control end of the first gating inverter INV3b is used as a first control end of the bidirectional transmission gate module, and the first judgment signal SA_out is received; the input end of the twelfth inverter INV3d is used as the second signal end of the bidirectional transmission gate module, the output end of the twelfth inverter INV3d is connected with the input end of the second gating inverter INV3c, the output end of the second gating inverter INV3c is connected with the first signal end, the control end of the second gating inverter INV3c is used as the second control end of the bidirectional transmission gate module, the second judgment signal sb_out is received, and the first control end and the second control end of the bidirectional transmission gate module jointly form the control end of the bidirectional transmission gate module.

Specifically, when the first judging signal sa_out is at a high level and the second judging signal sb_out is at a low level, the first gating inverter INV3b is controlled to operate, the second gating inverter INV3c is not operated, the bidirectional transmission gate module is controlled to be in a first transmission direction, and signals are transmitted from the first signal end to the second signal end; when the first judging signal sa_out is at a low level and the second judging signal sb_out is at a high level, the first gating inverter INV3b is controlled to be inactive and the second gating inverter INV3c is controlled to be active, and the bidirectional transmission gate module is controlled to be in a second transmission direction, so that signals are transmitted from the second signal terminal to the first signal terminal.

In the application, the automatic edge locking detection module circuit is simple, and can automatically identify and configure the transmission direction of the bidirectional transmission gate module only by adopting the transistor, the inverter and the D trigger, thereby being easy to realize.

Examples

As shown in fig. 5, the present application further provides a circuit structure diagram of a gating inverter, which is used for implementing a first gating inverter INV3b and a second gating inverter INV3c, where the gating inverter is enabled to operate or not operate by a judging signal input to a control end.

The gate inverter includes thirteenth, fourteenth, seventh, eighth, ninth, and tenth inverters INV4a, INV4b, and PM4c, and seventh, eighth, and tenth transistors PM4b, PM 4c.

The input end of the thirteenth inverter INV4a is used as the control end of the gating inverter, the output end of the thirteenth inverter INV4a is connected with the input end of the fourteenth inverter INV4b and the gate of the seventh transistor PM4b, the output end of the fourteenth inverter INV4b is connected with the gate of the ninth transistor NM4b, the gate of the eighth transistor PM4c is connected with the gate of the tenth transistor NM4c and is used as the input end of the gating inverter, the source of the eighth transistor PM4c is connected with the second power supply voltage, the drain of the eighth transistor PM4c is connected with the source of the seventh transistor PM4b, the drain of the seventh transistor PM4b is connected with the drain of the ninth transistor NM4b and is used as the output end of the gating inverter, the source of the ninth transistor NM4b is connected with the drain of the tenth transistor NM4c, and the source of the tenth transistor NM4c is grounded.

In a preferred embodiment, the seventh and eighth transistors PM4b and PM4c are PMOS transistors, and the ninth and tenth transistors NM4b and NM4c are NMOS transistors.

In the application, the gate-controlled inverter only adopts four transistors and two inverters, so that the circuit is simple and easy to realize.

While the foregoing description illustrates and describes the preferred embodiments of the present invention, it is to be understood that the invention is not limited to the forms disclosed herein, but is not to be construed as limited to other embodiments, and is capable of numerous other combinations, modifications and environments and is capable of changes or modifications within the scope of the inventive concept as described herein, either as a result of the foregoing teachings or as a result of the knowledge or technology in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.

Claims (6)

1. An automatic edge detection voltage level conversion circuit is characterized by comprising an automatic edge locking detection module and a bidirectional transmission gate module;

The bidirectional transmission gate module is provided with a first signal end, a second signal end and a control end, wherein the first signal end is used for inputting or outputting a first signal A, and the second signal end is used for inputting or outputting a second signal B; the automatic edge locking detection module is provided with a first detection end, a second detection end and a judgment signal output end, wherein the first detection end is connected with the first signal end, the second detection end is connected with the second signal end, and the judgment signal output end is connected with the control end;

The automatic edge locking detection module automatically detects the voltage level rising edge of the first signal end or the second signal end, generates a judging signal after judging the transmission direction of the bidirectional transmission gate module, and inputs the judging signal to the control end of the bidirectional transmission gate module to control the transmission direction of the bidirectional transmission gate module;

The automatic edge locking detection module comprises a power supply voltage generation module, a first signal end edge detection module and a second signal end edge detection module;

The power supply voltage generating module respectively generates a first power supply voltage VDD and a second power supply voltage VDD1, the first signal end edge detecting module is provided with a first detecting end, a first judging signal output end, a first power supply input end and a second power supply input end, and the first power supply input end and the second power supply input end respectively receive the first power supply voltage VDD and the second power supply voltage VDD1; the second signal end edge detection module is provided with a second detection end, a second judgment signal output end, a third power input end and a fourth power input end, and the third power input end and the fourth power input end respectively receive a first power voltage VDD and a second power voltage VDD1; the first judging signal output end of the first signal end edge detection module and the second judging signal output end of the second signal end edge detection module jointly form a judging signal output end of the automatic edge locking detection module;

The power supply voltage generation module comprises a low dropout linear regulator LDO1, a switch S1 and a first capacitor C1;

the voltage output end of the low dropout linear regulator LDO1 generates a first power supply voltage VDD, the first end of the switch S1 is connected with the first power supply voltage VDD, the control end of the switch S1 receives a switch control signal, the second end of the switch S1 is connected with the first end of the first capacitor C1 and is used as the output end of the power supply voltage generating module for generating a second power supply voltage VDD1, and the second end of the first capacitor C1 is grounded;

The first signal-end edge detection module includes a second capacitor C2a, a first inverter INV1a, a second inverter INV1b, a third inverter INV1C, a fourth inverter INV1D, a fifth inverter INV1e, a first transistor PM1, a second transistor NM1a, a third transistor NM1b, and a first D flip-flop DFF1;

The input end of the first inverter INV1a is used as the first detection end of the first signal end edge detection module, the first signal A is received, the output end of the first inverter INV1a is connected with the grid electrode of the first transistor PM1 and the grid electrode of the second transistor NM1a, the source electrode of the first transistor PM1 receives the second power supply voltage VDD1, the drain electrode of the first transistor PM1 is connected with the drain electrode of the second transistor NM1a, the drain electrode of the third transistor NM1b and the input end of the second inverter INV1b, the source electrode of the second transistor NM1a and the source electrode of the third transistor NM1b are grounded, the output end of the second inverter INV1b is connected with the input end of the third inverter INV1C, the output end of the third inverter INV1C is connected with the input end of the fourth inverter INV1D and the clock end of the first D trigger DFF1, the output end of the fourth inverter INV1D is connected with the first end of the second capacitor C2a and the input end of the fifth inverter INV1e, the source electrode of the second capacitor NM1b is connected with the first data output end of the first trigger signal F1 b is judged, the output end of the third inverter die of the third capacitor DFF 1D is connected with the first data output end of the first trigger signal of the first signal end of the first trigger output end of the third inverter NM1b is judged;

The first transistor PM1 is a PMOS transistor, and the second transistor NM1a and the third transistor NM1b are NMOS transistors.

2. The automatic edge detection voltage level conversion circuit according to claim 1, wherein the second signal side edge detection module includes a third capacitor C2b, a sixth inverter INV2a, a seventh inverter INV2b, an eighth inverter INV2C, a ninth inverter INV2D, a tenth inverter INV2e, a fourth transistor PM2, a fifth transistor NM2a, a sixth transistor NM2b, and a second D flip-flop DFF2;

the input end of the sixth inverter INV2a is used as the second detection end of the second signal end edge detection module, the second signal B is received, the output end of the sixth inverter INV2a is connected with the grid electrode of the fourth transistor PM2 and the grid electrode of the fifth transistor NM2a, the source electrode of the fourth transistor PM2 receives the second power supply voltage VDD1, the drain electrode of the fourth transistor PM2 is connected with the drain electrode of the fifth transistor NM2a, the drain electrode of the sixth transistor NM2B and the input end of the seventh inverter INV2B, the source electrode of the fifth transistor NM2a and the source electrode of the sixth transistor NM2B are grounded, the output end of the seventh inverter INV2B is connected with the input end of the eighth inverter INV2C, the output end of the eighth inverter INV2C is connected with the clock end of the ninth inverter INV2D and the second D trigger DFF2, the output end of the ninth inverter INV2D is connected with the first end of the third capacitor C2B and the input end of the tenth inverter INV2e, the output end of the third capacitor C2B is connected with the second data output end of the second inverter INV2B is connected with the second trigger signal B2D, the output end of the reset signal is judged by the second trigger module;

The fourth transistor PM2 is a PMOS transistor, and the fifth transistor NM2a and the sixth transistor NM2b are NMOS transistors.

3. The automatic edge detection voltage level conversion circuit according to claim 2, wherein the bidirectional transmission gate module includes an eleventh inverter INV3a, a twelfth inverter INV3d, a first gating inverter INV3b, a second gating inverter INV3c;

the input end of the eleventh inverter INV3a is used as a first signal end of the bidirectional transmission gate module, the output end of the eleventh inverter INV3a is connected with the input end of the first gating inverter INV3b, the output end of the first gating inverter INV3b is connected with a second signal end, the control end of the first gating inverter INV3b is used as a first control end of the bidirectional transmission gate module, and the first judgment signal SA_out is received; the input end of the twelfth inverter INV3d is used as the second signal end of the bidirectional transmission gate module, the output end of the twelfth inverter INV3d is connected with the input end of the second gating inverter INV3c, the output end of the second gating inverter INV3c is connected with the first signal end, the control end of the second gating inverter INV3c is used as the second control end of the bidirectional transmission gate module, the second judgment signal sb_out is received, and the first control end and the second control end of the bidirectional transmission gate module jointly form the control end of the bidirectional transmission gate module.

4. The automatic edge detection voltage level shifting circuit of claim 3, wherein when the first judgment signal sa_out is at a high level and the second judgment signal sb_out is at a low level, the first gating inverter INV3b is controlled to operate and the second gating inverter INV3c is controlled to not operate, the bidirectional transmission gate module is controlled to be in a first transmission direction, and signals are transmitted from the first signal terminal to the second signal terminal; when the first judging signal sa_out is at a low level and the second judging signal sb_out is at a high level, the first gating inverter INV3b is controlled to be inactive and the second gating inverter INV3c is controlled to be active, and the bidirectional transmission gate module is controlled to be in a second transmission direction, so that signals are transmitted from the second signal terminal to the first signal terminal.

5. The automatic edge detection voltage level conversion circuit according to claim 4, wherein the first gate inverter INV3b, the second gate inverter INV3c include a thirteenth inverter INV4a, a fourteenth inverter INV4b, a seventh transistor PM4b, an eighth transistor PM4c, a ninth transistor NM4b, a tenth transistor NM4c, respectively;

The input end of the thirteenth inverter INV4a is used as the control end of the gating inverter, the output end of the thirteenth inverter INV4a is connected with the input end of the fourteenth inverter INV4b and the gate of the seventh transistor PM4b, the output end of the fourteenth inverter INV4b is connected with the gate of the ninth transistor NM4b, the gate of the eighth transistor PM4c is connected with the gate of the tenth transistor NM4c and is used as the input end of the gating inverter, the source of the eighth transistor PM4c is connected with the second power supply voltage, the drain of the eighth transistor PM4c is connected with the source of the seventh transistor PM4b, the drain of the seventh transistor PM4b is connected with the drain of the ninth transistor NM4b and is used as the output end of the gating inverter, the source of the ninth transistor NM4b is connected with the drain of the tenth transistor NM4c, and the source of the tenth transistor NM4c is grounded.

6. The automatic edge detection voltage level shift circuit according to claim 5, wherein the seventh transistor PM4b and the eighth transistor PM4c are PMOS transistors, and the ninth transistor NM4b and the tenth transistor NM4c are NMOS transistors.